fs.py revision 7877:19beb0676222
1298SN/A# Copyright (c) 2010 ARM Limited 22188SN/A# All rights reserved. 3298SN/A# 4298SN/A# The license below extends only to copyright in the software and shall 5298SN/A# not be construed as granting a license to any other intellectual 6298SN/A# property including but not limited to intellectual property relating 7298SN/A# to a hardware implementation of the functionality of the software 8298SN/A# licensed hereunder. You may use the software subject to the license 9298SN/A# terms below provided that you ensure that this notice is replicated 10298SN/A# unmodified and in its entirety in all distributions of the software, 11298SN/A# modified or unmodified, in source code or in binary form. 12298SN/A# 13298SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 14298SN/A# All rights reserved. 15298SN/A# 16298SN/A# Redistribution and use in source and binary forms, with or without 17298SN/A# modification, are permitted provided that the following conditions are 18298SN/A# met: redistributions of source code must retain the above copyright 19298SN/A# notice, this list of conditions and the following disclaimer; 20298SN/A# redistributions in binary form must reproduce the above copyright 21298SN/A# notice, this list of conditions and the following disclaimer in the 22298SN/A# documentation and/or other materials provided with the distribution; 23298SN/A# neither the name of the copyright holders nor the names of its 24298SN/A# contributors may be used to endorse or promote products derived from 25298SN/A# this software without specific prior written permission. 26298SN/A# 272665Ssaidi@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 282665Ssaidi@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29298SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30298SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 311642SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32954SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33956SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34956SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35299SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36299SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 372081SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 382170SN/A# 393089Ssaidi@eecs.umich.edu# Authors: Ali Saidi 401717SN/A 412680Sktlim@umich.eduimport optparse 422313SN/Aimport os 431070SN/Aimport sys 44299SN/A 45298SN/Aimport m5 46298SN/Afrom m5.defines import buildEnv 47695SN/Afrom m5.objects import * 48695SN/Afrom m5.util import addToPath, fatal 49954SN/A 501052SN/Aif not buildEnv['FULL_SYSTEM']: 512080SN/A fatal("This script requires full-system mode (*_FS).") 52298SN/A 53299SN/AaddToPath('../common') 541052SN/A 55729SN/Afrom FSConfig import * 562107SN/Afrom SysPaths import * 57298SN/Afrom Benchmarks import * 58298SN/Aimport Simulation 59298SN/Aimport CacheConfig 60299SN/Afrom Caches import * 61299SN/A 62310SN/A# Get paths we might need. It's expected this file is in m5/configs/example. 63310SN/Aconfig_path = os.path.dirname(os.path.abspath(__file__)) 64310SN/Aconfig_root = os.path.dirname(config_path) 652680Sktlim@umich.edu 66711SN/Aparser = optparse.OptionParser() 672680Sktlim@umich.edu 682680Sktlim@umich.edu# Simulation options 69711SN/Aparser.add_option("--timesync", action="store_true", 70711SN/A help="Prevent simulated time from getting ahead of real time") 71711SN/A 722680Sktlim@umich.edu# System options 73310SN/Aparser.add_option("--kernel", action="store", type="string") 74310SN/Aparser.add_option("--script", action="store", type="string") 75310SN/Aif buildEnv['TARGET_ISA'] == "arm": 76310SN/A parser.add_option("--bare-metal", action="store_true", 772680Sktlim@umich.edu help="Provide the raw system without the linux specific bits") 782680Sktlim@umich.edu parser.add_option("--machine-type", action="store", type="choice", 792680Sktlim@umich.edu choices=ArmMachineType.map.keys(), default="RealView_PBX") 80310SN/A# Benchmark options 81299SN/Aparser.add_option("--dual", action="store_true", 82298SN/A help="Simulate two systems attached with an ethernet link") 832680Sktlim@umich.eduparser.add_option("-b", "--benchmark", action="store", type="string", 842188SN/A dest="benchmark", 852188SN/A help="Specify the benchmark to run. Available benchmarks: %s"\ 862188SN/A % DefinedBenchmarks) 872188SN/A 882680Sktlim@umich.edu# Metafile options 892235SN/Aparser.add_option("--etherdump", action="store", type="string", dest="etherdump", 902235SN/A help="Specify the filename to dump a pcap capture of the" \ 912235SN/A "ethernet traffic") 922188SN/A 932235SN/Aexecfile(os.path.join(config_root, "common", "Options.py")) 942188SN/A 952680Sktlim@umich.edu(options, args) = parser.parse_args() 962680Sktlim@umich.edu 972680Sktlim@umich.eduif args: 982188SN/A print "Error: script doesn't take any positional arguments" 992188SN/A sys.exit(1) 1002188SN/A 1012680Sktlim@umich.edu# driver system CPU is always simple... note this is an assignment of 1022188SN/A# a class, not an instance. 1032188SN/ADriveCPUClass = AtomicSimpleCPU 1042188SN/Adrive_mem_mode = 'atomic' 1052188SN/A 1062680Sktlim@umich.edu# system under test can be any CPU 1072235SN/A(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 1082235SN/A 1092235SN/ATestCPUClass.clock = '2GHz' 1102680Sktlim@umich.eduDriveCPUClass.clock = '2GHz' 1112188SN/A 1122235SN/Aif options.benchmark: 1132680Sktlim@umich.edu try: 1142188SN/A bm = Benchmarks[options.benchmark] 1152680Sktlim@umich.edu except KeyError: 1162680Sktlim@umich.edu print "Error benchmark %s has not been defined." % options.benchmark 1172680Sktlim@umich.edu print "Valid benchmarks are: %s" % DefinedBenchmarks 1182188SN/A sys.exit(1) 1192188SN/Aelse: 1202188SN/A if options.dual: 1212680Sktlim@umich.edu bm = [SysConfig(), SysConfig()] 1222188SN/A else: 1232680Sktlim@umich.edu bm = [SysConfig()] 1242188SN/A 1252188SN/Anp = options.num_cpus 1262188SN/A 1272680Sktlim@umich.eduif buildEnv['TARGET_ISA'] == "alpha": 128711SN/A test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) 1292680Sktlim@umich.eduelif buildEnv['TARGET_ISA'] == "mips": 1302680Sktlim@umich.edu test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) 131711SN/Aelif buildEnv['TARGET_ISA'] == "sparc": 132711SN/A test_sys = makeSparcSystem(test_mem_mode, bm[0]) 133711SN/Aelif buildEnv['TARGET_ISA'] == "x86": 1342680Sktlim@umich.edu test_sys = makeLinuxX86System(test_mem_mode, np, bm[0]) 135711SN/Aelif buildEnv['TARGET_ISA'] == "arm": 136711SN/A test_sys = makeLinuxArmSystem(test_mem_mode, bm[0], 137711SN/A bare_metal=options.bare_metal, machine_type=options.machine_type) 138711SN/Aelse: 1392680Sktlim@umich.edu fatal("incapable of building non-alpha or non-sparc full system!") 140298SN/A 1412667Sstever@eecs.umich.eduif options.kernel is not None: 142298SN/A test_sys.kernel = binary(options.kernel) 143298SN/A 144298SN/Aif options.script is not None: 1452680Sktlim@umich.edu test_sys.readfile = options.script 146298SN/A 1471609SN/Atest_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] 1482667Sstever@eecs.umich.edu 149298SN/ACacheConfig.config_cache(options, test_sys) 150298SN/A 151298SN/Aif options.caches or options.l2cache: 1522680Sktlim@umich.edu if bm[0]: 153298SN/A mem_size = bm[0].mem() 154299SN/A else: 155299SN/A mem_size = SysConfig().mem() 156299SN/A # For x86, we need to poke a hole for interrupt messages to get back to the 157298SN/A # CPU. These use a portion of the physical address space which has a 1581609SN/A # non-zero prefix in the top nibble. Normal memory accesses have a 0 1591609SN/A # prefix. 160298SN/A if buildEnv['TARGET_ISA'] == 'x86': 161729SN/A test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max >> 4)] 162298SN/A else: 163298SN/A test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] 164298SN/A test_sys.bridge.filter_ranges_b=[AddrRange(mem_size)] 165298SN/A test_sys.iocache = IOCache(addr_range=mem_size) 1662680Sktlim@umich.edu test_sys.iocache.cpu_side = test_sys.iobus.port 167298SN/A test_sys.iocache.mem_side = test_sys.membus.port 168299SN/A 169299SN/Afor i in xrange(np): 170299SN/A if options.fastmem: 171298SN/A test_sys.cpu[i].physmem_port = test_sys.physmem.port 1721609SN/A 1731609SN/Aif buildEnv['TARGET_ISA'] == 'mips': 174298SN/A setMipsOptions(TestCPUClass) 175729SN/A 176298SN/Aif len(bm) == 2: 177298SN/A if buildEnv['TARGET_ISA'] == 'alpha': 178298SN/A drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 179298SN/A elif buildEnv['TARGET_ISA'] == 'mips': 1802680Sktlim@umich.edu drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 1811973SN/A elif buildEnv['TARGET_ISA'] == 'sparc': 1821973SN/A drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 1832680Sktlim@umich.edu elif buildEnv['TARGET_ISA'] == 'x86': 1841973SN/A drive_sys = makeX86System(drive_mem_mode, np, bm[1]) 1851973SN/A elif buildEnv['TARGET_ISA'] == 'arm': 1861973SN/A drive_sys = makeLinuxArmSystem(drive_mem_mode, bm[1]) 1871973SN/A drive_sys.cpu = DriveCPUClass(cpu_id=0) 1882680Sktlim@umich.edu drive_sys.cpu.connectAllPorts(drive_sys.membus) 1891973SN/A if options.fastmem: 1901973SN/A drive_sys.cpu.physmem_port = drive_sys.physmem.port 1911973SN/A if options.kernel is not None: 1923089Ssaidi@eecs.umich.edu drive_sys.kernel = binary(options.kernel) 1933089Ssaidi@eecs.umich.edu 1943089Ssaidi@eecs.umich.edu root = makeDualRoot(test_sys, drive_sys, options.etherdump) 1953089Ssaidi@eecs.umich.eduelif len(bm) == 1: 1963089Ssaidi@eecs.umich.edu root = Root(system=test_sys) 1973089Ssaidi@eecs.umich.eduelse: 1983089Ssaidi@eecs.umich.edu print "Error I don't know how to create more than 2 systems." 1993089Ssaidi@eecs.umich.edu sys.exit(1) 2003089Ssaidi@eecs.umich.edu 2013089Ssaidi@eecs.umich.eduif options.timesync: 2023089Ssaidi@eecs.umich.edu root.time_sync_enable = True 2033089Ssaidi@eecs.umich.edu 2043089Ssaidi@eecs.umich.eduSimulation.run(options, root, test_sys, FutureClass) 2053089Ssaidi@eecs.umich.edu