fs.py revision 9826:014ff1fbff6d
1# Copyright (c) 2010-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40
41import optparse
42import sys
43
44import m5
45from m5.defines import buildEnv
46from m5.objects import *
47from m5.util import addToPath, fatal
48
49addToPath('../common')
50
51from FSConfig import *
52from SysPaths import *
53from Benchmarks import *
54import Simulation
55import CacheConfig
56from Caches import *
57import Options
58
59parser = optparse.OptionParser()
60Options.addCommonOptions(parser)
61Options.addFSOptions(parser)
62
63(options, args) = parser.parse_args()
64
65if args:
66    print "Error: script doesn't take any positional arguments"
67    sys.exit(1)
68
69# driver system CPU is always simple... note this is an assignment of
70# a class, not an instance.
71DriveCPUClass = AtomicSimpleCPU
72drive_mem_mode = 'atomic'
73
74# Check if KVM support has been enabled, we might need to do VM
75# configuration if that's the case.
76have_kvm_support = 'BaseKvmCPU' in globals()
77def is_kvm_cpu(cpu_class):
78    return have_kvm_support and cpu_class != None and \
79        issubclass(cpu_class, BaseKvmCPU)
80
81# system under test can be any CPU
82(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
83
84# Match the memories with the CPUs, the driver system always simple,
85# and based on the options for the test system
86DriveMemClass = SimpleMemory
87TestMemClass = Simulation.setMemClass(options)
88
89if options.benchmark:
90    try:
91        bm = Benchmarks[options.benchmark]
92    except KeyError:
93        print "Error benchmark %s has not been defined." % options.benchmark
94        print "Valid benchmarks are: %s" % DefinedBenchmarks
95        sys.exit(1)
96else:
97    if options.dual:
98        bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)]
99    else:
100        bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
101
102np = options.num_cpus
103
104if buildEnv['TARGET_ISA'] == "alpha":
105    test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
106elif buildEnv['TARGET_ISA'] == "mips":
107    test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
108elif buildEnv['TARGET_ISA'] == "sparc":
109    test_sys = makeSparcSystem(test_mem_mode, bm[0])
110elif buildEnv['TARGET_ISA'] == "x86":
111    test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
112elif buildEnv['TARGET_ISA'] == "arm":
113    test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
114                             options.dtb_filename,
115                             bare_metal=options.bare_metal)
116else:
117    fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
118
119# Create a source clock for the system and set the clock period
120test_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock)
121
122# Create a source clock for the CPUs and set the clock period
123test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
124
125if options.kernel is not None:
126    test_sys.kernel = binary(options.kernel)
127
128if options.script is not None:
129    test_sys.readfile = options.script
130
131test_sys.init_param = options.init_param
132
133# For now, assign all the CPUs to the same clock domain
134test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
135                for i in xrange(np)]
136
137if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
138    test_sys.vm = KvmVM()
139
140if options.caches or options.l2cache:
141    # By default the IOCache runs at the system clock
142    test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
143    test_sys.iocache.cpu_side = test_sys.iobus.master
144    test_sys.iocache.mem_side = test_sys.membus.slave
145else:
146    test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
147    test_sys.iobridge.slave = test_sys.iobus.master
148    test_sys.iobridge.master = test_sys.membus.slave
149
150# Sanity check
151if options.fastmem:
152    if TestCPUClass != AtomicSimpleCPU:
153        fatal("Fastmem can only be used with atomic CPU!")
154    if (options.caches or options.l2cache):
155        fatal("You cannot use fastmem in combination with caches!")
156
157for i in xrange(np):
158    if options.fastmem:
159        test_sys.cpu[i].fastmem = True
160    if options.checker:
161        test_sys.cpu[i].addCheckerCpu()
162    test_sys.cpu[i].createThreads()
163
164CacheConfig.config_cache(options, test_sys)
165
166# Create the appropriate memory controllers and connect them to the
167# memory bus
168test_sys.mem_ctrls = [TestMemClass(range = r, conf_table_reported = True)
169                      for r in test_sys.mem_ranges]
170for i in xrange(len(test_sys.mem_ctrls)):
171    test_sys.mem_ctrls[i].port = test_sys.membus.master
172
173if len(bm) == 2:
174    if buildEnv['TARGET_ISA'] == 'alpha':
175        drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
176    elif buildEnv['TARGET_ISA'] == 'mips':
177        drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
178    elif buildEnv['TARGET_ISA'] == 'sparc':
179        drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
180    elif buildEnv['TARGET_ISA'] == 'x86':
181        drive_sys = makeX86System(drive_mem_mode, np, bm[1])
182    elif buildEnv['TARGET_ISA'] == 'arm':
183        drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
184
185    # Create a source clock for the system and set the clock period
186    drive_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock)
187
188    # Create a source clock for the CPUs and set the clock period
189    drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
190
191    drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
192                                  cpu_id=0)
193    drive_sys.cpu.createThreads()
194    drive_sys.cpu.createInterruptController()
195    drive_sys.cpu.connectAllPorts(drive_sys.membus)
196    if options.fastmem:
197        drive_sys.cpu.fastmem = True
198    if options.kernel is not None:
199        drive_sys.kernel = binary(options.kernel)
200
201    if is_kvm_cpu(DriveCPUClass):
202        drive_sys.vm = KvmVM()
203
204    drive_sys.iobridge = Bridge(delay='50ns',
205                                ranges = drive_sys.mem_ranges)
206    drive_sys.iobridge.slave = drive_sys.iobus.master
207    drive_sys.iobridge.master = drive_sys.membus.slave
208
209    # Create the appropriate memory controllers and connect them to the
210    # memory bus
211    drive_sys.mem_ctrls = [DriveMemClass(range = r, conf_table_reported = True)
212                           for r in drive_sys.mem_ranges]
213    for i in xrange(len(drive_sys.mem_ctrls)):
214        drive_sys.mem_ctrls[i].port = drive_sys.membus.master
215
216    drive_sys.init_param = options.init_param
217    root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
218elif len(bm) == 1:
219    root = Root(full_system=True, system=test_sys)
220else:
221    print "Error I don't know how to create more than 2 systems."
222    sys.exit(1)
223
224if options.timesync:
225    root.time_sync_enable = True
226
227if options.frame_capture:
228    VncServer.frame_capture = True
229
230Simulation.setWorkCountOptions(test_sys, options)
231Simulation.run(options, root, test_sys, FutureClass)
232