fs.py revision 9836:4411b4e0c03a 
1# Copyright (c) 2010-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40
41import optparse
42import sys
43
44import m5
45from m5.defines import buildEnv
46from m5.objects import *
47from m5.util import addToPath, fatal
48
49addToPath('../common')
50
51from FSConfig import *
52from SysPaths import *
53from Benchmarks import *
54import Simulation
55import CacheConfig
56import MemConfig
57from Caches import *
58import Options
59
60parser = optparse.OptionParser()
61Options.addCommonOptions(parser)
62Options.addFSOptions(parser)
63
64(options, args) = parser.parse_args()
65
66if args:
67    print "Error: script doesn't take any positional arguments"
68    sys.exit(1)
69
70# driver system CPU is always simple... note this is an assignment of
71# a class, not an instance.
72DriveCPUClass = AtomicSimpleCPU
73drive_mem_mode = 'atomic'
74
75# Check if KVM support has been enabled, we might need to do VM
76# configuration if that's the case.
77have_kvm_support = 'BaseKvmCPU' in globals()
78def is_kvm_cpu(cpu_class):
79    return have_kvm_support and cpu_class != None and \
80        issubclass(cpu_class, BaseKvmCPU)
81
82# system under test can be any CPU
83(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
84
85# Match the memories with the CPUs, the driver system always simple,
86# and based on the options for the test system
87DriveMemClass = SimpleMemory
88TestMemClass = Simulation.setMemClass(options)
89
90if options.benchmark:
91    try:
92        bm = Benchmarks[options.benchmark]
93    except KeyError:
94        print "Error benchmark %s has not been defined." % options.benchmark
95        print "Valid benchmarks are: %s" % DefinedBenchmarks
96        sys.exit(1)
97else:
98    if options.dual:
99        bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)]
100    else:
101        bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
102
103np = options.num_cpus
104
105if buildEnv['TARGET_ISA'] == "alpha":
106    test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
107elif buildEnv['TARGET_ISA'] == "mips":
108    test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
109elif buildEnv['TARGET_ISA'] == "sparc":
110    test_sys = makeSparcSystem(test_mem_mode, bm[0])
111elif buildEnv['TARGET_ISA'] == "x86":
112    test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
113elif buildEnv['TARGET_ISA'] == "arm":
114    test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
115                             options.dtb_filename,
116                             bare_metal=options.bare_metal)
117else:
118    fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
119
120# Create a top-level voltage domain
121test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
122
123# Create a source clock for the system and set the clock period
124test_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock,
125                                     voltage_domain = test_sys.voltage_domain)
126
127# Create a CPU voltage domain
128test_sys.cpu_voltage_domain = VoltageDomain()
129
130# Create a source clock for the CPUs and set the clock period
131test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
132                                         voltage_domain =
133                                         test_sys.cpu_voltage_domain)
134
135if options.kernel is not None:
136    test_sys.kernel = binary(options.kernel)
137
138if options.script is not None:
139    test_sys.readfile = options.script
140
141test_sys.init_param = options.init_param
142
143# For now, assign all the CPUs to the same clock domain
144test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
145                for i in xrange(np)]
146
147if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
148    test_sys.vm = KvmVM()
149
150if options.caches or options.l2cache:
151    # By default the IOCache runs at the system clock
152    test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
153    test_sys.iocache.cpu_side = test_sys.iobus.master
154    test_sys.iocache.mem_side = test_sys.membus.slave
155else:
156    test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
157    test_sys.iobridge.slave = test_sys.iobus.master
158    test_sys.iobridge.master = test_sys.membus.slave
159
160# Sanity check
161if options.fastmem:
162    if TestCPUClass != AtomicSimpleCPU:
163        fatal("Fastmem can only be used with atomic CPU!")
164    if (options.caches or options.l2cache):
165        fatal("You cannot use fastmem in combination with caches!")
166
167for i in xrange(np):
168    if options.fastmem:
169        test_sys.cpu[i].fastmem = True
170    if options.checker:
171        test_sys.cpu[i].addCheckerCpu()
172    test_sys.cpu[i].createThreads()
173
174CacheConfig.config_cache(options, test_sys)
175MemConfig.config_mem(options, test_sys)
176
177if len(bm) == 2:
178    if buildEnv['TARGET_ISA'] == 'alpha':
179        drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
180    elif buildEnv['TARGET_ISA'] == 'mips':
181        drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
182    elif buildEnv['TARGET_ISA'] == 'sparc':
183        drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
184    elif buildEnv['TARGET_ISA'] == 'x86':
185        drive_sys = makeX86System(drive_mem_mode, np, bm[1])
186    elif buildEnv['TARGET_ISA'] == 'arm':
187        drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
188
189    # Create a top-level voltage domain
190    drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
191
192    # Create a source clock for the system and set the clock period
193    drive_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock)
194
195    # Create a CPU voltage domain
196    drive_sys.cpu_voltage_domain = VoltageDomain()
197
198    # Create a source clock for the CPUs and set the clock period
199    drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
200                                              voltage_domain =
201                                              drive_sys.cpu_voltage_domain)
202
203    drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
204                                  cpu_id=0)
205    drive_sys.cpu.createThreads()
206    drive_sys.cpu.createInterruptController()
207    drive_sys.cpu.connectAllPorts(drive_sys.membus)
208    if options.fastmem:
209        drive_sys.cpu.fastmem = True
210    if options.kernel is not None:
211        drive_sys.kernel = binary(options.kernel)
212
213    if is_kvm_cpu(DriveCPUClass):
214        drive_sys.vm = KvmVM()
215
216    drive_sys.iobridge = Bridge(delay='50ns',
217                                ranges = drive_sys.mem_ranges)
218    drive_sys.iobridge.slave = drive_sys.iobus.master
219    drive_sys.iobridge.master = drive_sys.membus.slave
220
221    # Create the appropriate memory controllers and connect them to the
222    # memory bus
223    drive_sys.mem_ctrls = [DriveMemClass(range = r)
224                           for r in drive_sys.mem_ranges]
225    for i in xrange(len(drive_sys.mem_ctrls)):
226        drive_sys.mem_ctrls[i].port = drive_sys.membus.master
227
228    drive_sys.init_param = options.init_param
229    root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
230elif len(bm) == 1:
231    root = Root(full_system=True, system=test_sys)
232else:
233    print "Error I don't know how to create more than 2 systems."
234    sys.exit(1)
235
236if options.timesync:
237    root.time_sync_enable = True
238
239if options.frame_capture:
240    VncServer.frame_capture = True
241
242Simulation.setWorkCountOptions(test_sys, options)
243Simulation.run(options, root, test_sys, FutureClass)
244