fs.py revision 10118:5e1f04b4d5e4
19243SN/A# Copyright (c) 2010-2013 ARM Limited
211675Swendy.elsasser@arm.com# All rights reserved.
39243SN/A#
49243SN/A# The license below extends only to copyright in the software and shall
59243SN/A# not be construed as granting a license to any other intellectual
69243SN/A# property including but not limited to intellectual property relating
79243SN/A# to a hardware implementation of the functionality of the software
89243SN/A# licensed hereunder.  You may use the software subject to the license
99243SN/A# terms below provided that you ensure that this notice is replicated
109243SN/A# unmodified and in its entirety in all distributions of the software,
119243SN/A# modified or unmodified, in source code or in binary form.
129243SN/A#
139243SN/A# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
149831SN/A# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
159831SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan
169831SN/A# All rights reserved.
179243SN/A#
189243SN/A# Redistribution and use in source and binary forms, with or without
199243SN/A# modification, are permitted provided that the following conditions are
209243SN/A# met: redistributions of source code must retain the above copyright
219243SN/A# notice, this list of conditions and the following disclaimer;
229243SN/A# redistributions in binary form must reproduce the above copyright
239243SN/A# notice, this list of conditions and the following disclaimer in the
249243SN/A# documentation and/or other materials provided with the distribution;
259243SN/A# neither the name of the copyright holders nor the names of its
269243SN/A# contributors may be used to endorse or promote products derived from
279243SN/A# this software without specific prior written permission.
289243SN/A#
299243SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
309243SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
319243SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
329243SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
339243SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
349243SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
359243SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
369243SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
379243SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
389243SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
399243SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
409243SN/A#
419243SN/A# Authors: Ali Saidi
429967SN/A#          Brad Beckmann
4310618SOmar.Naji@arm.com
4411555Sjungma@eit.uni-kl.deimport optparse
4511678Swendy.elsasser@arm.comimport sys
4612266Sradhika.jagtap@arm.com
479243SN/Aimport m5
489243SN/Afrom m5.defines import buildEnv
499243SN/Afrom m5.objects import *
509243SN/Afrom m5.util import addToPath, fatal
5110146Sandreas.hansson@arm.com
529243SN/AaddToPath('../common')
539243SN/AaddToPath('../ruby')
5410146Sandreas.hansson@arm.com
5510146Sandreas.hansson@arm.comimport Ruby
569243SN/A
579488SN/Afrom FSConfig import *
5810618SOmar.Naji@arm.comfrom SysPaths import *
5910889Sandreas.hansson@arm.comfrom Benchmarks import *
609488SN/Aimport Simulation
6111677Swendy.elsasser@arm.comimport CacheConfig
629243SN/Aimport MemConfig
639243SN/Afrom Caches import *
649243SN/Aimport Options
659243SN/A
669243SN/Aparser = optparse.OptionParser()
679243SN/AOptions.addCommonOptions(parser)
6810146Sandreas.hansson@arm.comOptions.addFSOptions(parser)
699243SN/A
7010432SOmar.Naji@arm.com# Add the ruby specific and protocol specific options
719243SN/Aif '--ruby' in sys.argv:
729243SN/A    Ruby.define_options(parser)
7310287Sandreas.hansson@arm.com
7410287Sandreas.hansson@arm.com(options, args) = parser.parse_args()
7510287Sandreas.hansson@arm.com
7610287Sandreas.hansson@arm.comif args:
7710287Sandreas.hansson@arm.com    print "Error: script doesn't take any positional arguments"
789243SN/A    sys.exit(1)
7910287Sandreas.hansson@arm.com
8010287Sandreas.hansson@arm.com# driver system CPU is always simple... note this is an assignment of
8110287Sandreas.hansson@arm.com# a class, not an instance.
8210287Sandreas.hansson@arm.comDriveCPUClass = AtomicSimpleCPU
8310287Sandreas.hansson@arm.comdrive_mem_mode = 'atomic'
8410287Sandreas.hansson@arm.com
8510287Sandreas.hansson@arm.com# Check if KVM support has been enabled, we might need to do VM
8610287Sandreas.hansson@arm.com# configuration if that's the case.
8710287Sandreas.hansson@arm.comhave_kvm_support = 'BaseKvmCPU' in globals()
8810287Sandreas.hansson@arm.comdef is_kvm_cpu(cpu_class):
8910287Sandreas.hansson@arm.com    return have_kvm_support and cpu_class != None and \
9010287Sandreas.hansson@arm.com        issubclass(cpu_class, BaseKvmCPU)
9110287Sandreas.hansson@arm.com
9211678Swendy.elsasser@arm.com# system under test can be any CPU
9311678Swendy.elsasser@arm.com(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
9411678Swendy.elsasser@arm.com
9511678Swendy.elsasser@arm.com# Match the memories with the CPUs, the driver system always simple,
969243SN/A# and based on the options for the test system
9710146Sandreas.hansson@arm.comDriveMemClass = SimpleMemory
989243SN/ATestMemClass = Simulation.setMemClass(options)
999243SN/A
1009243SN/Aif options.benchmark:
1019243SN/A    try:
1029243SN/A        bm = Benchmarks[options.benchmark]
1039243SN/A    except KeyError:
1049243SN/A        print "Error benchmark %s has not been defined." % options.benchmark
1059243SN/A        print "Valid benchmarks are: %s" % DefinedBenchmarks
1069243SN/A        sys.exit(1)
10710713Sandreas.hansson@arm.comelse:
10810146Sandreas.hansson@arm.com    if options.dual:
1099243SN/A        bm = [SysConfig(disk=options.disk_image, mem=options.mem_size),
1109243SN/A              SysConfig(disk=options.disk_image, mem=options.mem_size)]
1119243SN/A    else:
11210146Sandreas.hansson@arm.com        bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
1139243SN/A
1149243SN/Anp = options.num_cpus
1159243SN/A
1169243SN/Aif buildEnv['TARGET_ISA'] == "alpha":
1179243SN/A    test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby)
1189243SN/Aelif buildEnv['TARGET_ISA'] == "mips":
1199243SN/A    test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
1209243SN/Aelif buildEnv['TARGET_ISA'] == "sparc":
1219243SN/A    test_sys = makeSparcSystem(test_mem_mode, bm[0])
1229243SN/Aelif buildEnv['TARGET_ISA'] == "x86":
1239243SN/A    test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
1249243SN/A            options.ruby)
1259243SN/Aelif buildEnv['TARGET_ISA'] == "arm":
1269243SN/A    test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
1279243SN/A                             options.dtb_filename,
1289243SN/A                             bare_metal=options.bare_metal)
1299243SN/A    if options.enable_context_switch_stats_dump:
1309243SN/A        test_sys.enable_context_switch_stats_dump = True
1319243SN/Aelse:
1329243SN/A    fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
13310619Sandreas.hansson@arm.com
13410619Sandreas.hansson@arm.com# Set the cache line size for the entire system
13510619Sandreas.hansson@arm.comtest_sys.cache_line_size = options.cacheline_size
13610619Sandreas.hansson@arm.com
13710619Sandreas.hansson@arm.com# Create a top-level voltage domain
1389243SN/Atest_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
1399243SN/A
1409243SN/A# Create a source clock for the system and set the clock period
1419243SN/Atest_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock,
1429243SN/A                                     voltage_domain = test_sys.voltage_domain)
1439243SN/A
14410206Sandreas.hansson@arm.com# Create a CPU voltage domain
14510206Sandreas.hansson@arm.comtest_sys.cpu_voltage_domain = VoltageDomain()
1469243SN/A
14710206Sandreas.hansson@arm.com# Create a source clock for the CPUs and set the clock period
14810206Sandreas.hansson@arm.comtest_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
14910206Sandreas.hansson@arm.com                                         voltage_domain =
15010206Sandreas.hansson@arm.com                                         test_sys.cpu_voltage_domain)
15110206Sandreas.hansson@arm.com
15210206Sandreas.hansson@arm.comif options.kernel is not None:
1539243SN/A    test_sys.kernel = binary(options.kernel)
15411678Swendy.elsasser@arm.com
15511678Swendy.elsasser@arm.comif options.script is not None:
15611678Swendy.elsasser@arm.com    test_sys.readfile = options.script
1579243SN/A
15811675Swendy.elsasser@arm.comif options.lpae:
15911675Swendy.elsasser@arm.com    test_sys.have_lpae = True
16011675Swendy.elsasser@arm.com
16111675Swendy.elsasser@arm.comif options.virtualisation:
16211675Swendy.elsasser@arm.com    test_sys.have_virtualization = True
16311675Swendy.elsasser@arm.com
16411675Swendy.elsasser@arm.comtest_sys.init_param = options.init_param
16511675Swendy.elsasser@arm.com
16611675Swendy.elsasser@arm.com# For now, assign all the CPUs to the same clock domain
16711675Swendy.elsasser@arm.comtest_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
16811675Swendy.elsasser@arm.com                for i in xrange(np)]
16911675Swendy.elsasser@arm.com
17011675Swendy.elsasser@arm.comif is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
17111675Swendy.elsasser@arm.com    test_sys.vm = KvmVM()
17211675Swendy.elsasser@arm.com
17310210Sandreas.hansson@arm.comif options.ruby:
17410210Sandreas.hansson@arm.com    # Check for timing mode because ruby does not support atomic accesses
17510211Sandreas.hansson@arm.com    if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
17610211Sandreas.hansson@arm.com        print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
17710210Sandreas.hansson@arm.com        sys.exit(1)
17810210Sandreas.hansson@arm.com
17910210Sandreas.hansson@arm.com    Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports)
1809243SN/A
1819243SN/A    # Create a seperate clock domain for Ruby
1829243SN/A    test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
1839243SN/A                                    voltage_domain = test_sys.voltage_domain)
1849243SN/A
1859243SN/A    for (i, cpu) in enumerate(test_sys.cpu):
18610207Sandreas.hansson@arm.com        #
1879243SN/A        # Tie the cpu ports to the correct ruby system ports
1889243SN/A        #
18910246Sandreas.hansson@arm.com        cpu.clk_domain = test_sys.cpu_clk_domain
19010394Swendy.elsasser@arm.com        cpu.createThreads()
1919243SN/A        cpu.createInterruptController()
19210211Sandreas.hansson@arm.com
19310210Sandreas.hansson@arm.com        cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].slave
1949969SN/A        cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].slave
1959243SN/A
19610141SN/A        if buildEnv['TARGET_ISA'] == "x86":
1979727SN/A            cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
1989727SN/A            cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
1999727SN/A
20010618SOmar.Naji@arm.com            cpu.interrupts.pio = test_sys.ruby._cpu_ruby_ports[i].master
20110246Sandreas.hansson@arm.com            cpu.interrupts.int_master = test_sys.ruby._cpu_ruby_ports[i].slave
20210141SN/A            cpu.interrupts.int_slave = test_sys.ruby._cpu_ruby_ports[i].master
2039243SN/A
2049243SN/A        test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True
2059243SN/A
20610618SOmar.Naji@arm.com    # Create the appropriate memory controllers and connect them to the
20710618SOmar.Naji@arm.com    # PIO bus
20811678Swendy.elsasser@arm.com    test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
20911678Swendy.elsasser@arm.com    for i in xrange(len(test_sys.mem_ctrls)):
21011678Swendy.elsasser@arm.com        test_sys.mem_ctrls[i].port = test_sys.iobus.master
21111678Swendy.elsasser@arm.com
21211678Swendy.elsasser@arm.comelse:
21311678Swendy.elsasser@arm.com    if options.caches or options.l2cache:
21411678Swendy.elsasser@arm.com        # By default the IOCache runs at the system clock
21511678Swendy.elsasser@arm.com        test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
21611678Swendy.elsasser@arm.com        test_sys.iocache.cpu_side = test_sys.iobus.master
21711678Swendy.elsasser@arm.com        test_sys.iocache.mem_side = test_sys.membus.slave
21811678Swendy.elsasser@arm.com    else:
21911678Swendy.elsasser@arm.com        test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
22011678Swendy.elsasser@arm.com        test_sys.iobridge.slave = test_sys.iobus.master
22111678Swendy.elsasser@arm.com        test_sys.iobridge.master = test_sys.membus.slave
22211678Swendy.elsasser@arm.com
22311678Swendy.elsasser@arm.com    # Sanity check
22411678Swendy.elsasser@arm.com    if options.fastmem:
22511678Swendy.elsasser@arm.com        if TestCPUClass != AtomicSimpleCPU:
22611678Swendy.elsasser@arm.com            fatal("Fastmem can only be used with atomic CPU!")
22711678Swendy.elsasser@arm.com        if (options.caches or options.l2cache):
22811678Swendy.elsasser@arm.com            fatal("You cannot use fastmem in combination with caches!")
22911678Swendy.elsasser@arm.com
23011678Swendy.elsasser@arm.com    for i in xrange(np):
23111678Swendy.elsasser@arm.com        if options.fastmem:
23211678Swendy.elsasser@arm.com            test_sys.cpu[i].fastmem = True
23311678Swendy.elsasser@arm.com        if options.checker:
23411678Swendy.elsasser@arm.com            test_sys.cpu[i].addCheckerCpu()
23511678Swendy.elsasser@arm.com        test_sys.cpu[i].createThreads()
23611678Swendy.elsasser@arm.com
23711678Swendy.elsasser@arm.com    CacheConfig.config_cache(options, test_sys)
23811678Swendy.elsasser@arm.com    MemConfig.config_mem(options, test_sys)
23911678Swendy.elsasser@arm.com
24011678Swendy.elsasser@arm.comif len(bm) == 2:
24111678Swendy.elsasser@arm.com    if buildEnv['TARGET_ISA'] == 'alpha':
24211678Swendy.elsasser@arm.com        drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
24311678Swendy.elsasser@arm.com    elif buildEnv['TARGET_ISA'] == 'mips':
24411678Swendy.elsasser@arm.com        drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
24511678Swendy.elsasser@arm.com    elif buildEnv['TARGET_ISA'] == 'sparc':
24611678Swendy.elsasser@arm.com        drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
24711678Swendy.elsasser@arm.com    elif buildEnv['TARGET_ISA'] == 'x86':
24811678Swendy.elsasser@arm.com        drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1])
24911678Swendy.elsasser@arm.com    elif buildEnv['TARGET_ISA'] == 'arm':
25011678Swendy.elsasser@arm.com        drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
25111678Swendy.elsasser@arm.com
25211678Swendy.elsasser@arm.com    # Create a top-level voltage domain
25311678Swendy.elsasser@arm.com    drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
25411678Swendy.elsasser@arm.com
25511678Swendy.elsasser@arm.com    # Create a source clock for the system and set the clock period
25611678Swendy.elsasser@arm.com    drive_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock)
25711678Swendy.elsasser@arm.com
25811678Swendy.elsasser@arm.com    # Create a CPU voltage domain
25911678Swendy.elsasser@arm.com    drive_sys.cpu_voltage_domain = VoltageDomain()
26011678Swendy.elsasser@arm.com
26111678Swendy.elsasser@arm.com    # Create a source clock for the CPUs and set the clock period
26211678Swendy.elsasser@arm.com    drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
26311678Swendy.elsasser@arm.com                                              voltage_domain =
26411678Swendy.elsasser@arm.com                                              drive_sys.cpu_voltage_domain)
26511678Swendy.elsasser@arm.com
26611678Swendy.elsasser@arm.com    drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
26711678Swendy.elsasser@arm.com                                  cpu_id=0)
26811678Swendy.elsasser@arm.com    drive_sys.cpu.createThreads()
26911678Swendy.elsasser@arm.com    drive_sys.cpu.createInterruptController()
27011678Swendy.elsasser@arm.com    drive_sys.cpu.connectAllPorts(drive_sys.membus)
27111678Swendy.elsasser@arm.com    if options.fastmem:
27211678Swendy.elsasser@arm.com        drive_sys.cpu.fastmem = True
27311678Swendy.elsasser@arm.com    if options.kernel is not None:
27411678Swendy.elsasser@arm.com        drive_sys.kernel = binary(options.kernel)
27511678Swendy.elsasser@arm.com
27611678Swendy.elsasser@arm.com    if is_kvm_cpu(DriveCPUClass):
27711678Swendy.elsasser@arm.com        drive_sys.vm = KvmVM()
27811678Swendy.elsasser@arm.com
27911678Swendy.elsasser@arm.com    drive_sys.iobridge = Bridge(delay='50ns',
28011678Swendy.elsasser@arm.com                                ranges = drive_sys.mem_ranges)
28111678Swendy.elsasser@arm.com    drive_sys.iobridge.slave = drive_sys.iobus.master
28211678Swendy.elsasser@arm.com    drive_sys.iobridge.master = drive_sys.membus.slave
28311678Swendy.elsasser@arm.com
28410618SOmar.Naji@arm.com    # Create the appropriate memory controllers and connect them to the
28510618SOmar.Naji@arm.com    # memory bus
28610618SOmar.Naji@arm.com    drive_sys.mem_ctrls = [DriveMemClass(range = r)
28710618SOmar.Naji@arm.com                           for r in drive_sys.mem_ranges]
28810618SOmar.Naji@arm.com    for i in xrange(len(drive_sys.mem_ctrls)):
28910618SOmar.Naji@arm.com        drive_sys.mem_ctrls[i].port = drive_sys.membus.master
29010618SOmar.Naji@arm.com
29110618SOmar.Naji@arm.com    drive_sys.init_param = options.init_param
29210618SOmar.Naji@arm.com    root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
29310618SOmar.Naji@arm.comelif len(bm) == 1:
29410618SOmar.Naji@arm.com    root = Root(full_system=True, system=test_sys)
29510618SOmar.Naji@arm.comelse:
29610618SOmar.Naji@arm.com    print "Error I don't know how to create more than 2 systems."
29710618SOmar.Naji@arm.com    sys.exit(1)
29810618SOmar.Naji@arm.com
29910618SOmar.Naji@arm.comif options.timesync:
30010618SOmar.Naji@arm.com    root.time_sync_enable = True
30110618SOmar.Naji@arm.com
30211678Swendy.elsasser@arm.comif options.frame_capture:
30310618SOmar.Naji@arm.com    VncServer.frame_capture = True
30410618SOmar.Naji@arm.com
30510618SOmar.Naji@arm.comSimulation.setWorkCountOptions(test_sys, options)
30610618SOmar.Naji@arm.comSimulation.run(options, root, test_sys, FutureClass)
30711678Swendy.elsasser@arm.com