Searched refs:readMiscRegNoEffect (Results 1 - 25 of 74) sorted by relevance

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/gem5/src/arch/sparc/
H A Dutility.cc71 uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL);
79 src->readMiscRegNoEffect(MISCREG_TT));
81 src->readMiscRegNoEffect(MISCREG_TPC));
83 src->readMiscRegNoEffect(MISCREG_TNPC));
85 src->readMiscRegNoEffect(MISCREG_TSTATE));
95 // src->readMiscRegNoEffect(MISCREG_Y));
97 // src->readMiscRegNoEffect(MISCREG_CCR));
99 src->readMiscRegNoEffect(MISCREG_ASI));
101 src->readMiscRegNoEffect(MISCREG_TICK));
103 src->readMiscRegNoEffect(MISCREG_FPR
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H A Dutility.hh60 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
61 HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
97 return tc->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT);
H A Dfaults.cc286 HPSTATE hpstate= tc->readMiscRegNoEffect(MISCREG_HPSTATE);
292 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
305 RegVal TL = tc->readMiscRegNoEffect(MISCREG_TL);
306 RegVal TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
307 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
308 HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
310 RegVal ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
311 RegVal CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
312 RegVal CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3);
313 RegVal GL = tc->readMiscRegNoEffect(MISCREG_G
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H A Dinterrupts.hh139 HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
140 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
196 HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
197 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
/gem5/src/arch/x86/
H A Dremote_gdb.cc98 HandyM5Reg m5reg = context()->readMiscRegNoEffect(MISCREG_M5_REG);
128 r.eflags = context->readMiscRegNoEffect(MISCREG_RFLAGS);
129 r.cs = context->readMiscRegNoEffect(MISCREG_CS);
130 r.ss = context->readMiscRegNoEffect(MISCREG_SS);
131 r.ds = context->readMiscRegNoEffect(MISCREG_DS);
132 r.es = context->readMiscRegNoEffect(MISCREG_ES);
133 r.fs = context->readMiscRegNoEffect(MISCREG_FS);
134 r.gs = context->readMiscRegNoEffect(MISCREG_GS);
150 r.eflags = context->readMiscRegNoEffect(MISCREG_RFLAGS);
151 r.cs = context->readMiscRegNoEffect(MISCREG_C
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H A Dtlb.cc207 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
242 tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
288 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
299 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
302 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
311 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
312 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
392 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
H A Dutility.hh67 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
/gem5/src/arch/mips/
H A Dinterrupts.cc47 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
53 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
116 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
123 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
137 StatusReg M5_VAR_USED status = tc->readMiscRegNoEffect(MISCREG_STATUS);
138 CauseReg M5_VAR_USED cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
148 RegVal compare = tc->readMiscRegNoEffect(MISCREG_COMPARE);
149 RegVal count = tc->readMiscRegNoEffect(MISCREG_COUNT);
169 IntCtlReg intCtl = tc->readMiscRegNoEffect(MISCREG_INTCTL);
H A Dmt.hh121 TCBindReg tcbind = tc->readMiscRegNoEffect(MISCREG_TC_BIND);
129 VPEControlReg vpeCtrl = tc->readMiscRegNoEffect(MISCREG_VPE_CONTROL);
158 Addr restartPC = tc->readMiscRegNoEffect(MISCREG_TC_RESTART);
173 MVPConf0Reg mvpConf = tc->readMiscRegNoEffect(MISCREG_MVP_CONF0);
180 TCBindReg tcBind = tc->readMiscRegNoEffect(MISCREG_TC_BIND);
229 tc->readMiscRegNoEffect(MISCREG_VPE_CONTROL);
242 MVPConf0Reg mvpConf0 = tc->readMiscRegNoEffect(MISCREG_MVP_CONF0);
248 TCBindReg tcBind = tc->readMiscRegNoEffect(MISCREG_TC_BIND);
271 TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS);
286 TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATU
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H A Dremote_gdb.cc177 r.sr = context->readMiscRegNoEffect(MISCREG_STATUS);
180 r.badvaddr = context->readMiscRegNoEffect(MISCREG_BADVADDR);
181 r.cause = context->readMiscRegNoEffect(MISCREG_CAUSE);
H A Disa.cc180 PRIdReg procId = readMiscRegNoEffect(MISCREG_PRID);
193 ConfigReg cfg = readMiscRegNoEffect(MISCREG_CONFIG);
207 Config1Reg cfg1 = readMiscRegNoEffect(MISCREG_CONFIG1);
229 Config2Reg cfg2 = readMiscRegNoEffect(MISCREG_CONFIG2);
246 Config3Reg cfg3 = readMiscRegNoEffect(MISCREG_CONFIG3);
262 EBaseReg eBase = readMiscRegNoEffect(MISCREG_EBASE);
273 SRSCtlReg scsCtl = readMiscRegNoEffect(MISCREG_SRSCTL);
282 IntCtlReg intCtl = readMiscRegNoEffect(MISCREG_INTCTL);
292 WatchHiReg watchHi = readMiscRegNoEffect(MISCREG_WATCHHI0);
301 PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(MISCREG_PERFCNT
421 ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const function in class:MipsISA::ISA
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/gem5/src/arch/alpha/
H A Didle_event.cc43 RegVal val = tc->readMiscRegNoEffect(IPR_PALtemp23);
H A Dutility.cc89 src->readMiscRegNoEffect(MISCREG_FPCR));
91 src->readMiscRegNoEffect(MISCREG_UNIQ));
93 src->readMiscRegNoEffect(MISCREG_LOCKFLAG));
95 src->readMiscRegNoEffect(MISCREG_LOCKADDR));
H A Dinterrupts.hh146 if (tc->readMiscRegNoEffect(IPR_ASTRR))
152 if (tc->readMiscRegNoEffect(IPR_SIRR)) {
155 if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
172 return ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR);
182 if (tc->readMiscRegNoEffect(IPR_SIRR)) {
185 if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
206 tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
H A Dutility.hh58 return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
116 return DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
H A Dstacktrace.cc144 (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
215 if (addr == tc->readMiscRegNoEffect(IPR_PALtemp12))
218 if (addr == tc->readMiscRegNoEffect(IPR_PALtemp7))
221 if (addr == tc->readMiscRegNoEffect(IPR_PALtemp11))
224 if (addr == tc->readMiscRegNoEffect(IPR_PALtemp21))
227 if (addr == tc->readMiscRegNoEffect(IPR_PALtemp9))
230 if (addr == tc->readMiscRegNoEffect(IPR_PALtemp2))
H A Dfaults.cc133 tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
136 pc.set(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
171 tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
184 tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc88 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
102 HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
116 RegVal value = isa->readMiscRegNoEffect(misc_reg);
125 return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1);
148 return isa->readMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1);
179 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
197 isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
206 igrp_el3.EnableGrp1S = ((ICC_IGRPEN1_EL1)isa->readMiscRegNoEffect(
209 igrp_el3.EnableGrp1NS = ((ICC_IGRPEN1_EL1)isa->readMiscRegNoEffect(
227 (isa->readMiscRegNoEffect(MISCREG_SCR_EL
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/gem5/src/arch/arm/
H A Dfaults.cc301 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
459 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
518 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
730 CPSR M5_VAR_USED cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
798 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
799 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
800 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
870 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
871 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
872 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPS
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H A Disa.cc428 ISA::readMiscRegNoEffect(int misc_reg) const function in class:ArmISA::ISA
483 return readMiscRegNoEffect(MISCREG_HCR);
497 scr = readMiscRegNoEffect(MISCREG_SCR);
498 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
500 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
506 RegVal val = readMiscRegNoEffect(MISCREG_CPACR);
518 return readMiscRegNoEffect(misc_reg) | 0x80000000;
522 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
523 scr = readMiscRegNoEffect(MISCREG_SCR);
525 return readMiscRegNoEffect(misc_re
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H A Dremote_gdb.cc210 r.cpsr = context->readMiscRegNoEffect(MISCREG_CPSR);
220 r.fpsr = context->readMiscRegNoEffect(MISCREG_FPSR);
221 r.fpcr = context->readMiscRegNoEffect(MISCREG_FPCR);
274 r.cpsr = context->readMiscRegNoEffect(MISCREG_CPSR);
280 r.fpscr = context->readMiscRegNoEffect(MISCREG_FPSCR);
/gem5/src/arch/power/
H A Disa.hh65 readMiscRegNoEffect(int misc_reg) const function in class:PowerISA::ISA
/gem5/src/arch/riscv/
H A Disa.hh77 RegVal readMiscRegNoEffect(int misc_reg) const;
H A Disa.cc82 switch (readMiscRegNoEffect(MISCREG_PRV)) {
99 ISA::readMiscRegNoEffect(int misc_reg) const function in class:RiscvISA::ISA
164 return readMiscRegNoEffect(misc_reg);
/gem5/src/cpu/kvm/
H A Dx86_cpu.cc713 SegAttr attr(tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(index)));
715 kvm_seg.base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(index));
716 kvm_seg.limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(index));
717 kvm_seg.selector = tc->readMiscRegNoEffect(MISCREG_SEG_SEL(index));
738 kvm_dtable.base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(index));
739 kvm_dtable.limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(index));
759 #define APPLY_SREG(kreg, mreg) sregs.kreg = tc->readMiscRegNoEffect(mreg)
826 fpu.mxcsr = tc->readMiscRegNoEffect(MISCREG_MXCSR);
827 fpu.fcw = tc->readMiscRegNoEffect(MISCREG_FCW);
832 uint64_t ftw(tc->readMiscRegNoEffect(MISCREG_FT
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