12SN/A/*
21762SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Gabe Black
292665Ssaidi@eecs.umich.edu *          Kevin Lim
302SN/A */
312SN/A
3211793Sbrandon.potter@amd.com#include "arch/alpha/faults.hh"
3311793Sbrandon.potter@amd.com
344997Sgblack@eecs.umich.edu#include "arch/alpha/ev5.hh"
354997Sgblack@eecs.umich.edu#include "arch/alpha/tlb.hh"
368229Snate@binkert.org#include "base/trace.hh"
378229Snate@binkert.org#include "cpu/base.hh"
382680Sktlim@umich.edu#include "cpu/thread_context.hh"
398229Snate@binkert.org#include "mem/page_table.hh"
4011793Sbrandon.potter@amd.com#include "sim/full_system.hh"
412800Ssaidi@eecs.umich.edu#include "sim/process.hh"
422SN/A
435569Snate@binkert.orgnamespace AlphaISA {
442167SN/A
452203SN/AFaultName MachineCheckFault::_name = "mchk";
462203SN/AFaultVect MachineCheckFault::_vect = 0x0401;
472222SN/AFaultStat MachineCheckFault::_count;
482166SN/A
492203SN/AFaultName AlignmentFault::_name = "unalign";
502203SN/AFaultVect AlignmentFault::_vect = 0x0301;
512222SN/AFaultStat AlignmentFault::_count;
522166SN/A
532147SN/AFaultName ResetFault::_name = "reset";
542147SN/AFaultVect ResetFault::_vect = 0x0001;
552222SN/AFaultStat ResetFault::_count;
562147SN/A
572147SN/AFaultName ArithmeticFault::_name = "arith";
582147SN/AFaultVect ArithmeticFault::_vect = 0x0501;
592222SN/AFaultStat ArithmeticFault::_count;
602147SN/A
612147SN/AFaultName InterruptFault::_name = "interrupt";
622147SN/AFaultVect InterruptFault::_vect = 0x0101;
632222SN/AFaultStat InterruptFault::_count;
642147SN/A
652147SN/AFaultName NDtbMissFault::_name = "dtb_miss_single";
662147SN/AFaultVect NDtbMissFault::_vect = 0x0201;
672222SN/AFaultStat NDtbMissFault::_count;
682147SN/A
692147SN/AFaultName PDtbMissFault::_name = "dtb_miss_double";
702147SN/AFaultVect PDtbMissFault::_vect = 0x0281;
712222SN/AFaultStat PDtbMissFault::_count;
722147SN/A
738405Sksewell@umich.eduFaultName DtbPageFault::_name = "dtb_page_fault";
742147SN/AFaultVect DtbPageFault::_vect = 0x0381;
752222SN/AFaultStat DtbPageFault::_count;
762147SN/A
778405Sksewell@umich.eduFaultName DtbAcvFault::_name = "dtb_acv_fault";
782147SN/AFaultVect DtbAcvFault::_vect = 0x0381;
792222SN/AFaultStat DtbAcvFault::_count;
802147SN/A
812289SN/AFaultName DtbAlignmentFault::_name = "unalign";
822289SN/AFaultVect DtbAlignmentFault::_vect = 0x0301;
832289SN/AFaultStat DtbAlignmentFault::_count;
842289SN/A
852147SN/AFaultName ItbPageFault::_name = "itbmiss";
862147SN/AFaultVect ItbPageFault::_vect = 0x0181;
872222SN/AFaultStat ItbPageFault::_count;
882147SN/A
892147SN/AFaultName ItbAcvFault::_name = "iaccvio";
902147SN/AFaultVect ItbAcvFault::_vect = 0x0081;
912222SN/AFaultStat ItbAcvFault::_count;
922147SN/A
932147SN/AFaultName UnimplementedOpcodeFault::_name = "opdec";
942147SN/AFaultVect UnimplementedOpcodeFault::_vect = 0x0481;
952222SN/AFaultStat UnimplementedOpcodeFault::_count;
962147SN/A
972147SN/AFaultName FloatEnableFault::_name = "fen";
982147SN/AFaultVect FloatEnableFault::_vect = 0x0581;
992222SN/AFaultStat FloatEnableFault::_count;
1002147SN/A
10112110SRekai.GonzalezAlberquilla@arm.com/* We use the same fault vector, as for the guest system these should be the
10212110SRekai.GonzalezAlberquilla@arm.com * same, but for host purposes, having differentiation is helpful for
10312110SRekai.GonzalezAlberquilla@arm.com * debug/monitorization purposes. */
10412110SRekai.GonzalezAlberquilla@arm.comFaultName VectorEnableFault::_name = "ven";
10512110SRekai.GonzalezAlberquilla@arm.comFaultVect VectorEnableFault::_vect = 0x0581;
10612110SRekai.GonzalezAlberquilla@arm.comFaultStat VectorEnableFault::_count;
10712110SRekai.GonzalezAlberquilla@arm.com
1082147SN/AFaultName PalFault::_name = "pal";
1092147SN/AFaultVect PalFault::_vect = 0x2001;
1102222SN/AFaultStat PalFault::_count;
1112147SN/A
1122147SN/AFaultName IntegerOverflowFault::_name = "intover";
1132147SN/AFaultVect IntegerOverflowFault::_vect = 0x0501;
1142222SN/AFaultStat IntegerOverflowFault::_count;
1152147SN/A
1165569Snate@binkert.orgvoid
11710417Sandreas.hansson@arm.comAlphaFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1182174SN/A{
1192680Sktlim@umich.edu    FaultBase::invoke(tc);
1208780Sgblack@eecs.umich.edu    if (!FullSystem)
1218780Sgblack@eecs.umich.edu        return;
1222222SN/A    countStat()++;
1232174SN/A
1247720Sgblack@eecs.umich.edu    PCState pc = tc->pcState();
1257720Sgblack@eecs.umich.edu
1262196SN/A    // exception restart address
1277720Sgblack@eecs.umich.edu    if (setRestartAddress() || !(pc.pc() & 0x3))
1287720Sgblack@eecs.umich.edu        tc->setMiscRegNoEffect(IPR_EXC_ADDR, pc.pc());
1292196SN/A
1302201SN/A    if (skipFaultingInstruction()) {
1312196SN/A        // traps...  skip faulting instruction.
1325568Snate@binkert.org        tc->setMiscRegNoEffect(IPR_EXC_ADDR,
1335568Snate@binkert.org                   tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
1342196SN/A    }
1352196SN/A
1367720Sgblack@eecs.umich.edu    pc.set(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
1377720Sgblack@eecs.umich.edu    tc->pcState(pc);
1382174SN/A}
1392174SN/A
1405569Snate@binkert.orgvoid
14110417Sandreas.hansson@arm.comArithmeticFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1422201SN/A{
1432680Sktlim@umich.edu    FaultBase::invoke(tc);
1448780Sgblack@eecs.umich.edu    if (!FullSystem)
1458780Sgblack@eecs.umich.edu        return;
1462201SN/A    panic("Arithmetic traps are unimplemented!");
1472201SN/A}
1482201SN/A
1495569Snate@binkert.orgvoid
15010417Sandreas.hansson@arm.comDtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1512289SN/A{
1528780Sgblack@eecs.umich.edu    if (FullSystem) {
1538780Sgblack@eecs.umich.edu        // Set fault address and flags.  Even though we're modeling an
1548780Sgblack@eecs.umich.edu        // EV5, we use the EV6 technique of not latching fault registers
1558780Sgblack@eecs.umich.edu        // on VPTE loads (instead of locking the registers until IPR_VA is
1568780Sgblack@eecs.umich.edu        // read, like the EV5).  The EV6 approach is cleaner and seems to
1578780Sgblack@eecs.umich.edu        // work with EV5 PAL code, but not the other way around.
15810823SAndreas.Sandberg@ARM.com        if (reqFlags.noneSet(AlphaRequestFlags::VPTE | Request::PREFETCH)) {
1598780Sgblack@eecs.umich.edu            // set VA register with faulting address
1608780Sgblack@eecs.umich.edu            tc->setMiscRegNoEffect(IPR_VA, vaddr);
1612289SN/A
1628780Sgblack@eecs.umich.edu            // set MM_STAT register flags
1638780Sgblack@eecs.umich.edu            MachInst machInst = inst->machInst;
1648780Sgblack@eecs.umich.edu            tc->setMiscRegNoEffect(IPR_MM_STAT,
1658780Sgblack@eecs.umich.edu                (((Opcode(machInst) & 0x3f) << 11) |
1668780Sgblack@eecs.umich.edu                 ((Ra(machInst) & 0x1f) << 6) |
1678780Sgblack@eecs.umich.edu                 (flags & 0x3f)));
1682289SN/A
1698780Sgblack@eecs.umich.edu            // set VA_FORM register with faulting formatted address
1708780Sgblack@eecs.umich.edu            tc->setMiscRegNoEffect(IPR_VA_FORM,
1718780Sgblack@eecs.umich.edu                tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
1728780Sgblack@eecs.umich.edu        }
1732289SN/A    }
1742289SN/A
1752680Sktlim@umich.edu    AlphaFault::invoke(tc);
1762289SN/A}
1772289SN/A
1785569Snate@binkert.orgvoid
17910417Sandreas.hansson@arm.comItbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1802289SN/A{
1818780Sgblack@eecs.umich.edu    if (FullSystem) {
18210664SAli.Saidi@ARM.com        tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
18310664SAli.Saidi@ARM.com        tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
18410664SAli.Saidi@ARM.com            tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
1852289SN/A    }
1862289SN/A
1872680Sktlim@umich.edu    AlphaFault::invoke(tc);
1882289SN/A}
1892289SN/A
1905569Snate@binkert.orgvoid
19110417Sandreas.hansson@arm.comItbPageFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1924997Sgblack@eecs.umich.edu{
1938780Sgblack@eecs.umich.edu    if (FullSystem) {
1948780Sgblack@eecs.umich.edu        ItbFault::invoke(tc);
1958806Sgblack@eecs.umich.edu        return;
1968806Sgblack@eecs.umich.edu    }
1978806Sgblack@eecs.umich.edu
1988806Sgblack@eecs.umich.edu    Process *p = tc->getProcessPtr();
19912461Sgabeblack@google.com    const EmulationPageTable::Entry *pte = p->pTable->lookup(pc);
20012461Sgabeblack@google.com    panic_if(!pte, "Tried to execute unmapped address %#x.\n", pc);
20112455Sgabeblack@google.com
20212455Sgabeblack@google.com    VAddr vaddr(pc);
20312461Sgabeblack@google.com    TlbEntry entry(p->pTable->pid(), vaddr.page(), pte->paddr,
20412461Sgabeblack@google.com                   pte->flags & EmulationPageTable::Uncacheable,
20512461Sgabeblack@google.com                   pte->flags & EmulationPageTable::ReadOnly);
20612461Sgabeblack@google.com    dynamic_cast<TLB *>(tc->getITBPtr())->insert(vaddr.page(), entry);
2074997Sgblack@eecs.umich.edu}
2084997Sgblack@eecs.umich.edu
2095569Snate@binkert.orgvoid
21010417Sandreas.hansson@arm.comNDtbMissFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
2114997Sgblack@eecs.umich.edu{
2128780Sgblack@eecs.umich.edu    if (FullSystem) {
2138780Sgblack@eecs.umich.edu        DtbFault::invoke(tc, inst);
2148806Sgblack@eecs.umich.edu        return;
2158806Sgblack@eecs.umich.edu    }
2168806Sgblack@eecs.umich.edu
2178806Sgblack@eecs.umich.edu    Process *p = tc->getProcessPtr();
21812461Sgabeblack@google.com    const EmulationPageTable::Entry *pte = p->pTable->lookup(vaddr);
21912461Sgabeblack@google.com    if (!pte && p->fixupStackFault(vaddr))
22012461Sgabeblack@google.com        pte = p->pTable->lookup(vaddr);
22112461Sgabeblack@google.com    panic_if(!pte, "Tried to access unmapped address %#x.\n", (Addr)vaddr);
22212461Sgabeblack@google.com    TlbEntry entry(p->pTable->pid(), vaddr.page(), pte->paddr,
22312461Sgabeblack@google.com                   pte->flags & EmulationPageTable::Uncacheable,
22412461Sgabeblack@google.com                   pte->flags & EmulationPageTable::ReadOnly);
22512461Sgabeblack@google.com    dynamic_cast<TLB *>(tc->getDTBPtr())->insert(vaddr.page(), entry);
2264997Sgblack@eecs.umich.edu}
2274997Sgblack@eecs.umich.edu
2282167SN/A} // namespace AlphaISA
2292167SN/A
230