16691Stjones1@inf.ed.ac.uk/* 26691Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The Regents of The University of Michigan 36691Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The University of Edinburgh 46691Stjones1@inf.ed.ac.uk * All rights reserved. 56691Stjones1@inf.ed.ac.uk * 66691Stjones1@inf.ed.ac.uk * Redistribution and use in source and binary forms, with or without 76691Stjones1@inf.ed.ac.uk * modification, are permitted provided that the following conditions are 86691Stjones1@inf.ed.ac.uk * met: redistributions of source code must retain the above copyright 96691Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer; 106691Stjones1@inf.ed.ac.uk * redistributions in binary form must reproduce the above copyright 116691Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer in the 126691Stjones1@inf.ed.ac.uk * documentation and/or other materials provided with the distribution; 136691Stjones1@inf.ed.ac.uk * neither the name of the copyright holders nor the names of its 146691Stjones1@inf.ed.ac.uk * contributors may be used to endorse or promote products derived from 156691Stjones1@inf.ed.ac.uk * this software without specific prior written permission. 166691Stjones1@inf.ed.ac.uk * 176691Stjones1@inf.ed.ac.uk * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186691Stjones1@inf.ed.ac.uk * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196691Stjones1@inf.ed.ac.uk * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206691Stjones1@inf.ed.ac.uk * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216691Stjones1@inf.ed.ac.uk * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226691Stjones1@inf.ed.ac.uk * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236691Stjones1@inf.ed.ac.uk * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246691Stjones1@inf.ed.ac.uk * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256691Stjones1@inf.ed.ac.uk * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266691Stjones1@inf.ed.ac.uk * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276691Stjones1@inf.ed.ac.uk * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286691Stjones1@inf.ed.ac.uk * 296691Stjones1@inf.ed.ac.uk * Authors: Gabe Black 306691Stjones1@inf.ed.ac.uk * Timothy M. Jones 316691Stjones1@inf.ed.ac.uk */ 326691Stjones1@inf.ed.ac.uk 336691Stjones1@inf.ed.ac.uk#ifndef __ARCH_POWER_ISA_HH__ 346691Stjones1@inf.ed.ac.uk#define __ARCH_POWER_ISA_HH__ 356691Stjones1@inf.ed.ac.uk 366691Stjones1@inf.ed.ac.uk#include "arch/power/registers.hh" 376691Stjones1@inf.ed.ac.uk#include "arch/power/types.hh" 3812334Sgabeblack@google.com#include "base/logging.hh" 3912106SRekai.GonzalezAlberquilla@arm.com#include "cpu/reg_class.hh" 409384SAndreas.Sandberg@arm.com#include "sim/sim_object.hh" 416691Stjones1@inf.ed.ac.uk 429384SAndreas.Sandberg@arm.comstruct PowerISAParams; 436691Stjones1@inf.ed.ac.ukclass ThreadContext; 446691Stjones1@inf.ed.ac.ukclass Checkpoint; 456691Stjones1@inf.ed.ac.ukclass EventManager; 466691Stjones1@inf.ed.ac.uk 476691Stjones1@inf.ed.ac.uknamespace PowerISA 486691Stjones1@inf.ed.ac.uk{ 496691Stjones1@inf.ed.ac.uk 509384SAndreas.Sandberg@arm.comclass ISA : public SimObject 516691Stjones1@inf.ed.ac.uk{ 526691Stjones1@inf.ed.ac.uk protected: 5313617Sgabeblack@google.com RegVal dummy; 5413617Sgabeblack@google.com RegVal miscRegs[NumMiscRegs]; 556691Stjones1@inf.ed.ac.uk 566691Stjones1@inf.ed.ac.uk public: 579384SAndreas.Sandberg@arm.com typedef PowerISAParams Params; 589384SAndreas.Sandberg@arm.com 596691Stjones1@inf.ed.ac.uk void 606691Stjones1@inf.ed.ac.uk clear() 616691Stjones1@inf.ed.ac.uk { 626691Stjones1@inf.ed.ac.uk } 636691Stjones1@inf.ed.ac.uk 6413617Sgabeblack@google.com RegVal 6510698Sandreas.hansson@arm.com readMiscRegNoEffect(int misc_reg) const 666691Stjones1@inf.ed.ac.uk { 676691Stjones1@inf.ed.ac.uk fatal("Power does not currently have any misc regs defined\n"); 686691Stjones1@inf.ed.ac.uk return dummy; 696691Stjones1@inf.ed.ac.uk } 706691Stjones1@inf.ed.ac.uk 7113617Sgabeblack@google.com RegVal 726691Stjones1@inf.ed.ac.uk readMiscReg(int misc_reg, ThreadContext *tc) 736691Stjones1@inf.ed.ac.uk { 746691Stjones1@inf.ed.ac.uk fatal("Power does not currently have any misc regs defined\n"); 756691Stjones1@inf.ed.ac.uk return dummy; 766691Stjones1@inf.ed.ac.uk } 776691Stjones1@inf.ed.ac.uk 786691Stjones1@inf.ed.ac.uk void 7913617Sgabeblack@google.com setMiscRegNoEffect(int misc_reg, RegVal val) 806691Stjones1@inf.ed.ac.uk { 816691Stjones1@inf.ed.ac.uk fatal("Power does not currently have any misc regs defined\n"); 826691Stjones1@inf.ed.ac.uk } 836691Stjones1@inf.ed.ac.uk 846691Stjones1@inf.ed.ac.uk void 8513617Sgabeblack@google.com setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) 866691Stjones1@inf.ed.ac.uk { 876691Stjones1@inf.ed.ac.uk fatal("Power does not currently have any misc regs defined\n"); 886691Stjones1@inf.ed.ac.uk } 896691Stjones1@inf.ed.ac.uk 9012106SRekai.GonzalezAlberquilla@arm.com RegId flattenRegId(const RegId& regId) const { return regId; } 9112106SRekai.GonzalezAlberquilla@arm.com 926691Stjones1@inf.ed.ac.uk int 9310035Sandreas.hansson@arm.com flattenIntIndex(int reg) const 946691Stjones1@inf.ed.ac.uk { 956691Stjones1@inf.ed.ac.uk return reg; 966691Stjones1@inf.ed.ac.uk } 976691Stjones1@inf.ed.ac.uk 986691Stjones1@inf.ed.ac.uk int 9910035Sandreas.hansson@arm.com flattenFloatIndex(int reg) const 1006691Stjones1@inf.ed.ac.uk { 1016691Stjones1@inf.ed.ac.uk return reg; 1026691Stjones1@inf.ed.ac.uk } 1036691Stjones1@inf.ed.ac.uk 10412109SRekai.GonzalezAlberquilla@arm.com int 10512109SRekai.GonzalezAlberquilla@arm.com flattenVecIndex(int reg) const 10612109SRekai.GonzalezAlberquilla@arm.com { 10712109SRekai.GonzalezAlberquilla@arm.com return reg; 10812109SRekai.GonzalezAlberquilla@arm.com } 10912109SRekai.GonzalezAlberquilla@arm.com 11012109SRekai.GonzalezAlberquilla@arm.com int 11112109SRekai.GonzalezAlberquilla@arm.com flattenVecElemIndex(int reg) const 11212109SRekai.GonzalezAlberquilla@arm.com { 11312109SRekai.GonzalezAlberquilla@arm.com return reg; 11412109SRekai.GonzalezAlberquilla@arm.com } 11512109SRekai.GonzalezAlberquilla@arm.com 11613610Sgiacomo.gabrielli@arm.com int 11713610Sgiacomo.gabrielli@arm.com flattenVecPredIndex(int reg) const 11813610Sgiacomo.gabrielli@arm.com { 11913610Sgiacomo.gabrielli@arm.com return reg; 12013610Sgiacomo.gabrielli@arm.com } 12113610Sgiacomo.gabrielli@arm.com 1229920Syasuko.eckert@amd.com // dummy 1239920Syasuko.eckert@amd.com int 12410035Sandreas.hansson@arm.com flattenCCIndex(int reg) const 1259920Syasuko.eckert@amd.com { 1269920Syasuko.eckert@amd.com return reg; 1279920Syasuko.eckert@amd.com } 1289920Syasuko.eckert@amd.com 12910033SAli.Saidi@ARM.com int 13010035Sandreas.hansson@arm.com flattenMiscIndex(int reg) const 13110033SAli.Saidi@ARM.com { 13210033SAli.Saidi@ARM.com return reg; 13310033SAli.Saidi@ARM.com } 13410033SAli.Saidi@ARM.com 1359461Snilay@cs.wisc.edu void startup(ThreadContext *tc) {} 1369461Snilay@cs.wisc.edu 1379553Sandreas.hansson@arm.com /// Explicitly import the otherwise hidden startup 1389553Sandreas.hansson@arm.com using SimObject::startup; 1399553Sandreas.hansson@arm.com 1409384SAndreas.Sandberg@arm.com const Params *params() const; 1419384SAndreas.Sandberg@arm.com 1429384SAndreas.Sandberg@arm.com ISA(Params *p); 1436691Stjones1@inf.ed.ac.uk}; 1446691Stjones1@inf.ed.ac.uk 1457811Ssteve.reinhardt@amd.com} // namespace PowerISA 1466691Stjones1@inf.ed.ac.uk 1476691Stjones1@inf.ed.ac.uk#endif // __ARCH_POWER_ISA_HH__ 148