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14279:0f25d914f4a8 |
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06-Sep-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: ISV bit in DataAbort should check for translation stage
According to the ESR spec, the ISV bit is set to 1 only for stage 2 aborts.
Change-Id: Id524ef36e82184f741e968ddba04ca8ccdd4ad58 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20980 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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14171:58d343fa3194 |
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15-Aug-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Replace direct use cpsr.el with currEL helper
The patch is replacing it in places where the current EL could be using AArch32, hence leading to an incorrect ExceptionLevel.
Change-Id: I99b75af2668f2c38fd88bec62e985ab7dbea80dc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20251 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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14128:6ed23d07d0d1 |
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28-Jul-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Implement ARMv8.1-PAN, Privileged access never
ARMv8.1-PAN adds a new bit to PSTATE. When the value of this PAN state bit is 1, any privileged data access from EL1 or EL2 to a virtual memory address that is accessible at EL0 generates a Permission fault. This feature is mandatory in ARMv8.1 implementations. This feature is supported in AArch64 and AArch32 states. The ID_AA64MMFR1_EL1.PAN, ID_MMFR3_EL1.PAN, and ID_MMFR3.PAN fields identify the support for ARMv8.1-PAN.
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Change-Id: I94a76311711739dd2394c72944d88ba9321fd159 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19729 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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14091:090449e74135 |
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11-Jun-2019 |
Gabor Dozsa <gabor.dozsa@arm.com> |
arch-arm: Add first-/non-faulting load instructions
First-/non-faulting loads are part of Arm SVE.
Change-Id: I93dfd6d1d74791653927e99098ddb651150a8ef7 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19177 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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13896:5a827a65bd1d |
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14-Feb-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Faults DebugFlag now printing inst opcode if available
This makes it easier to debug unimplemented instructions.
Change-Id: Iaaa288037326722f07251299fd68eacb2e295376 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18396 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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13895:5762b3dc79c6 |
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13-Feb-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Report real instruction encoding when Undefined
When dumping the opcode that caused an Undefined Instruction, we just want to dump the real instruction encoding, and not the extended version with metabits (like thumb, bigThumb etc). This was not appening when panicking in SE mode.
The patch is also replacing custom masking in the Unknown(64) disassembler in favour of ArmStaticInstruction::encoding() helper.
Change-Id: I9eb6fd145d02b4b07bb51f0bd89ca014d6d5a6de Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18395 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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13396:23277eaae855 |
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31-Oct-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32
ARMv8 differs from ARMv7 with the presence of RVBAR register, which contains the implementation defined reset address when EL3 is not implemented. The entry 0x0 in the AArch32 vector table, once used for the Reset Vector, is now marked as "Not used", stating that it is now IMPLEMENTATION DEFINED. An implementation might still use this vector table entry to hold the Reset vector, but having a Reset address != than the general vector table (for any other exception) is allowed.
At the moment any Reset exception is still using 0 as a vector table base address. This patch is extending the ArmSystem::resetAddr64 to ArmSystem::resetAddr so that it can be used for initializing MVBAR/RVBAR. In order to do so, we are providing a specialized behavior for the Reset exception when evaluating the vector base address.
Change-Id: I051a730dc089e194db3b107bbed19251c661f87e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14000 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13394:ebe487b6f18a |
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02-Nov-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Remove SCTLR.VE bit
ARMv8 has removed SCTLR.VE bit which is now hardcoded to 0. We are removing it from gem5 since we were not handling it anyway.
Change-Id: Ibde2db45c7f8add4a3188f2cb8c23701a6088d03 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13998 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12789:b28b286fa57d |
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05-Jun-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: AArch32 execution triggering AArch64 SW Break
AArch32 Software Breakpoint (BKPT) can trigger an AArch64 fault when interprocessing if the trapping conditions are met.
Change-Id: I485852ed19429f9cd928a6447a95eb6f471f189c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11197 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12764:5f812c4e0701 |
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29-May-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Adapting IllegalExecution fault for AArch32
The Illegal Execution fault triggered by the setting of processor state PSTATE.IL happens in AArch32 as well and takes the form of UNDEFINED exception fault. We are hence copying the UndefinedInstruction AArch32 fields into the IllegalInstSetStateFault.
Change-Id: Ibb7424397c2030ea5d010577c530277a27036aea Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10814 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12763:37c243ed1112 |
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29-May-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Add Illegal Execution flag to PCState
This patch moves the detection of the Illegal Execution flag (PSTATE.IL) from the tlb translation stage (fetch) to the decoding stage. This is done by adding the illegalExecution field to the PCState.
Change-Id: I9c1c4e9c6bd5ded905c1d56b3034e4e9322582fa Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10813 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12732:c8b4f25eea9b |
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22-May-2018 |
Andreas Sandberg <andreas.sandberg@arm.com> |
arch-arm: Adjust breakpoint EC depending on source state
The software breakpoint exception class needs to be adjusted depending on the source EL's execution state. This change fixes an incorrect exception class when taking a breakpoint from aarch64.
Change-Id: I99d87a04be6bf9ce3a69f6b19969fa006cfd63a4 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10809 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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12589:812b72ee214c |
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12-Mar-2018 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
arch-arm: Fix unused variable warning in faults.cc
Change-Id: Ife4a2189e140cdefcf53fa88213d8a5225067457 Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9201 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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12571:19063d7d209a |
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15-Feb-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Enable Debug IFSC when faulting to aarch64 mode
Previous code was aborting simulation when a debug exception taken in aarch64 mode was encountered. This because an invalid (0xff) instruction fault status code was produced.
Change-Id: I289f93f672be70cfbdc404be536809835160bdaf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8363 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12570:e32771e88250 |
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09-Feb-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Fix FSC generation in AbortFault
The fault status code generated by a Prefetch/Data Fault was containing a wrong value when the fault was triggered in aarch32 but handled in aarch64. This because the encoding differs between the two ISAs and the encoder was just checking the starting ISA rather than the the ending one. In this case the getFsr must be called after we know which is the ending ISA, which happens only after ArmFault::invoke gets called. The fsc update hence happens before writing into the Syndrome register.
Change-Id: I725f12b6dcc0178f608233bd3d15e466d1cd1ffc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8362 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12569:fe1ff4059715 |
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09-Feb-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Introduce update method in ArmFault class
There is a set of internal variables in ArmFault thats get updated once the fault is invoked (ArmFault::invoke). Sometimes we rely on those even if the fault is generated but not invoked (e.g. when checking if a memory access is producing a fault). This patch is moving the update functionalities inside a public method so that a client can make use of it even when not invoking the fault.
Change-Id: I3ac5b6835023f28ec569fe25487dffa356e1b2fd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8361 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12568:c82782e5a84c |
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20-Feb-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Fix PCAlignmentFault routing to Hypervisor
This patch enables PCAlignmentFault routing to Hypervisor in case HCR_EL2.TGE == 1, as is happening for other arm exceptions.
Change-Id: I48364ef1a0bcb5d030135221ae4bc6429e32759e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8841 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12517:77e8688fc670 |
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10-Feb-2017 |
Rekai Gonzalez-Alberquilla <rekai.gonzalezalberquilla@arm.com> |
sim: Make Stats truly non-copy-constructible
The stats are silently non-copy constructible. Therefore, when someone copy-constructs any object with stats, asserts happen when registering the stats, as they were not constructed in the intended way.
This patch solves that by explicitly deleting the copy constructor, trading an obscure run-time assert for a compile-time somehow more meaningful error meassage.
This triggers some compilation errors as the FaultStats in the fault definitions of ARM and SPARC use brace-enclosed initialisations in which one of the elements derives from DataWrap, which is not copy-constructible anymore. To fix that, this patch also adds a constructor for the FaultVals in both ISAs.
Change-Id: I340e203b9386609b32c66e3b8918a015afe415a4 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8082 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12512:cb5ebe30bb9e |
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28-Nov-2017 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Correct SecureMonitorTrap vals for aarch32
This patch replaces the dummy values which were defined for the SecureMonitorTrap thus enabling its usage in aarch32 mode. 1) It changes the vector table offset from 0x14 to 0x4 in compliance with the armv8 documentation. 2) When trapping in monitor mode for aarch32, the mon_lr is updated with the pc + a non zero offset (+4/2 depending on the current instruction set: +4 for A32, +2 for T32).
Change-Id: I01e1e52bf5ecd405e7472e31e01cf9a599153b08 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8041 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12511:99c28b88d4d8 |
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05-Jan-2018 |
Chuan Zhu <chuan.zhu@arm.com> |
arch-arm: Fixed error in choosing vector offset
The old code chose vector offset associated with exceptions taken to EL3 by incorrectly using "from64", which is associated with the exception level where the exception was taken from. However, the offset should depends on the ISA of the lower EL and not of the starting EL itself, as specified in ARM ARM. This patch corrects this by implementing the method in AArch64.TakeException in ARM ARM.
Change-Id: I8f7c9aa777c5f2eef9e2d89c36e9daee23f3a822 Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8001 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12509:aa16dce23e98 |
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15-Jan-2018 |
Chuan Zhu <chuan.zhu@arm.com> |
arch-arm: Handle route to EL2 in Supervisor Trap
Supervisor Trap is supposed to be able to handle exceptions routed to EL2, which is enabled by HCR_EL2.TGE. This fix adds routeToHyp() function to Supervisor Trap to handle this, similar to that in UndefinedFault, DataAbort, etc.
Change-Id: I1fcf9f2d445ecbc13c8f6d3b7d599728b0250ab7 Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7961 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12402:a90842ce2303 |
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01-Dec-2017 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Hyp routed undef fault need to change its syndrome
If undefined instruction has to be routed to EL2, the HSR register must change the HSR.EC and HSR.ISS accordingly, which means not using the EL1 exception syndrome, but the unknown reason one (EC=0, ISS=0)
Change-Id: I1540c713ab545bf307c1dad3ae305de4178443f4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6621 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12398:5c48d7e08ba0 |
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15-Dec-2017 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Change casting type from reinterpret to static
Cosmetic fix: prefer static_cast rather than reinterpret_cast in hierarchy.
Change-Id: Ic0e5a4df9b18072a6df5ee316f674241074c349a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6761 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12299:c54efdd48952 |
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23-Jun-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
arch-arm: Add support for the brk instruction
Add support for software breakpoints as signalled by the aarch64 brk instruction. This introduces a new SoftwareBreakpoint fault.
Change-Id: I93646c3298e09d7f7b0983108ba8937c7331297a Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5721 Reviewed-by: Giacomo Gabrielli <Giacomo.Gabrielli@arm.com>
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12259:f787f664d57a |
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20-Oct-2017 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Removing FlushPipe fault, using SquashAfter
This Patch is removing the FlushPipe ArmFault, which was used for flushing the pipeline in favour of the general IsSquashAfter StaticInstr flag. Using a fault was preventing tracers from tracing barriers like ISB and from adding them to the instruction count
Change-Id: I176e9254eca904694f2f611eb486c55e50ec61ff Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5361 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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11877:5ea85692a53e |
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20-Jul-2015 |
Brandon Potter <brandon.potter@amd.com> |
syscall_emul: [patch 13/22] add system call retry capability
This changeset adds functionality that allows system calls to retry without affecting thread context state such as the program counter or register values for the associated thread context (when system calls return with a retry fault).
This functionality is needed to solve problems with blocking system calls in multi-process or multi-threaded simulations where information is passed between processes/threads. Blocking system calls can cause deadlock because the simulator itself is single threaded. There is only a single thread servicing the event queue which can cause deadlock if the thread hits a blocking system call instruction.
To illustrate the problem, consider two processes using the producer/consumer sharing model. The processes can use file descriptors and the read and write calls to pass information to one another. If the consumer calls the blocking read system call before the producer has produced anything, the call will block the event queue (while executing the system call instruction) and deadlock the simulation.
The solution implemented in this changeset is to recognize that the system calls will block and then generate a special retry fault. The fault will be sent back up through the function call chain until it is exposed to the cpu model's pipeline where the fault becomes visible. The fault will trigger the cpu model to replay the instruction at a future tick where the call has a chance to succeed without actually going into a blocking state.
In subsequent patches, we recognize that a syscall will block by calling a non-blocking poll (from inside the system call implementation) and checking for events. When events show up during the poll, it signifies that the call would not have blocked and the syscall is allowed to proceed (calling an underlying host system call if necessary). If no events are returned from the poll, we generate the fault and try the instruction for the thread context at a distant tick. Note that retrying every tick is not efficient.
As an aside, the simulator has some multi-threading support for the event queue, but it is not used by default and needs work. Even if the event queue was completely multi-threaded, meaning that there is a hardware thread on the host servicing a single simulator thread contexts with a 1:1 mapping between them, it's still possible to run into deadlock due to the event queue barriers on quantum boundaries. The solution of replaying at a later tick is the simplest solution and solves the problem generally.
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11793:ef606668d247 |
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09-Nov-2016 |
Brandon Potter <brandon.potter@amd.com> |
style: [patch 1/22] use /r/3648/ to reorganize includes
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11585:83784c48fb73 |
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02-Aug-2016 |
Dylan Johnson <Dylan.Johnson@ARM.com> |
arm: correctly assign faulting IPA's to HPFAR_EL2
This patch corrects IPA reporting if the translation faults in a stage 2 lookup.
Change-Id: I0b914527f8a9f98a5e980a131cf9d03e5584b4e9
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11581:d6cfd0be73b2 |
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02-Aug-2016 |
Dylan Johnson <Dylan.Johnson@ARM.com> |
arm: Fix secure state checking in various places
Faults that could potentially be routed to the hypervisor checked whether or not they were in a secure state without checking if security was enabled or not. This caused faults not to be routed correctly. This patch causes secure state checking to first ask if security is enabled.
Change-Id: I179e9b181b27f552734c9bab2b18d05ac579a119
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11578:10a0ce0e358c |
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02-Aug-2016 |
Dylan Johnson <Dylan.Johnson@ARM.com> |
arm: Add check to fault routing for hypervisor/virtualization
This patch adds the option for faults to be routed to the hypervisor using the pre-existing routeToHyp() functions that are present in each fault type.
Change-Id: I9735512c094457636b9870456a5be5432288e004
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11576:9ff589e30935 |
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02-Aug-2016 |
Dylan Johnson <Dylan.Johnson@ARM.com> |
arm: Add AArch64 hypervisor call instruction 'hvc'
This patch adds the AArch64 instruction hvc which raises an exception from EL1 into EL2. The host OS uses this instruction to world switch into the guest.
Change-Id: I930ee43f4f0abd4b35a68eb2a72e44e3ea6570be
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11574:868c31fcca24 |
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02-Aug-2016 |
Curtis Dunham <Curtis.Dunham@arm.com> |
arm: enable EL2 support
Change-Id: I59fa4fae98c33d9e5c2185382e1411911d27d341
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11496:8e14075966d0 |
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27-May-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
arm: Use the target EL state when determining fault format
We currently check the current state instead of the state of the target EL when determining how we report a fault. This breaks interprocessing since EL0 in aarch32 would report its fault status using the aarch32 registers even if EL1 is in aarch64. Fix this to report the fault using the format of the target EL.
Change-Id: Ic080267ac210783d1e01c722a4ddaa687dce280e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>
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11150:a8a64cca231b |
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30-Sep-2015 |
Mitch Hayenga <mitch.hayenga@arm.com> |
isa,cpu: Add support for FS SMT Interrupts
Adds per-thread interrupt controllers and thread/context logic so that interrupts properly get routed in SMT systems.
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10417:710ee116eb68 |
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27-Sep-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
arch: Use const StaticInstPtr references where possible
This patch optimises the passing of StaticInstPtr by avoiding copying the reference-counting pointer. This avoids first incrementing and then decrementing the reference-counting pointer.
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10367:bf52480abd01 |
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12-Sep-2014 |
Andrew Bardsley <Andrew.Bardsley@arm.com> |
style: Fix line continuation, especially in debug messages
This patch closes a number of space gaps in debug messages caused by the incorrect use of line continuation within strings. (There's also one consistency change to a similar, but correct, use of line continuation)
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10338:8bee5f4edb92 |
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29-Apr-2014 |
Curtis Dunham <Curtis.Dunham@arm.com> |
arm: use condition code registers for ARM ISA
Analogous to ee049bf (for x86). Requires a bump of the checkpoint version and corresponding upgrader code to move the condition code register values to the new register file.
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10037:5cac77888310 |
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24-Jan-2014 |
ARM gem5 Developers |
arm: Add support for ARMv8 (AArch64 & AArch32)
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch.
Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch.
Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
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9551:f867e530f39b |
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19-Feb-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
scons: Add warning for missing field initializers
This patch adds a warning for missing field initializers for both gcc and clang, and addresses the warnings that were generated.
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8806:669e93d79ed9 |
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29-Jan-2012 |
Gabe Black <gblack@eecs.umich.edu> |
Implement Ali's review feedback.
Try to decrease indentation, and remove some redundant FullSystem checks.
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8782:10c9297e14d5 |
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02-Nov-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.
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8545:a3992291e230 |
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13-Sep-2011 |
Ali Saidi <saidi@eecs.umich.edu> |
LSQ: Only trigger a memory violation with a load/load if the value changes.
Only create a memory ordering violation when the value could have changed between two subsequent loads, instead of just when loads go out-of-order to the same address. While not very common in the case of Alpha, with an architecture with a hardware table walker this can happen reasonably frequently beacuse a translation will miss and start a table walk and before the CPU re-schedules the faulting instruction another one will pass it to the same address (or cache block depending on the dendency checking).
This patch has been tested with a couple of self-checking hand crafted programs to stress ordering between two cores.
The performance improvement on SPEC benchmarks can be substantial (2-10%).
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8518:9c87727099ce |
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19-Aug-2011 |
Geoffrey Blake <geoffrey.blake@arm.com> |
Fix bugs due to interaction between SEV instructions and O3 pipeline
SEV instructions were originally implemented to cause asynchronous squashes via the generateTCSquash() function in the O3 pipeline when updating the SEV_MAILBOX miscReg. This caused race conditions between CPUs in an MP system that would lead to a pipeline either going inactive indefinitely or not being able to commit squashed instructions. Fixed SEV instructions to behave like interrupts and cause synchronous sqaushes inside the pipeline, eliminating the race conditions. Also fixed up the semantics of the WFE instruction to behave as documented in the ARMv7 ISA description to not sleep if SEV_MAILBOX=1 or unmasked interrupts are pending.
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8314:13ac7b9939ef |
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23-May-2011 |
Geoffrey Blake <geoffrey.blake@arm.com> |
O3: Fix issue with interrupts/faults occuring in the middle of a macro-op
This patch fixes two problems with the O3 cpu model. The first is an issue with an instruction fetch causing a fault on the next address while the current macro-op is being issued. This happens when the micro-ops exceed the fetch bandwdith and then on the next cycle the fetch stage attempts to issue a request to the next line while it still has micro-ops to issue if the next line faults a fault is attached to a micro-op in the currently executing macro-op rather than a "nop" from the next instruction block. This leads to an instruction incorrectly faulting when on fetch when it had no reason to fault.
A similar problem occurs with interrupts. When an interrupt occurs the fetch stage nominally stops issuing instructions immediately. This is incorrect in the case of a macro-op as the current location might not be interruptable.
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8303:5a95f1d2494e |
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13-May-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Further break up condition code into NZ, C, V bits.
Break up the condition code bits into NZ, C, V registers. These are individually written and this removes some incorrect dependencies between instructions.
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8302:9f23d01421de |
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13-May-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Remove the saturating (Q) condition code from the renamed register.
Move the saturating bit (which is also saturating) from the renamed register that holds the flags to the CPSR miscreg and adds a allows setting it in a similar way to the FP saturating registers. This removes a dependency in instructions that don't write, but need to preserve the Q bit.
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8301:858384f3af1c |
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13-May-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Break up condition codes into normal flags, saturation, and simd.
This change splits out the condcodes from being one monolithic register into three blocks that are updated independently. This allows CPUs to not have to do RMW operations on the flags registers for instructions that don't write all flags.
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8232:b28d06a175be |
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15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help
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8229:78bf55f23338 |
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15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
includes: sort all includes
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8205:7ecbffb674aa |
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04-Apr-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Cleanup implementation of ITSTATE and put important code in PCState.
Consolidate all code to handle ITSTATE in the PCState object rather than touching a variety of structures/objects.
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8202:1b63e9afeafc |
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04-Apr-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Fix table walk going on while ASID changes error
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8076:323e63527496 |
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23-Feb-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Set ITSTATE correctly after FlushPipe
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8063:eea37fdcfc11 |
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23-Feb-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Delete OABI syscall handling.
We only support EABI binaries, so there is no reason to support OABI syscalls. The loader detects OABI calls and fatal() so there is no reason to even check here.
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7720:65d338a8dba4 |
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31-Oct-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way.
PC type:
Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM.
These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later.
Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses.
Advancing the PC:
The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements.
One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now.
Variable length instructions:
To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back.
ISA parser:
To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out.
Return address stack:
The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works.
Change in stats:
There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS.
TODO:
Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
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7692:8173327c9c65 |
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01-Oct-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Clean up use of TBit and JBit.
Rather tha constantly using ULL(1) << PcXBitShift define those directly. Additionally, add some helper functions to further clean up the code.
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7678:f19b6a3a8cec |
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13-Sep-2010 |
Gabe Black <gblack@eecs.umich.edu> |
Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.
Also move the "Fault" reference counted pointer type into a separate file, sim/fault.hh. It would be better to name this less similarly to sim/faults.hh to reduce confusion, but fault.hh matches the name of the type. We could change Fault to FaultPtr to match other pointer types, and then changing the name of the file would make more sense.
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7652:f2621206b062 |
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25-Aug-2010 |
Min Kyu Jeong <minkyu.jeong@arm.com> |
ARM: Adding a bogus fault that does nothing. This fault can used to flush the pipe, not including the faulting instruction.
The particular case I needed this was for a self-modifying code. It needed to drain the store queue and force the following instruction to refetch from icache. DCCMVAC cp15 mcr instruction is modified to raise this fault.
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7640:5286a8a469c5 |
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25-Aug-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Implement CPACR register and return Undefined Instruction when FP access is disabled.
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7585:afbc40280b56 |
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23-Aug-2010 |
Ali Saidi <Ali.Saidi@arm.com> |
ARM: Add system for ARM/Linux and bootstrapping
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7426:5da64155a605 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Get rid of the binary dumping function in utility.hh.
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7412:b62d0343ad8f |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Make sure the upc is zeroed when vectoring to a fault.
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7400:f6c9b27c4dbe |
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02-Jun-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Implement ARM CPU interrupts
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7362:9ea92e0eb4a9 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Implement and update the DFSR and IFSR registers on faults.
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7302:d9b1ad210629 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Set CPSR.E to SCTLR.EE on faults.
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7295:afc0f5c08e99 |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Zero the micropc when vectoring to a fault.
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7197:21b9790c446d |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Trigger system calls from the SupervisorCall invoke method.
This simplifies the decoder slightly, and makes the system call mechanism very slightly more realistic.
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7189:28998288c48b |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Rework how unrecognized/unimplemented instructions are handled.
Instead of panic immediately when these instructions are executed, an UndefinedInstruction fault is returned. In FS mode (not currently implemented), this is the fault that should, to my knowledge, be triggered in these situations and should be handled using the normal architected mechanisms. In SE mode, the fault causes a panic when it's invoked that gives the same information as the instruction did. When/if support for speculative execution of ARM is supported, this will allow a mispeculated and unrecognized and/or unimplemented instruction from causing a panic. Only once the instruction is going to be committed will the fault be invoked, triggering the panic.
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7093:9832d4b070fc |
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02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Track the current ISA mode using the PC.
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6735:6437ad24a8a0 |
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10-Nov-2009 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Implement fault classes.
Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.
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6326:008930a4ace5 |
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09-Jul-2009 |
Gabe Black <gblack@eecs.umich.edu> |
Registers: Eliminate the ISA defined RegFile class.
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6019:76890d8b28f5 |
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05-Apr-2009 |
Stephen Hines <hines@cs.fsu.edu> |
arm: add ARM support to M5
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