faults.cc revision 12402:a90842ce2303
1/* 2 * Copyright (c) 2010, 2012-2014, 2016-2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * Copyright (c) 2007-2008 The Florida State University 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Ali Saidi 42 * Gabe Black 43 * Giacomo Gabrielli 44 * Thomas Grocutt 45 */ 46 47#include "arch/arm/faults.hh" 48 49#include "arch/arm/insts/static_inst.hh" 50#include "arch/arm/system.hh" 51#include "arch/arm/utility.hh" 52#include "base/compiler.hh" 53#include "base/trace.hh" 54#include "cpu/base.hh" 55#include "cpu/thread_context.hh" 56#include "debug/Faults.hh" 57#include "sim/full_system.hh" 58 59namespace ArmISA 60{ 61 62uint8_t ArmFault::shortDescFaultSources[] = { 63 0x01, // AlignmentFault 64 0x04, // InstructionCacheMaintenance 65 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID) 66 0x0c, // SynchExtAbtOnTranslTableWalkL1 67 0x0e, // SynchExtAbtOnTranslTableWalkL2 68 0xff, // SynchExtAbtOnTranslTableWalkL3 (INVALID) 69 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID) 70 0x1c, // SynchPtyErrOnTranslTableWalkL1 71 0x1e, // SynchPtyErrOnTranslTableWalkL2 72 0xff, // SynchPtyErrOnTranslTableWalkL3 (INVALID) 73 0xff, // TranslationL0 (INVALID) 74 0x05, // TranslationL1 75 0x07, // TranslationL2 76 0xff, // TranslationL3 (INVALID) 77 0xff, // AccessFlagL0 (INVALID) 78 0x03, // AccessFlagL1 79 0x06, // AccessFlagL2 80 0xff, // AccessFlagL3 (INVALID) 81 0xff, // DomainL0 (INVALID) 82 0x09, // DomainL1 83 0x0b, // DomainL2 84 0xff, // DomainL3 (INVALID) 85 0xff, // PermissionL0 (INVALID) 86 0x0d, // PermissionL1 87 0x0f, // PermissionL2 88 0xff, // PermissionL3 (INVALID) 89 0x02, // DebugEvent 90 0x08, // SynchronousExternalAbort 91 0x10, // TLBConflictAbort 92 0x19, // SynchPtyErrOnMemoryAccess 93 0x16, // AsynchronousExternalAbort 94 0x18, // AsynchPtyErrOnMemoryAccess 95 0xff, // AddressSizeL0 (INVALID) 96 0xff, // AddressSizeL1 (INVALID) 97 0xff, // AddressSizeL2 (INVALID) 98 0xff, // AddressSizeL3 (INVALID) 99 0x40, // PrefetchTLBMiss 100 0x80 // PrefetchUncacheable 101}; 102 103static_assert(sizeof(ArmFault::shortDescFaultSources) == 104 ArmFault::NumFaultSources, 105 "Invalid size of ArmFault::shortDescFaultSources[]"); 106 107uint8_t ArmFault::longDescFaultSources[] = { 108 0x21, // AlignmentFault 109 0xff, // InstructionCacheMaintenance (INVALID) 110 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID) 111 0x15, // SynchExtAbtOnTranslTableWalkL1 112 0x16, // SynchExtAbtOnTranslTableWalkL2 113 0x17, // SynchExtAbtOnTranslTableWalkL3 114 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID) 115 0x1d, // SynchPtyErrOnTranslTableWalkL1 116 0x1e, // SynchPtyErrOnTranslTableWalkL2 117 0x1f, // SynchPtyErrOnTranslTableWalkL3 118 0xff, // TranslationL0 (INVALID) 119 0x05, // TranslationL1 120 0x06, // TranslationL2 121 0x07, // TranslationL3 122 0xff, // AccessFlagL0 (INVALID) 123 0x09, // AccessFlagL1 124 0x0a, // AccessFlagL2 125 0x0b, // AccessFlagL3 126 0xff, // DomainL0 (INVALID) 127 0x3d, // DomainL1 128 0x3e, // DomainL2 129 0xff, // DomainL3 (RESERVED) 130 0xff, // PermissionL0 (INVALID) 131 0x0d, // PermissionL1 132 0x0e, // PermissionL2 133 0x0f, // PermissionL3 134 0x22, // DebugEvent 135 0x10, // SynchronousExternalAbort 136 0x30, // TLBConflictAbort 137 0x18, // SynchPtyErrOnMemoryAccess 138 0x11, // AsynchronousExternalAbort 139 0x19, // AsynchPtyErrOnMemoryAccess 140 0xff, // AddressSizeL0 (INVALID) 141 0xff, // AddressSizeL1 (INVALID) 142 0xff, // AddressSizeL2 (INVALID) 143 0xff, // AddressSizeL3 (INVALID) 144 0x40, // PrefetchTLBMiss 145 0x80 // PrefetchUncacheable 146}; 147 148static_assert(sizeof(ArmFault::longDescFaultSources) == 149 ArmFault::NumFaultSources, 150 "Invalid size of ArmFault::longDescFaultSources[]"); 151 152uint8_t ArmFault::aarch64FaultSources[] = { 153 0x21, // AlignmentFault 154 0xff, // InstructionCacheMaintenance (INVALID) 155 0x14, // SynchExtAbtOnTranslTableWalkL0 156 0x15, // SynchExtAbtOnTranslTableWalkL1 157 0x16, // SynchExtAbtOnTranslTableWalkL2 158 0x17, // SynchExtAbtOnTranslTableWalkL3 159 0x1c, // SynchPtyErrOnTranslTableWalkL0 160 0x1d, // SynchPtyErrOnTranslTableWalkL1 161 0x1e, // SynchPtyErrOnTranslTableWalkL2 162 0x1f, // SynchPtyErrOnTranslTableWalkL3 163 0x04, // TranslationL0 164 0x05, // TranslationL1 165 0x06, // TranslationL2 166 0x07, // TranslationL3 167 0x08, // AccessFlagL0 168 0x09, // AccessFlagL1 169 0x0a, // AccessFlagL2 170 0x0b, // AccessFlagL3 171 // @todo: Section & Page Domain Fault in AArch64? 172 0xff, // DomainL0 (INVALID) 173 0xff, // DomainL1 (INVALID) 174 0xff, // DomainL2 (INVALID) 175 0xff, // DomainL3 (INVALID) 176 0x0c, // PermissionL0 177 0x0d, // PermissionL1 178 0x0e, // PermissionL2 179 0x0f, // PermissionL3 180 0xff, // DebugEvent (INVALID) 181 0x10, // SynchronousExternalAbort 182 0x30, // TLBConflictAbort 183 0x18, // SynchPtyErrOnMemoryAccess 184 0xff, // AsynchronousExternalAbort (INVALID) 185 0xff, // AsynchPtyErrOnMemoryAccess (INVALID) 186 0x00, // AddressSizeL0 187 0x01, // AddressSizeL1 188 0x02, // AddressSizeL2 189 0x03, // AddressSizeL3 190 0x40, // PrefetchTLBMiss 191 0x80 // PrefetchUncacheable 192}; 193 194static_assert(sizeof(ArmFault::aarch64FaultSources) == 195 ArmFault::NumFaultSources, 196 "Invalid size of ArmFault::aarch64FaultSources[]"); 197 198// Fields: name, offset, cur{ELT,ELH}Offset, lowerEL{64,32}Offset, next mode, 199// {ARM, Thumb, ARM_ELR, Thumb_ELR} PC offset, hyp trap, 200// {A, F} disable, class, stat 201template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals = { 202 // Some dummy values (the reset vector has an IMPLEMENTATION DEFINED 203 // location in AArch64) 204 "Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 205 0, 0, 0, 0, false, true, true, EC_UNKNOWN, FaultStat() 206}; 207template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals = { 208 "Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 209 4, 2, 0, 0, true, false, false, EC_UNKNOWN, FaultStat() 210}; 211template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals = { 212 "Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 213 4, 2, 4, 2, true, false, false, EC_SVC_TO_HYP, FaultStat() 214}; 215template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals = { 216 "Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON, 217 4, 4, 4, 4, false, true, true, EC_SMC_TO_HYP, FaultStat() 218}; 219template<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals = { 220 "Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 221 4, 4, 4, 4, true, false, false, EC_HVC, FaultStat() 222}; 223template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals = { 224 "Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 225 4, 4, 0, 0, true, true, false, EC_PREFETCH_ABORT_TO_HYP, FaultStat() 226}; 227template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals = { 228 "Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 229 8, 8, 0, 0, true, true, false, EC_DATA_ABORT_TO_HYP, FaultStat() 230}; 231template<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals = { 232 "Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 233 8, 8, 0, 0, true, true, false, EC_INVALID, FaultStat() 234}; 235template<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals = { 236 // @todo: double check these values 237 "Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 238 0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat() 239}; 240template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals = { 241 "IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 242 4, 4, 0, 0, false, true, false, EC_UNKNOWN, FaultStat() 243}; 244template<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals = { 245 "Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 246 4, 4, 0, 0, false, true, false, EC_INVALID, FaultStat() 247}; 248template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals = { 249 "FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 250 4, 4, 0, 0, false, true, true, EC_UNKNOWN, FaultStat() 251}; 252template<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals = { 253 "Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 254 4, 4, 0, 0, false, true, true, EC_INVALID, FaultStat() 255}; 256template<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals = { 257 // Some dummy values (SupervisorTrap is AArch64-only) 258 "Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 259 0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat() 260}; 261template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals = { 262 // Some dummy values (SecureMonitorTrap is AArch64-only) 263 "Secure Monitor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_MON, 264 0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat() 265}; 266template<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals = { 267 // Some dummy values (PCAlignmentFault is AArch64-only) 268 "PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 269 0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT, FaultStat() 270}; 271template<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals = { 272 // Some dummy values (SPAlignmentFault is AArch64-only) 273 "SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 274 0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT, FaultStat() 275}; 276template<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals = { 277 // Some dummy values (SError is AArch64-only) 278 "SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC, 279 0, 0, 0, 0, false, true, true, EC_SERROR, FaultStat() 280}; 281template<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals = { 282 // Some dummy values (SoftwareBreakpoint is AArch64-only) 283 "Software Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 284 0, 0, 0, 0, true, false, false, EC_SOFTWARE_BREAKPOINT, FaultStat() 285}; 286template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals = { 287 // Some dummy values 288 "ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 289 0, 0, 0, 0, false, true, true, EC_UNKNOWN, FaultStat() 290}; 291template<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals = { 292 // Some dummy values (SPAlignmentFault is AArch64-only) 293 "Illegal Inst Set State Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 294 0, 0, 0, 0, true, false, false, EC_ILLEGAL_INST, FaultStat() 295}; 296 297Addr 298ArmFault::getVector(ThreadContext *tc) 299{ 300 Addr base; 301 302 // ARM ARM issue C B1.8.1 303 bool haveSecurity = ArmSystem::haveSecurity(tc); 304 305 // panic if SCTLR.VE because I have no idea what to do with vectored 306 // interrupts 307 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 308 assert(!sctlr.ve); 309 // Check for invalid modes 310 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 311 assert(haveSecurity || cpsr.mode != MODE_MON); 312 assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP); 313 314 switch (cpsr.mode) 315 { 316 case MODE_MON: 317 base = tc->readMiscReg(MISCREG_MVBAR); 318 break; 319 case MODE_HYP: 320 base = tc->readMiscReg(MISCREG_HVBAR); 321 break; 322 default: 323 if (sctlr.v) { 324 base = HighVecs; 325 } else { 326 base = haveSecurity ? tc->readMiscReg(MISCREG_VBAR) : 0; 327 } 328 break; 329 } 330 return base + offset(tc); 331} 332 333Addr 334ArmFault::getVector64(ThreadContext *tc) 335{ 336 Addr vbar; 337 switch (toEL) { 338 case EL3: 339 assert(ArmSystem::haveSecurity(tc)); 340 vbar = tc->readMiscReg(MISCREG_VBAR_EL3); 341 break; 342 case EL2: 343 assert(ArmSystem::haveVirtualization(tc)); 344 vbar = tc->readMiscReg(MISCREG_VBAR_EL2); 345 break; 346 case EL1: 347 vbar = tc->readMiscReg(MISCREG_VBAR_EL1); 348 break; 349 default: 350 panic("Invalid target exception level"); 351 break; 352 } 353 return vbar + offset64(); 354} 355 356MiscRegIndex 357ArmFault::getSyndromeReg64() const 358{ 359 switch (toEL) { 360 case EL1: 361 return MISCREG_ESR_EL1; 362 case EL2: 363 return MISCREG_ESR_EL2; 364 case EL3: 365 return MISCREG_ESR_EL3; 366 default: 367 panic("Invalid exception level"); 368 break; 369 } 370} 371 372MiscRegIndex 373ArmFault::getFaultAddrReg64() const 374{ 375 switch (toEL) { 376 case EL1: 377 return MISCREG_FAR_EL1; 378 case EL2: 379 return MISCREG_FAR_EL2; 380 case EL3: 381 return MISCREG_FAR_EL3; 382 default: 383 panic("Invalid exception level"); 384 break; 385 } 386} 387 388void 389ArmFault::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) 390{ 391 uint32_t value; 392 uint32_t exc_class = (uint32_t) ec(tc); 393 uint32_t issVal = iss(); 394 395 assert(!from64 || ArmSystem::highestELIs64(tc)); 396 397 value = exc_class << 26; 398 399 // HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts (0x24, 400 // 0x25) for which the ISS information is not valid (ARMv7). 401 // @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not 402 // valid it is treated as RES1. 403 if (to64) { 404 value |= 1 << 25; 405 } else if ((bits(exc_class, 5, 3) != 4) || 406 (bits(exc_class, 2) && bits(issVal, 24))) { 407 if (!machInst.thumb || machInst.bigThumb) 408 value |= 1 << 25; 409 } 410 // Condition code valid for EC[5:4] nonzero 411 if (!from64 && ((bits(exc_class, 5, 4) == 0) && 412 (bits(exc_class, 3, 0) != 0))) { 413 if (!machInst.thumb) { 414 uint32_t cond; 415 ConditionCode condCode = (ConditionCode) (uint32_t) machInst.condCode; 416 // If its on unconditional instruction report with a cond code of 417 // 0xE, ie the unconditional code 418 cond = (condCode == COND_UC) ? COND_AL : condCode; 419 value |= cond << 20; 420 value |= 1 << 24; 421 } 422 value |= bits(issVal, 19, 0); 423 } else { 424 value |= issVal; 425 } 426 tc->setMiscReg(syndrome_reg, value); 427} 428 429void 430ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 431{ 432 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 433 434 if (ArmSystem::highestELIs64(tc)) { // ARMv8 435 // Determine source exception level and mode 436 fromMode = (OperatingMode) (uint8_t) cpsr.mode; 437 fromEL = opModeToEL(fromMode); 438 if (opModeIs64(fromMode)) 439 from64 = true; 440 441 // Determine target exception level 442 if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc)) { 443 toEL = EL3; 444 } else if (ArmSystem::haveVirtualization(tc) && routeToHyp(tc)) { 445 toEL = EL2; 446 hypRouted = true; 447 } else { 448 toEL = opModeToEL(nextMode()); 449 } 450 451 if (fromEL > toEL) 452 toEL = fromEL; 453 454 if (toEL == ArmSystem::highestEL(tc) || ELIs64(tc, toEL)) { 455 // Invoke exception handler in AArch64 state 456 to64 = true; 457 invoke64(tc, inst); 458 return; 459 } 460 } 461 462 // ARMv7 (ARM ARM issue C B1.9) 463 464 bool have_security = ArmSystem::haveSecurity(tc); 465 bool have_virtualization = ArmSystem::haveVirtualization(tc); 466 467 FaultBase::invoke(tc); 468 if (!FullSystem) 469 return; 470 countStat()++; 471 472 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 473 SCR scr = tc->readMiscReg(MISCREG_SCR); 474 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR); 475 saved_cpsr.nz = tc->readCCReg(CCREG_NZ); 476 saved_cpsr.c = tc->readCCReg(CCREG_C); 477 saved_cpsr.v = tc->readCCReg(CCREG_V); 478 saved_cpsr.ge = tc->readCCReg(CCREG_GE); 479 480 Addr curPc M5_VAR_USED = tc->pcState().pc(); 481 ITSTATE it = tc->pcState().itstate(); 482 saved_cpsr.it2 = it.top6; 483 saved_cpsr.it1 = it.bottom2; 484 485 // if we have a valid instruction then use it to annotate this fault with 486 // extra information. This is used to generate the correct fault syndrome 487 // information 488 if (inst) { 489 ArmStaticInst *armInst = static_cast<ArmStaticInst *>(inst.get()); 490 armInst->annotateFault(this); 491 } 492 493 if (have_security && routeToMonitor(tc)) { 494 cpsr.mode = MODE_MON; 495 } else if (have_virtualization && routeToHyp(tc)) { 496 cpsr.mode = MODE_HYP; 497 hypRouted = true; 498 } else { 499 cpsr.mode = nextMode(); 500 } 501 502 // Ensure Secure state if initially in Monitor mode 503 if (have_security && saved_cpsr.mode == MODE_MON) { 504 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 505 if (scr.ns) { 506 scr.ns = 0; 507 tc->setMiscRegNoEffect(MISCREG_SCR, scr); 508 } 509 } 510 511 // some bits are set differently if we have been routed to hyp mode 512 if (cpsr.mode == MODE_HYP) { 513 SCTLR hsctlr = tc->readMiscReg(MISCREG_HSCTLR); 514 cpsr.t = hsctlr.te; 515 cpsr.e = hsctlr.ee; 516 if (!scr.ea) {cpsr.a = 1;} 517 if (!scr.fiq) {cpsr.f = 1;} 518 if (!scr.irq) {cpsr.i = 1;} 519 } else if (cpsr.mode == MODE_MON) { 520 // Special case handling when entering monitor mode 521 cpsr.t = sctlr.te; 522 cpsr.e = sctlr.ee; 523 cpsr.a = 1; 524 cpsr.f = 1; 525 cpsr.i = 1; 526 } else { 527 cpsr.t = sctlr.te; 528 cpsr.e = sctlr.ee; 529 530 // The *Disable functions are virtual and different per fault 531 cpsr.a = cpsr.a | abortDisable(tc); 532 cpsr.f = cpsr.f | fiqDisable(tc); 533 cpsr.i = 1; 534 } 535 cpsr.it1 = cpsr.it2 = 0; 536 cpsr.j = 0; 537 tc->setMiscReg(MISCREG_CPSR, cpsr); 538 539 // Make sure mailbox sets to one always 540 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 541 542 // Clear the exclusive monitor 543 tc->setMiscReg(MISCREG_LOCKFLAG, 0); 544 545 if (cpsr.mode == MODE_HYP) { 546 tc->setMiscReg(MISCREG_ELR_HYP, curPc + 547 (saved_cpsr.t ? thumbPcOffset(true) : armPcOffset(true))); 548 } else { 549 tc->setIntReg(INTREG_LR, curPc + 550 (saved_cpsr.t ? thumbPcOffset(false) : armPcOffset(false))); 551 } 552 553 switch (cpsr.mode) { 554 case MODE_FIQ: 555 tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr); 556 break; 557 case MODE_IRQ: 558 tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr); 559 break; 560 case MODE_SVC: 561 tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr); 562 break; 563 case MODE_MON: 564 assert(have_security); 565 tc->setMiscReg(MISCREG_SPSR_MON, saved_cpsr); 566 break; 567 case MODE_ABORT: 568 tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr); 569 break; 570 case MODE_UNDEFINED: 571 tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr); 572 if (ec(tc) != EC_UNKNOWN) 573 setSyndrome(tc, MISCREG_HSR); 574 break; 575 case MODE_HYP: 576 assert(have_virtualization); 577 tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr); 578 setSyndrome(tc, MISCREG_HSR); 579 break; 580 default: 581 panic("unknown Mode\n"); 582 } 583 584 Addr newPc = getVector(tc); 585 DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n", 586 name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc); 587 PCState pc(newPc); 588 pc.thumb(cpsr.t); 589 pc.nextThumb(pc.thumb()); 590 pc.jazelle(cpsr.j); 591 pc.nextJazelle(pc.jazelle()); 592 pc.aarch64(!cpsr.width); 593 pc.nextAArch64(!cpsr.width); 594 tc->pcState(pc); 595} 596 597void 598ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst) 599{ 600 // Determine actual misc. register indices for ELR_ELx and SPSR_ELx 601 MiscRegIndex elr_idx, spsr_idx; 602 switch (toEL) { 603 case EL1: 604 elr_idx = MISCREG_ELR_EL1; 605 spsr_idx = MISCREG_SPSR_EL1; 606 break; 607 case EL2: 608 assert(ArmSystem::haveVirtualization(tc)); 609 elr_idx = MISCREG_ELR_EL2; 610 spsr_idx = MISCREG_SPSR_EL2; 611 break; 612 case EL3: 613 assert(ArmSystem::haveSecurity(tc)); 614 elr_idx = MISCREG_ELR_EL3; 615 spsr_idx = MISCREG_SPSR_EL3; 616 break; 617 default: 618 panic("Invalid target exception level"); 619 break; 620 } 621 622 // Save process state into SPSR_ELx 623 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 624 CPSR spsr = cpsr; 625 spsr.nz = tc->readCCReg(CCREG_NZ); 626 spsr.c = tc->readCCReg(CCREG_C); 627 spsr.v = tc->readCCReg(CCREG_V); 628 if (from64) { 629 // Force some bitfields to 0 630 spsr.q = 0; 631 spsr.it1 = 0; 632 spsr.j = 0; 633 spsr.res0_23_22 = 0; 634 spsr.ge = 0; 635 spsr.it2 = 0; 636 spsr.t = 0; 637 } else { 638 spsr.ge = tc->readCCReg(CCREG_GE); 639 ITSTATE it = tc->pcState().itstate(); 640 spsr.it2 = it.top6; 641 spsr.it1 = it.bottom2; 642 // Force some bitfields to 0 643 spsr.res0_23_22 = 0; 644 spsr.ss = 0; 645 } 646 tc->setMiscReg(spsr_idx, spsr); 647 648 // Save preferred return address into ELR_ELx 649 Addr curr_pc = tc->pcState().pc(); 650 Addr ret_addr = curr_pc; 651 if (from64) 652 ret_addr += armPcElrOffset(); 653 else 654 ret_addr += spsr.t ? thumbPcElrOffset() : armPcElrOffset(); 655 tc->setMiscReg(elr_idx, ret_addr); 656 657 // Update process state 658 OperatingMode64 mode = 0; 659 mode.spX = 1; 660 mode.el = toEL; 661 mode.width = 0; 662 cpsr.mode = mode; 663 cpsr.daif = 0xf; 664 cpsr.il = 0; 665 cpsr.ss = 0; 666 tc->setMiscReg(MISCREG_CPSR, cpsr); 667 668 // Set PC to start of exception handler 669 Addr new_pc = purifyTaggedAddr(getVector64(tc), tc, toEL); 670 DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x " 671 "elr:%#x newVec: %#x\n", name(), cpsr, curr_pc, ret_addr, new_pc); 672 PCState pc(new_pc); 673 pc.aarch64(!cpsr.width); 674 pc.nextAArch64(!cpsr.width); 675 tc->pcState(pc); 676 677 // If we have a valid instruction then use it to annotate this fault with 678 // extra information. This is used to generate the correct fault syndrome 679 // information 680 if (inst) 681 static_cast<ArmStaticInst *>(inst.get())->annotateFault(this); 682 // Save exception syndrome 683 if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ)) 684 setSyndrome(tc, getSyndromeReg64()); 685} 686 687void 688Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst) 689{ 690 if (FullSystem) { 691 tc->getCpuPtr()->clearInterrupts(tc->threadId()); 692 tc->clearArchRegs(); 693 } 694 if (!ArmSystem::highestELIs64(tc)) { 695 ArmFault::invoke(tc, inst); 696 tc->setMiscReg(MISCREG_VMPIDR, 697 getMPIDR(dynamic_cast<ArmSystem*>(tc->getSystemPtr()), tc)); 698 699 // Unless we have SMC code to get us there, boot in HYP! 700 if (ArmSystem::haveVirtualization(tc) && 701 !ArmSystem::haveSecurity(tc)) { 702 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 703 cpsr.mode = MODE_HYP; 704 tc->setMiscReg(MISCREG_CPSR, cpsr); 705 } 706 } else { 707 // Advance the PC to the IMPLEMENTATION DEFINED reset value 708 PCState pc = ArmSystem::resetAddr64(tc); 709 pc.aarch64(true); 710 pc.nextAArch64(true); 711 tc->pcState(pc); 712 } 713} 714 715void 716UndefinedInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst) 717{ 718 if (FullSystem) { 719 ArmFault::invoke(tc, inst); 720 return; 721 } 722 723 // If the mnemonic isn't defined this has to be an unknown instruction. 724 assert(unknown || mnemonic != NULL); 725 if (disabled) { 726 panic("Attempted to execute disabled instruction " 727 "'%s' (inst 0x%08x)", mnemonic, machInst); 728 } else if (unknown) { 729 panic("Attempted to execute unknown instruction (inst 0x%08x)", 730 machInst); 731 } else { 732 panic("Attempted to execute unimplemented instruction " 733 "'%s' (inst 0x%08x)", mnemonic, machInst); 734 } 735} 736 737bool 738UndefinedInstruction::routeToHyp(ThreadContext *tc) const 739{ 740 bool toHyp; 741 742 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 743 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 744 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 745 746 // if in Hyp mode then stay in Hyp mode 747 toHyp = scr.ns && (cpsr.mode == MODE_HYP); 748 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 749 toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER); 750 return toHyp; 751} 752 753uint32_t 754UndefinedInstruction::iss() const 755{ 756 757 // If UndefinedInstruction is routed to hypervisor, iss field is 0. 758 if (hypRouted) { 759 return 0; 760 } 761 762 if (overrideEc == EC_INVALID) 763 return issRaw; 764 765 uint32_t new_iss = 0; 766 uint32_t op0, op1, op2, CRn, CRm, Rt, dir; 767 768 dir = bits(machInst, 21, 21); 769 op0 = bits(machInst, 20, 19); 770 op1 = bits(machInst, 18, 16); 771 CRn = bits(machInst, 15, 12); 772 CRm = bits(machInst, 11, 8); 773 op2 = bits(machInst, 7, 5); 774 Rt = bits(machInst, 4, 0); 775 776 new_iss = op0 << 20 | op2 << 17 | op1 << 14 | CRn << 10 | 777 Rt << 5 | CRm << 1 | dir; 778 779 return new_iss; 780} 781 782void 783SupervisorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst) 784{ 785 if (FullSystem) { 786 ArmFault::invoke(tc, inst); 787 return; 788 } 789 790 // As of now, there isn't a 32 bit thumb version of this instruction. 791 assert(!machInst.bigThumb); 792 uint32_t callNum; 793 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 794 OperatingMode mode = (OperatingMode)(uint8_t)cpsr.mode; 795 if (opModeIs64(mode)) 796 callNum = tc->readIntReg(INTREG_X8); 797 else 798 callNum = tc->readIntReg(INTREG_R7); 799 Fault fault; 800 tc->syscall(callNum, &fault); 801 802 // Advance the PC since that won't happen automatically. 803 PCState pc = tc->pcState(); 804 assert(inst); 805 inst->advancePC(pc); 806 tc->pcState(pc); 807} 808 809bool 810SupervisorCall::routeToHyp(ThreadContext *tc) const 811{ 812 bool toHyp; 813 814 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 815 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 816 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 817 818 // if in Hyp mode then stay in Hyp mode 819 toHyp = scr.ns && (cpsr.mode == MODE_HYP); 820 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 821 toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER); 822 return toHyp; 823} 824 825ExceptionClass 826SupervisorCall::ec(ThreadContext *tc) const 827{ 828 return (overrideEc != EC_INVALID) ? overrideEc : 829 (from64 ? EC_SVC_64 : vals.ec); 830} 831 832uint32_t 833SupervisorCall::iss() const 834{ 835 // Even if we have a 24 bit imm from an arm32 instruction then we only use 836 // the bottom 16 bits for the ISS value (it doesn't hurt for AArch64 SVC). 837 return issRaw & 0xFFFF; 838} 839 840uint32_t 841SecureMonitorCall::iss() const 842{ 843 if (from64) 844 return bits(machInst, 20, 5); 845 return 0; 846} 847 848ExceptionClass 849UndefinedInstruction::ec(ThreadContext *tc) const 850{ 851 // If UndefinedInstruction is routed to hypervisor, 852 // HSR.EC field is 0. 853 if (hypRouted) 854 return EC_UNKNOWN; 855 else 856 return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 857} 858 859 860HypervisorCall::HypervisorCall(ExtMachInst _machInst, uint32_t _imm) : 861 ArmFaultVals<HypervisorCall>(_machInst, _imm) 862{} 863 864ExceptionClass 865HypervisorCall::ec(ThreadContext *tc) const 866{ 867 return from64 ? EC_HVC_64 : vals.ec; 868} 869 870ExceptionClass 871HypervisorTrap::ec(ThreadContext *tc) const 872{ 873 return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 874} 875 876template<class T> 877FaultOffset 878ArmFaultVals<T>::offset(ThreadContext *tc) 879{ 880 bool isHypTrap = false; 881 882 // Normally we just use the exception vector from the table at the top if 883 // this file, however if this exception has caused a transition to hype 884 // mode, and its an exception type that would only do this if it has been 885 // trapped then we use the hyp trap vector instead of the normal vector 886 if (vals.hypTrappable) { 887 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 888 if (cpsr.mode == MODE_HYP) { 889 CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 890 isHypTrap = spsr.mode != MODE_HYP; 891 } 892 } 893 return isHypTrap ? 0x14 : vals.offset; 894} 895 896// void 897// SupervisorCall::setSyndrome64(ThreadContext *tc, MiscRegIndex esr_idx) 898// { 899// ESR esr = 0; 900// esr.ec = machInst.aarch64 ? SvcAArch64 : SvcAArch32; 901// esr.il = !machInst.thumb; 902// if (machInst.aarch64) 903// esr.imm16 = bits(machInst.instBits, 20, 5); 904// else if (machInst.thumb) 905// esr.imm16 = bits(machInst.instBits, 7, 0); 906// else 907// esr.imm16 = bits(machInst.instBits, 15, 0); 908// tc->setMiscReg(esr_idx, esr); 909// } 910 911void 912SecureMonitorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst) 913{ 914 if (FullSystem) { 915 ArmFault::invoke(tc, inst); 916 return; 917 } 918} 919 920ExceptionClass 921SecureMonitorCall::ec(ThreadContext *tc) const 922{ 923 return (from64 ? EC_SMC_64 : vals.ec); 924} 925 926ExceptionClass 927SupervisorTrap::ec(ThreadContext *tc) const 928{ 929 return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 930} 931 932ExceptionClass 933SecureMonitorTrap::ec(ThreadContext *tc) const 934{ 935 return (overrideEc != EC_INVALID) ? overrideEc : 936 (from64 ? EC_SMC_64 : vals.ec); 937} 938 939template<class T> 940void 941AbortFault<T>::invoke(ThreadContext *tc, const StaticInstPtr &inst) 942{ 943 if (tranMethod == ArmFault::UnknownTran) { 944 tranMethod = longDescFormatInUse(tc) ? ArmFault::LpaeTran 945 : ArmFault::VmsaTran; 946 947 if ((tranMethod == ArmFault::VmsaTran) && this->routeToMonitor(tc)) { 948 // See ARM ARM B3-1416 949 bool override_LPAE = false; 950 TTBCR ttbcr_s = tc->readMiscReg(MISCREG_TTBCR_S); 951 TTBCR M5_VAR_USED ttbcr_ns = tc->readMiscReg(MISCREG_TTBCR_NS); 952 if (ttbcr_s.eae) { 953 override_LPAE = true; 954 } else { 955 // Unimplemented code option, not seen in testing. May need 956 // extension according to the manual exceprt above. 957 DPRINTF(Faults, "Warning: Incomplete translation method " 958 "override detected.\n"); 959 } 960 if (override_LPAE) 961 tranMethod = ArmFault::LpaeTran; 962 } 963 } 964 965 if (source == ArmFault::AsynchronousExternalAbort) { 966 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0); 967 } 968 // Get effective fault source encoding 969 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 970 FSR fsr = getFsr(tc); 971 972 // source must be determined BEFORE invoking generic routines which will 973 // try to set hsr etc. and are based upon source! 974 ArmFaultVals<T>::invoke(tc, inst); 975 976 if (!this->to64) { // AArch32 977 if (cpsr.mode == MODE_HYP) { 978 tc->setMiscReg(T::HFarIndex, faultAddr); 979 } else if (stage2) { 980 tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf); 981 tc->setMiscReg(T::HFarIndex, OVAddr); 982 } else { 983 tc->setMiscReg(T::FsrIndex, fsr); 984 tc->setMiscReg(T::FarIndex, faultAddr); 985 } 986 DPRINTF(Faults, "Abort Fault source=%#x fsr=%#x faultAddr=%#x "\ 987 "tranMethod=%#x\n", source, fsr, faultAddr, tranMethod); 988 } else { // AArch64 989 // Set the FAR register. Nothing else to do if we are in AArch64 state 990 // because the syndrome register has already been set inside invoke64() 991 if (stage2) { 992 // stage 2 fault, set HPFAR_EL2 to the faulting IPA 993 // and FAR_EL2 to the Original VA 994 tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), OVAddr); 995 tc->setMiscReg(MISCREG_HPFAR_EL2, bits(faultAddr, 47, 12) << 4); 996 997 DPRINTF(Faults, "Abort Fault (Stage 2) VA: 0x%x IPA: 0x%x\n", 998 OVAddr, faultAddr); 999 } else { 1000 tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), faultAddr); 1001 } 1002 } 1003} 1004 1005template<class T> 1006FSR 1007AbortFault<T>::getFsr(ThreadContext *tc) 1008{ 1009 FSR fsr = 0; 1010 1011 if (((CPSR) tc->readMiscRegNoEffect(MISCREG_CPSR)).width) { 1012 // AArch32 1013 assert(tranMethod != ArmFault::UnknownTran); 1014 if (tranMethod == ArmFault::LpaeTran) { 1015 srcEncoded = ArmFault::longDescFaultSources[source]; 1016 fsr.status = srcEncoded; 1017 fsr.lpae = 1; 1018 } else { 1019 srcEncoded = ArmFault::shortDescFaultSources[source]; 1020 fsr.fsLow = bits(srcEncoded, 3, 0); 1021 fsr.fsHigh = bits(srcEncoded, 4); 1022 fsr.domain = static_cast<uint8_t>(domain); 1023 } 1024 fsr.wnr = (write ? 1 : 0); 1025 fsr.ext = 0; 1026 } else { 1027 // AArch64 1028 srcEncoded = ArmFault::aarch64FaultSources[source]; 1029 } 1030 if (srcEncoded == ArmFault::FaultSourceInvalid) { 1031 panic("Invalid fault source\n"); 1032 } 1033 return fsr; 1034} 1035 1036template<class T> 1037bool 1038AbortFault<T>::abortDisable(ThreadContext *tc) 1039{ 1040 if (ArmSystem::haveSecurity(tc)) { 1041 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1042 return (!scr.ns || scr.aw); 1043 } 1044 return true; 1045} 1046 1047template<class T> 1048void 1049AbortFault<T>::annotate(ArmFault::AnnotationIDs id, uint64_t val) 1050{ 1051 switch (id) 1052 { 1053 case ArmFault::S1PTW: 1054 s1ptw = val; 1055 break; 1056 case ArmFault::OVA: 1057 OVAddr = val; 1058 break; 1059 1060 // Just ignore unknown ID's 1061 default: 1062 break; 1063 } 1064} 1065 1066template<class T> 1067uint32_t 1068AbortFault<T>::iss() const 1069{ 1070 uint32_t val; 1071 1072 val = srcEncoded & 0x3F; 1073 val |= write << 6; 1074 val |= s1ptw << 7; 1075 return (val); 1076} 1077 1078template<class T> 1079bool 1080AbortFault<T>::isMMUFault() const 1081{ 1082 // NOTE: Not relying on LL information being aligned to lowest bits here 1083 return 1084 (source == ArmFault::AlignmentFault) || 1085 ((source >= ArmFault::TranslationLL) && 1086 (source < ArmFault::TranslationLL + 4)) || 1087 ((source >= ArmFault::AccessFlagLL) && 1088 (source < ArmFault::AccessFlagLL + 4)) || 1089 ((source >= ArmFault::DomainLL) && 1090 (source < ArmFault::DomainLL + 4)) || 1091 ((source >= ArmFault::PermissionLL) && 1092 (source < ArmFault::PermissionLL + 4)); 1093} 1094 1095ExceptionClass 1096PrefetchAbort::ec(ThreadContext *tc) const 1097{ 1098 if (to64) { 1099 // AArch64 1100 if (toEL == fromEL) 1101 return EC_PREFETCH_ABORT_CURR_EL; 1102 else 1103 return EC_PREFETCH_ABORT_LOWER_EL; 1104 } else { 1105 // AArch32 1106 // Abort faults have different EC codes depending on whether 1107 // the fault originated within HYP mode, or not. So override 1108 // the method and add the extra adjustment of the EC value. 1109 1110 ExceptionClass ec = ArmFaultVals<PrefetchAbort>::vals.ec; 1111 1112 CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 1113 if (spsr.mode == MODE_HYP) { 1114 ec = ((ExceptionClass) (((uint32_t) ec) + 1)); 1115 } 1116 return ec; 1117 } 1118} 1119 1120bool 1121PrefetchAbort::routeToMonitor(ThreadContext *tc) const 1122{ 1123 SCR scr = 0; 1124 if (from64) 1125 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1126 else 1127 scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1128 1129 return scr.ea && !isMMUFault(); 1130} 1131 1132bool 1133PrefetchAbort::routeToHyp(ThreadContext *tc) const 1134{ 1135 bool toHyp; 1136 1137 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1138 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1139 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 1140 HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR); 1141 1142 // if in Hyp mode then stay in Hyp mode 1143 toHyp = scr.ns && (cpsr.mode == MODE_HYP); 1144 // otherwise, check whether to take to Hyp mode through Hyp Trap vector 1145 toHyp |= (stage2 || 1146 ( (source == DebugEvent) && hdcr.tde && (cpsr.mode != MODE_HYP)) || 1147 ( (source == SynchronousExternalAbort) && hcr.tge && (cpsr.mode == MODE_USER)) 1148 ) && !inSecureState(tc); 1149 return toHyp; 1150} 1151 1152ExceptionClass 1153DataAbort::ec(ThreadContext *tc) const 1154{ 1155 if (to64) { 1156 // AArch64 1157 if (source == ArmFault::AsynchronousExternalAbort) { 1158 panic("Asynchronous External Abort should be handled with " 1159 "SystemErrors (SErrors)!"); 1160 } 1161 if (toEL == fromEL) 1162 return EC_DATA_ABORT_CURR_EL; 1163 else 1164 return EC_DATA_ABORT_LOWER_EL; 1165 } else { 1166 // AArch32 1167 // Abort faults have different EC codes depending on whether 1168 // the fault originated within HYP mode, or not. So override 1169 // the method and add the extra adjustment of the EC value. 1170 1171 ExceptionClass ec = ArmFaultVals<DataAbort>::vals.ec; 1172 1173 CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 1174 if (spsr.mode == MODE_HYP) { 1175 ec = ((ExceptionClass) (((uint32_t) ec) + 1)); 1176 } 1177 return ec; 1178 } 1179} 1180 1181bool 1182DataAbort::routeToMonitor(ThreadContext *tc) const 1183{ 1184 SCR scr = 0; 1185 if (from64) 1186 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1187 else 1188 scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1189 1190 return scr.ea && !isMMUFault(); 1191} 1192 1193bool 1194DataAbort::routeToHyp(ThreadContext *tc) const 1195{ 1196 bool toHyp; 1197 1198 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1199 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1200 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 1201 HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR); 1202 1203 // if in Hyp mode then stay in Hyp mode 1204 toHyp = scr.ns && (cpsr.mode == MODE_HYP); 1205 // otherwise, check whether to take to Hyp mode through Hyp Trap vector 1206 toHyp |= (stage2 || 1207 ( (cpsr.mode != MODE_HYP) && ( ((source == AsynchronousExternalAbort) && hcr.amo) || 1208 ((source == DebugEvent) && hdcr.tde) ) 1209 ) || 1210 ( (cpsr.mode == MODE_USER) && hcr.tge && 1211 ((source == AlignmentFault) || 1212 (source == SynchronousExternalAbort)) 1213 ) 1214 ) && !inSecureState(tc); 1215 return toHyp; 1216} 1217 1218uint32_t 1219DataAbort::iss() const 1220{ 1221 uint32_t val; 1222 1223 // Add on the data abort specific fields to the generic abort ISS value 1224 val = AbortFault<DataAbort>::iss(); 1225 // ISS is valid if not caused by a stage 1 page table walk, and when taken 1226 // to AArch64 only when directed to EL2 1227 if (!s1ptw && (!to64 || toEL == EL2)) { 1228 val |= isv << 24; 1229 if (isv) { 1230 val |= sas << 22; 1231 val |= sse << 21; 1232 val |= srt << 16; 1233 // AArch64 only. These assignments are safe on AArch32 as well 1234 // because these vars are initialized to false 1235 val |= sf << 15; 1236 val |= ar << 14; 1237 } 1238 } 1239 return (val); 1240} 1241 1242void 1243DataAbort::annotate(AnnotationIDs id, uint64_t val) 1244{ 1245 AbortFault<DataAbort>::annotate(id, val); 1246 switch (id) 1247 { 1248 case SAS: 1249 isv = true; 1250 sas = val; 1251 break; 1252 case SSE: 1253 isv = true; 1254 sse = val; 1255 break; 1256 case SRT: 1257 isv = true; 1258 srt = val; 1259 break; 1260 case SF: 1261 isv = true; 1262 sf = val; 1263 break; 1264 case AR: 1265 isv = true; 1266 ar = val; 1267 break; 1268 // Just ignore unknown ID's 1269 default: 1270 break; 1271 } 1272} 1273 1274void 1275VirtualDataAbort::invoke(ThreadContext *tc, const StaticInstPtr &inst) 1276{ 1277 AbortFault<VirtualDataAbort>::invoke(tc, inst); 1278 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1279 hcr.va = 0; 1280 tc->setMiscRegNoEffect(MISCREG_HCR, hcr); 1281} 1282 1283bool 1284Interrupt::routeToMonitor(ThreadContext *tc) const 1285{ 1286 assert(ArmSystem::haveSecurity(tc)); 1287 SCR scr = 0; 1288 if (from64) 1289 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1290 else 1291 scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1292 return scr.irq; 1293} 1294 1295bool 1296Interrupt::routeToHyp(ThreadContext *tc) const 1297{ 1298 bool toHyp; 1299 1300 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1301 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1302 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 1303 // Determine whether IRQs are routed to Hyp mode. 1304 toHyp = (!scr.irq && hcr.imo && !inSecureState(tc)) || 1305 (cpsr.mode == MODE_HYP); 1306 return toHyp; 1307} 1308 1309bool 1310Interrupt::abortDisable(ThreadContext *tc) 1311{ 1312 if (ArmSystem::haveSecurity(tc)) { 1313 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1314 return (!scr.ns || scr.aw); 1315 } 1316 return true; 1317} 1318 1319VirtualInterrupt::VirtualInterrupt() 1320{} 1321 1322bool 1323FastInterrupt::routeToMonitor(ThreadContext *tc) const 1324{ 1325 assert(ArmSystem::haveSecurity(tc)); 1326 SCR scr = 0; 1327 if (from64) 1328 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1329 else 1330 scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1331 return scr.fiq; 1332} 1333 1334bool 1335FastInterrupt::routeToHyp(ThreadContext *tc) const 1336{ 1337 bool toHyp; 1338 1339 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1340 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1341 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 1342 // Determine whether IRQs are routed to Hyp mode. 1343 toHyp = (!scr.fiq && hcr.fmo && !inSecureState(tc)) || 1344 (cpsr.mode == MODE_HYP); 1345 return toHyp; 1346} 1347 1348bool 1349FastInterrupt::abortDisable(ThreadContext *tc) 1350{ 1351 if (ArmSystem::haveSecurity(tc)) { 1352 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1353 return (!scr.ns || scr.aw); 1354 } 1355 return true; 1356} 1357 1358bool 1359FastInterrupt::fiqDisable(ThreadContext *tc) 1360{ 1361 if (ArmSystem::haveVirtualization(tc)) { 1362 return true; 1363 } else if (ArmSystem::haveSecurity(tc)) { 1364 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1365 return (!scr.ns || scr.fw); 1366 } 1367 return true; 1368} 1369 1370VirtualFastInterrupt::VirtualFastInterrupt() 1371{} 1372 1373void 1374PCAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 1375{ 1376 ArmFaultVals<PCAlignmentFault>::invoke(tc, inst); 1377 assert(from64); 1378 // Set the FAR 1379 tc->setMiscReg(getFaultAddrReg64(), faultPC); 1380} 1381 1382SPAlignmentFault::SPAlignmentFault() 1383{} 1384 1385SystemError::SystemError() 1386{} 1387 1388void 1389SystemError::invoke(ThreadContext *tc, const StaticInstPtr &inst) 1390{ 1391 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0); 1392 ArmFault::invoke(tc, inst); 1393} 1394 1395bool 1396SystemError::routeToMonitor(ThreadContext *tc) const 1397{ 1398 assert(ArmSystem::haveSecurity(tc)); 1399 assert(from64); 1400 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1401 return scr.ea; 1402} 1403 1404bool 1405SystemError::routeToHyp(ThreadContext *tc) const 1406{ 1407 bool toHyp; 1408 assert(from64); 1409 1410 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1411 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1412 1413 toHyp = (!scr.ea && hcr.amo && !inSecureState(tc)) || 1414 (!scr.ea && !scr.rw && !hcr.amo && !inSecureState(tc)); 1415 return toHyp; 1416} 1417 1418 1419SoftwareBreakpoint::SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss) 1420 : ArmFaultVals<SoftwareBreakpoint>(_mach_inst, _iss) 1421{} 1422 1423bool 1424SoftwareBreakpoint::routeToHyp(ThreadContext *tc) const 1425{ 1426 assert(from64); 1427 1428 const bool have_el2 = ArmSystem::haveVirtualization(tc); 1429 1430 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); 1431 const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2); 1432 1433 return have_el2 && !inSecureState(tc) && fromEL <= EL1 && 1434 (hcr.tge || mdcr.tde); 1435} 1436 1437void 1438ArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) { 1439 DPRINTF(Faults, "Invoking ArmSev Fault\n"); 1440 if (!FullSystem) 1441 return; 1442 1443 // Set sev_mailbox to 1, clear the pending interrupt from remote 1444 // SEV execution and let pipeline continue as pcState is still 1445 // valid. 1446 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 1447 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_SEV, 0); 1448} 1449 1450// Instantiate all the templates to make the linker happy 1451template class ArmFaultVals<Reset>; 1452template class ArmFaultVals<UndefinedInstruction>; 1453template class ArmFaultVals<SupervisorCall>; 1454template class ArmFaultVals<SecureMonitorCall>; 1455template class ArmFaultVals<HypervisorCall>; 1456template class ArmFaultVals<PrefetchAbort>; 1457template class ArmFaultVals<DataAbort>; 1458template class ArmFaultVals<VirtualDataAbort>; 1459template class ArmFaultVals<HypervisorTrap>; 1460template class ArmFaultVals<Interrupt>; 1461template class ArmFaultVals<VirtualInterrupt>; 1462template class ArmFaultVals<FastInterrupt>; 1463template class ArmFaultVals<VirtualFastInterrupt>; 1464template class ArmFaultVals<SupervisorTrap>; 1465template class ArmFaultVals<SecureMonitorTrap>; 1466template class ArmFaultVals<PCAlignmentFault>; 1467template class ArmFaultVals<SPAlignmentFault>; 1468template class ArmFaultVals<SystemError>; 1469template class ArmFaultVals<SoftwareBreakpoint>; 1470template class ArmFaultVals<ArmSev>; 1471template class AbortFault<PrefetchAbort>; 1472template class AbortFault<DataAbort>; 1473template class AbortFault<VirtualDataAbort>; 1474 1475 1476IllegalInstSetStateFault::IllegalInstSetStateFault() 1477{} 1478 1479 1480} // namespace ArmISA 1481