faults.cc revision 7678:f19b6a3a8cec
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * Copyright (c) 2007-2008 The Florida State University 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Ali Saidi 42 * Gabe Black 43 */ 44 45#include "arch/arm/faults.hh" 46#include "cpu/thread_context.hh" 47#include "cpu/base.hh" 48#include "base/trace.hh" 49 50namespace ArmISA 51{ 52 53template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals = 54 {"reset", 0x00, MODE_SVC, 0, 0, true, true}; 55 56template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals = 57 {"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ; 58 59template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals = 60 {"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false}; 61 62template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals = 63 {"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false}; 64 65template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals = 66 {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false}; 67 68template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals = 69 {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false}; 70 71template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals = 72 {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true}; 73 74template<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals = 75 {"Pipe Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values 76 77Addr 78ArmFault::getVector(ThreadContext *tc) 79{ 80 // ARM ARM B1-3 81 82 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 83 84 // panic if SCTLR.VE because I have no idea what to do with vectored 85 // interrupts 86 assert(!sctlr.ve); 87 88 if (!sctlr.v) 89 return offset(); 90 return offset() + HighVecs; 91 92} 93 94#if FULL_SYSTEM 95 96void 97ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst) 98{ 99 // ARM ARM B1.6.3 100 FaultBase::invoke(tc); 101 countStat()++; 102 103 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 104 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 105 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) | 106 tc->readIntReg(INTREG_CONDCODES); 107 108 109 cpsr.mode = nextMode(); 110 cpsr.it1 = cpsr.it2 = 0; 111 cpsr.j = 0; 112 113 cpsr.t = sctlr.te; 114 cpsr.a = cpsr.a | abortDisable(); 115 cpsr.f = cpsr.f | fiqDisable(); 116 cpsr.i = 1; 117 cpsr.e = sctlr.ee; 118 tc->setMiscReg(MISCREG_CPSR, cpsr); 119 tc->setIntReg(INTREG_LR, tc->readPC() + 120 (saved_cpsr.t ? thumbPcOffset() : armPcOffset())); 121 122 switch (nextMode()) { 123 case MODE_FIQ: 124 tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr); 125 break; 126 case MODE_IRQ: 127 tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr); 128 break; 129 case MODE_SVC: 130 tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr); 131 break; 132 case MODE_UNDEFINED: 133 tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr); 134 break; 135 case MODE_ABORT: 136 tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr); 137 break; 138 default: 139 panic("unknown Mode\n"); 140 } 141 142 Addr pc M5_VAR_USED = tc->readPC(); 143 Addr newPc = getVector(tc) | (sctlr.te ? (ULL(1) << PcTBitShift) : 0); 144 DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n", 145 name(), cpsr, pc, tc->readIntReg(INTREG_LR), newPc); 146 tc->setPC(newPc); 147 tc->setNextPC(newPc + cpsr.t ? 2 : 4 ); 148 tc->setMicroPC(0); 149 tc->setNextMicroPC(1); 150} 151 152void 153Reset::invoke(ThreadContext *tc, StaticInstPtr inst) 154{ 155 tc->getCpuPtr()->clearInterrupts(); 156 tc->clearArchRegs(); 157 ArmFault::invoke(tc); 158} 159 160#else 161 162void 163UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst) 164{ 165 // If the mnemonic isn't defined this has to be an unknown instruction. 166 assert(unknown || mnemonic != NULL); 167 if (disabled) { 168 panic("Attempted to execute disabled instruction " 169 "'%s' (inst 0x%08x)", mnemonic, machInst); 170 } else if (unknown) { 171 panic("Attempted to execute unknown instruction (inst 0x%08x)", 172 machInst); 173 } else { 174 panic("Attempted to execute unimplemented instruction " 175 "'%s' (inst 0x%08x)", mnemonic, machInst); 176 } 177} 178 179void 180SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst) 181{ 182 // As of now, there isn't a 32 bit thumb version of this instruction. 183 assert(!machInst.bigThumb); 184 uint32_t callNum; 185 if (machInst.thumb) { 186 callNum = bits(machInst, 7, 0); 187 } else { 188 callNum = bits(machInst, 23, 0); 189 } 190 if (callNum == 0) { 191 callNum = tc->readIntReg(INTREG_R7); 192 } 193 tc->syscall(callNum); 194 195 // Advance the PC since that won't happen automatically. 196 tc->setPC(tc->readNextPC()); 197 tc->setNextPC(tc->readNextNPC()); 198 tc->setMicroPC(0); 199 tc->setNextMicroPC(1); 200} 201 202#endif // FULL_SYSTEM 203 204template<class T> 205void 206AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst) 207{ 208 ArmFaultVals<T>::invoke(tc); 209 FSR fsr = 0; 210 fsr.fsLow = bits(status, 3, 0); 211 fsr.fsHigh = bits(status, 4); 212 fsr.domain = domain; 213 fsr.wnr = (write ? 1 : 0); 214 fsr.ext = 0; 215 tc->setMiscReg(T::FsrIndex, fsr); 216 tc->setMiscReg(T::FarIndex, faultAddr); 217} 218 219void 220FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) { 221 DPRINTF(Faults, "Invoking FlushPipe Fault\n"); 222 223 // Set the PC to the next instruction of the faulting instruction. 224 // Net effect is simply squashing all instructions behind and 225 // start refetching from the next instruction. 226 tc->setPC(tc->readNextPC()); 227 tc->setNextPC(tc->readNextNPC()); 228 tc->setMicroPC(0); 229 tc->setNextMicroPC(1); 230} 231 232template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc, 233 StaticInstPtr inst); 234template void AbortFault<DataAbort>::invoke(ThreadContext *tc, 235 StaticInstPtr inst); 236 237// return via SUBS pc, lr, xxx; rfe, movs, ldm 238 239} // namespace ArmISA 240