faults.cc revision 8302:9f23d01421de 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 *          Gabe Black
43 */
44
45#include "arch/arm/faults.hh"
46#include "base/trace.hh"
47#include "cpu/base.hh"
48#include "cpu/thread_context.hh"
49#include "debug/Faults.hh"
50
51namespace ArmISA
52{
53
54template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals =
55    {"reset", 0x00, MODE_SVC, 0, 0, true, true};
56
57template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals =
58    {"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ;
59
60template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals =
61    {"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false};
62
63template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals =
64    {"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false};
65
66template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals =
67    {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false};
68
69template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals =
70    {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false};
71
72template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals =
73    {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true};
74
75template<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals =
76    {"Pipe Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values
77
78template<> ArmFault::FaultVals ArmFaultVals<ReExec>::vals =
79    {"ReExec Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values
80
81Addr
82ArmFault::getVector(ThreadContext *tc)
83{
84    // ARM ARM B1-3
85
86    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
87
88    // panic if SCTLR.VE because I have no idea what to do with vectored
89    // interrupts
90    assert(!sctlr.ve);
91
92    if (!sctlr.v)
93        return offset();
94    return offset() + HighVecs;
95
96}
97
98#if FULL_SYSTEM
99
100void
101ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
102{
103    // ARM ARM B1.6.3
104    FaultBase::invoke(tc);
105    countStat()++;
106
107    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
108    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
109    CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) |
110                      tc->readIntReg(INTREG_CONDCODES_F) |
111                      tc->readIntReg(INTREG_CONDCODES_GE);
112    Addr curPc M5_VAR_USED = tc->pcState().pc();
113    ITSTATE it = tc->pcState().itstate();
114    saved_cpsr.it2 = it.top6;
115    saved_cpsr.it1 = it.bottom2;
116
117    cpsr.mode = nextMode();
118    cpsr.it1 = cpsr.it2 = 0;
119    cpsr.j = 0;
120
121    cpsr.t = sctlr.te;
122    cpsr.a = cpsr.a | abortDisable();
123    cpsr.f = cpsr.f | fiqDisable();
124    cpsr.i = 1;
125    cpsr.e = sctlr.ee;
126    tc->setMiscReg(MISCREG_CPSR, cpsr);
127    tc->setIntReg(INTREG_LR, curPc +
128            (saved_cpsr.t ? thumbPcOffset() : armPcOffset()));
129
130    switch (nextMode()) {
131      case MODE_FIQ:
132        tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
133        break;
134      case MODE_IRQ:
135        tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
136        break;
137      case MODE_SVC:
138        tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
139        break;
140      case MODE_UNDEFINED:
141        tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
142        break;
143      case MODE_ABORT:
144        tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
145        break;
146      default:
147        panic("unknown Mode\n");
148    }
149
150    Addr newPc = getVector(tc);
151    DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
152            name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc);
153    PCState pc(newPc);
154    pc.thumb(cpsr.t);
155    pc.nextThumb(pc.thumb());
156    pc.jazelle(cpsr.j);
157    pc.nextJazelle(pc.jazelle());
158    tc->pcState(pc);
159}
160
161void
162Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
163{
164    tc->getCpuPtr()->clearInterrupts();
165    tc->clearArchRegs();
166    ArmFault::invoke(tc, inst);
167}
168
169#else
170
171void
172UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
173{
174    // If the mnemonic isn't defined this has to be an unknown instruction.
175    assert(unknown || mnemonic != NULL);
176    if (disabled) {
177        panic("Attempted to execute disabled instruction "
178                "'%s' (inst 0x%08x)", mnemonic, machInst);
179    } else if (unknown) {
180        panic("Attempted to execute unknown instruction (inst 0x%08x)",
181              machInst);
182    } else {
183        panic("Attempted to execute unimplemented instruction "
184                "'%s' (inst 0x%08x)", mnemonic, machInst);
185    }
186}
187
188void
189SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
190{
191    // As of now, there isn't a 32 bit thumb version of this instruction.
192    assert(!machInst.bigThumb);
193    uint32_t callNum;
194    callNum = tc->readIntReg(INTREG_R7);
195    tc->syscall(callNum);
196
197    // Advance the PC since that won't happen automatically.
198    PCState pc = tc->pcState();
199    assert(inst);
200    inst->advancePC(pc);
201    tc->pcState(pc);
202}
203
204#endif // FULL_SYSTEM
205
206template<class T>
207void
208AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
209{
210    ArmFaultVals<T>::invoke(tc, inst);
211    FSR fsr = 0;
212    fsr.fsLow = bits(status, 3, 0);
213    fsr.fsHigh = bits(status, 4);
214    fsr.domain = domain;
215    fsr.wnr = (write ? 1 : 0);
216    fsr.ext = 0;
217    tc->setMiscReg(T::FsrIndex, fsr);
218    tc->setMiscReg(T::FarIndex, faultAddr);
219}
220
221void
222FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) {
223    DPRINTF(Faults, "Invoking FlushPipe Fault\n");
224
225    // Set the PC to the next instruction of the faulting instruction.
226    // Net effect is simply squashing all instructions behind and
227    // start refetching from the next instruction.
228    PCState pc = tc->pcState();
229    assert(inst);
230    inst->advancePC(pc);
231    tc->pcState(pc);
232}
233
234void
235ReExec::invoke(ThreadContext *tc, StaticInstPtr inst) {
236    DPRINTF(Faults, "Invoking ReExec Fault\n");
237
238    // Set the PC to then the faulting instruction.
239    // Net effect is simply squashing all instructions including this
240    // instruction and refetching/rexecuting current instruction
241    PCState pc = tc->pcState();
242    tc->pcState(pc);
243}
244
245template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc,
246                                                StaticInstPtr inst);
247template void AbortFault<DataAbort>::invoke(ThreadContext *tc,
248                                            StaticInstPtr inst);
249
250// return via SUBS pc, lr, xxx; rfe, movs, ldm
251
252} // namespace ArmISA
253