faults.cc revision 12509:aa16dce23e98 
1/*
2 * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 *          Gabe Black
43 *          Giacomo Gabrielli
44 *          Thomas Grocutt
45 */
46
47#include "arch/arm/faults.hh"
48
49#include "arch/arm/insts/static_inst.hh"
50#include "arch/arm/system.hh"
51#include "arch/arm/utility.hh"
52#include "base/compiler.hh"
53#include "base/trace.hh"
54#include "cpu/base.hh"
55#include "cpu/thread_context.hh"
56#include "debug/Faults.hh"
57#include "sim/full_system.hh"
58
59namespace ArmISA
60{
61
62uint8_t ArmFault::shortDescFaultSources[] = {
63    0x01,  // AlignmentFault
64    0x04,  // InstructionCacheMaintenance
65    0xff,  // SynchExtAbtOnTranslTableWalkL0 (INVALID)
66    0x0c,  // SynchExtAbtOnTranslTableWalkL1
67    0x0e,  // SynchExtAbtOnTranslTableWalkL2
68    0xff,  // SynchExtAbtOnTranslTableWalkL3 (INVALID)
69    0xff,  // SynchPtyErrOnTranslTableWalkL0 (INVALID)
70    0x1c,  // SynchPtyErrOnTranslTableWalkL1
71    0x1e,  // SynchPtyErrOnTranslTableWalkL2
72    0xff,  // SynchPtyErrOnTranslTableWalkL3 (INVALID)
73    0xff,  // TranslationL0 (INVALID)
74    0x05,  // TranslationL1
75    0x07,  // TranslationL2
76    0xff,  // TranslationL3 (INVALID)
77    0xff,  // AccessFlagL0 (INVALID)
78    0x03,  // AccessFlagL1
79    0x06,  // AccessFlagL2
80    0xff,  // AccessFlagL3 (INVALID)
81    0xff,  // DomainL0 (INVALID)
82    0x09,  // DomainL1
83    0x0b,  // DomainL2
84    0xff,  // DomainL3 (INVALID)
85    0xff,  // PermissionL0 (INVALID)
86    0x0d,  // PermissionL1
87    0x0f,  // PermissionL2
88    0xff,  // PermissionL3 (INVALID)
89    0x02,  // DebugEvent
90    0x08,  // SynchronousExternalAbort
91    0x10,  // TLBConflictAbort
92    0x19,  // SynchPtyErrOnMemoryAccess
93    0x16,  // AsynchronousExternalAbort
94    0x18,  // AsynchPtyErrOnMemoryAccess
95    0xff,  // AddressSizeL0 (INVALID)
96    0xff,  // AddressSizeL1 (INVALID)
97    0xff,  // AddressSizeL2 (INVALID)
98    0xff,  // AddressSizeL3 (INVALID)
99    0x40,  // PrefetchTLBMiss
100    0x80   // PrefetchUncacheable
101};
102
103static_assert(sizeof(ArmFault::shortDescFaultSources) ==
104              ArmFault::NumFaultSources,
105              "Invalid size of ArmFault::shortDescFaultSources[]");
106
107uint8_t ArmFault::longDescFaultSources[] = {
108    0x21,  // AlignmentFault
109    0xff,  // InstructionCacheMaintenance (INVALID)
110    0xff,  // SynchExtAbtOnTranslTableWalkL0 (INVALID)
111    0x15,  // SynchExtAbtOnTranslTableWalkL1
112    0x16,  // SynchExtAbtOnTranslTableWalkL2
113    0x17,  // SynchExtAbtOnTranslTableWalkL3
114    0xff,  // SynchPtyErrOnTranslTableWalkL0 (INVALID)
115    0x1d,  // SynchPtyErrOnTranslTableWalkL1
116    0x1e,  // SynchPtyErrOnTranslTableWalkL2
117    0x1f,  // SynchPtyErrOnTranslTableWalkL3
118    0xff,  // TranslationL0 (INVALID)
119    0x05,  // TranslationL1
120    0x06,  // TranslationL2
121    0x07,  // TranslationL3
122    0xff,  // AccessFlagL0 (INVALID)
123    0x09,  // AccessFlagL1
124    0x0a,  // AccessFlagL2
125    0x0b,  // AccessFlagL3
126    0xff,  // DomainL0 (INVALID)
127    0x3d,  // DomainL1
128    0x3e,  // DomainL2
129    0xff,  // DomainL3 (RESERVED)
130    0xff,  // PermissionL0 (INVALID)
131    0x0d,  // PermissionL1
132    0x0e,  // PermissionL2
133    0x0f,  // PermissionL3
134    0x22,  // DebugEvent
135    0x10,  // SynchronousExternalAbort
136    0x30,  // TLBConflictAbort
137    0x18,  // SynchPtyErrOnMemoryAccess
138    0x11,  // AsynchronousExternalAbort
139    0x19,  // AsynchPtyErrOnMemoryAccess
140    0xff,  // AddressSizeL0 (INVALID)
141    0xff,  // AddressSizeL1 (INVALID)
142    0xff,  // AddressSizeL2 (INVALID)
143    0xff,  // AddressSizeL3 (INVALID)
144    0x40,  // PrefetchTLBMiss
145    0x80   // PrefetchUncacheable
146};
147
148static_assert(sizeof(ArmFault::longDescFaultSources) ==
149              ArmFault::NumFaultSources,
150              "Invalid size of ArmFault::longDescFaultSources[]");
151
152uint8_t ArmFault::aarch64FaultSources[] = {
153    0x21,  // AlignmentFault
154    0xff,  // InstructionCacheMaintenance (INVALID)
155    0x14,  // SynchExtAbtOnTranslTableWalkL0
156    0x15,  // SynchExtAbtOnTranslTableWalkL1
157    0x16,  // SynchExtAbtOnTranslTableWalkL2
158    0x17,  // SynchExtAbtOnTranslTableWalkL3
159    0x1c,  // SynchPtyErrOnTranslTableWalkL0
160    0x1d,  // SynchPtyErrOnTranslTableWalkL1
161    0x1e,  // SynchPtyErrOnTranslTableWalkL2
162    0x1f,  // SynchPtyErrOnTranslTableWalkL3
163    0x04,  // TranslationL0
164    0x05,  // TranslationL1
165    0x06,  // TranslationL2
166    0x07,  // TranslationL3
167    0x08,  // AccessFlagL0
168    0x09,  // AccessFlagL1
169    0x0a,  // AccessFlagL2
170    0x0b,  // AccessFlagL3
171    // @todo: Section & Page Domain Fault in AArch64?
172    0xff,  // DomainL0 (INVALID)
173    0xff,  // DomainL1 (INVALID)
174    0xff,  // DomainL2 (INVALID)
175    0xff,  // DomainL3 (INVALID)
176    0x0c,  // PermissionL0
177    0x0d,  // PermissionL1
178    0x0e,  // PermissionL2
179    0x0f,  // PermissionL3
180    0xff,  // DebugEvent (INVALID)
181    0x10,  // SynchronousExternalAbort
182    0x30,  // TLBConflictAbort
183    0x18,  // SynchPtyErrOnMemoryAccess
184    0xff,  // AsynchronousExternalAbort (INVALID)
185    0xff,  // AsynchPtyErrOnMemoryAccess (INVALID)
186    0x00,  // AddressSizeL0
187    0x01,  // AddressSizeL1
188    0x02,  // AddressSizeL2
189    0x03,  // AddressSizeL3
190    0x40,  // PrefetchTLBMiss
191    0x80   // PrefetchUncacheable
192};
193
194static_assert(sizeof(ArmFault::aarch64FaultSources) ==
195              ArmFault::NumFaultSources,
196              "Invalid size of ArmFault::aarch64FaultSources[]");
197
198// Fields: name, offset, cur{ELT,ELH}Offset, lowerEL{64,32}Offset, next mode,
199//         {ARM, Thumb, ARM_ELR, Thumb_ELR} PC offset, hyp trap,
200//         {A, F} disable, class, stat
201template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals = {
202    // Some dummy values (the reset vector has an IMPLEMENTATION DEFINED
203    // location in AArch64)
204    "Reset",                 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
205    0, 0, 0, 0, false, true,  true,  EC_UNKNOWN, FaultStat()
206};
207template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals = {
208    "Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED,
209    4, 2, 0, 0, true,  false, false, EC_UNKNOWN, FaultStat()
210};
211template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals = {
212    "Supervisor Call",       0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
213    4, 2, 4, 2, true,  false, false, EC_SVC_TO_HYP, FaultStat()
214};
215template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals = {
216    "Secure Monitor Call",   0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON,
217    4, 4, 4, 4, false, true,  true,  EC_SMC_TO_HYP, FaultStat()
218};
219template<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals = {
220    "Hypervisor Call",       0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
221    4, 4, 4, 4, true,  false, false, EC_HVC, FaultStat()
222};
223template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals = {
224    "Prefetch Abort",        0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
225    4, 4, 0, 0, true,  true,  false, EC_PREFETCH_ABORT_TO_HYP, FaultStat()
226};
227template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals = {
228    "Data Abort",            0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
229    8, 8, 0, 0, true,  true,  false, EC_DATA_ABORT_TO_HYP, FaultStat()
230};
231template<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals = {
232    "Virtual Data Abort",    0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
233    8, 8, 0, 0, true,  true,  false, EC_INVALID, FaultStat()
234};
235template<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals = {
236    // @todo: double check these values
237    "Hypervisor Trap",       0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
238    0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat()
239};
240template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals = {
241    "IRQ",                   0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ,
242    4, 4, 0, 0, false, true,  false, EC_UNKNOWN, FaultStat()
243};
244template<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals = {
245    "Virtual IRQ",           0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ,
246    4, 4, 0, 0, false, true,  false, EC_INVALID, FaultStat()
247};
248template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals = {
249    "FIQ",                   0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ,
250    4, 4, 0, 0, false, true,  true,  EC_UNKNOWN, FaultStat()
251};
252template<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals = {
253    "Virtual FIQ",           0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ,
254    4, 4, 0, 0, false, true,  true,  EC_INVALID, FaultStat()
255};
256template<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals = {
257    // Some dummy values (SupervisorTrap is AArch64-only)
258    "Supervisor Trap",   0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
259    0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat()
260};
261template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals = {
262    // Some dummy values (SecureMonitorTrap is AArch64-only)
263    "Secure Monitor Trap",   0x014, 0x000, 0x200, 0x400, 0x600, MODE_MON,
264    0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat()
265};
266template<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals = {
267    // Some dummy values (PCAlignmentFault is AArch64-only)
268    "PC Alignment Fault",   0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
269    0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT, FaultStat()
270};
271template<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals = {
272    // Some dummy values (SPAlignmentFault is AArch64-only)
273    "SP Alignment Fault",   0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
274    0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT, FaultStat()
275};
276template<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals = {
277    // Some dummy values (SError is AArch64-only)
278    "SError",                0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC,
279    0, 0, 0, 0, false, true,  true,  EC_SERROR, FaultStat()
280};
281template<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals = {
282    // Some dummy values (SoftwareBreakpoint is AArch64-only)
283    "Software Breakpoint",   0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
284    0, 0, 0, 0, true, false, false,  EC_SOFTWARE_BREAKPOINT, FaultStat()
285};
286template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals = {
287    // Some dummy values
288    "ArmSev Flush",          0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
289    0, 0, 0, 0, false, true,  true,  EC_UNKNOWN, FaultStat()
290};
291template<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals = {
292    // Some dummy values (SPAlignmentFault is AArch64-only)
293    "Illegal Inst Set State Fault",   0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
294    0, 0, 0, 0, true, false, false, EC_ILLEGAL_INST, FaultStat()
295};
296
297Addr
298ArmFault::getVector(ThreadContext *tc)
299{
300    Addr base;
301
302    // ARM ARM issue C B1.8.1
303    bool haveSecurity = ArmSystem::haveSecurity(tc);
304
305    // panic if SCTLR.VE because I have no idea what to do with vectored
306    // interrupts
307    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
308    assert(!sctlr.ve);
309    // Check for invalid modes
310    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
311    assert(haveSecurity                      || cpsr.mode != MODE_MON);
312    assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
313
314    switch (cpsr.mode)
315    {
316      case MODE_MON:
317        base = tc->readMiscReg(MISCREG_MVBAR);
318        break;
319      case MODE_HYP:
320        base = tc->readMiscReg(MISCREG_HVBAR);
321        break;
322      default:
323        if (sctlr.v) {
324            base = HighVecs;
325        } else {
326            base = haveSecurity ? tc->readMiscReg(MISCREG_VBAR) : 0;
327        }
328        break;
329    }
330    return base + offset(tc);
331}
332
333Addr
334ArmFault::getVector64(ThreadContext *tc)
335{
336    Addr vbar;
337    switch (toEL) {
338      case EL3:
339        assert(ArmSystem::haveSecurity(tc));
340        vbar = tc->readMiscReg(MISCREG_VBAR_EL3);
341        break;
342      case EL2:
343        assert(ArmSystem::haveVirtualization(tc));
344        vbar = tc->readMiscReg(MISCREG_VBAR_EL2);
345        break;
346      case EL1:
347        vbar = tc->readMiscReg(MISCREG_VBAR_EL1);
348        break;
349      default:
350        panic("Invalid target exception level");
351        break;
352    }
353    return vbar + offset64();
354}
355
356MiscRegIndex
357ArmFault::getSyndromeReg64() const
358{
359    switch (toEL) {
360      case EL1:
361        return MISCREG_ESR_EL1;
362      case EL2:
363        return MISCREG_ESR_EL2;
364      case EL3:
365        return MISCREG_ESR_EL3;
366      default:
367        panic("Invalid exception level");
368        break;
369    }
370}
371
372MiscRegIndex
373ArmFault::getFaultAddrReg64() const
374{
375    switch (toEL) {
376      case EL1:
377        return MISCREG_FAR_EL1;
378      case EL2:
379        return MISCREG_FAR_EL2;
380      case EL3:
381        return MISCREG_FAR_EL3;
382      default:
383        panic("Invalid exception level");
384        break;
385    }
386}
387
388void
389ArmFault::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg)
390{
391    uint32_t value;
392    uint32_t exc_class = (uint32_t) ec(tc);
393    uint32_t issVal = iss();
394
395    assert(!from64 || ArmSystem::highestELIs64(tc));
396
397    value = exc_class << 26;
398
399    // HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts (0x24,
400    // 0x25) for which the ISS information is not valid (ARMv7).
401    // @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not
402    // valid it is treated as RES1.
403    if (to64) {
404        value |= 1 << 25;
405    } else if ((bits(exc_class, 5, 3) != 4) ||
406               (bits(exc_class, 2) && bits(issVal, 24))) {
407        if (!machInst.thumb || machInst.bigThumb)
408            value |= 1 << 25;
409    }
410    // Condition code valid for EC[5:4] nonzero
411    if (!from64 && ((bits(exc_class, 5, 4) == 0) &&
412                    (bits(exc_class, 3, 0) != 0))) {
413        if (!machInst.thumb) {
414            uint32_t      cond;
415            ConditionCode condCode = (ConditionCode) (uint32_t) machInst.condCode;
416            // If its on unconditional instruction report with a cond code of
417            // 0xE, ie the unconditional code
418            cond  = (condCode == COND_UC) ? COND_AL : condCode;
419            value |= cond << 20;
420            value |= 1    << 24;
421        }
422        value |= bits(issVal, 19, 0);
423    } else {
424        value |= issVal;
425    }
426    tc->setMiscReg(syndrome_reg, value);
427}
428
429void
430ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
431{
432    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
433
434    if (ArmSystem::highestELIs64(tc)) {  // ARMv8
435        // Determine source exception level and mode
436        fromMode = (OperatingMode) (uint8_t) cpsr.mode;
437        fromEL = opModeToEL(fromMode);
438        if (opModeIs64(fromMode))
439            from64 = true;
440
441        // Determine target exception level
442        if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc)) {
443            toEL = EL3;
444        } else if (ArmSystem::haveVirtualization(tc) && routeToHyp(tc)) {
445            toEL = EL2;
446            hypRouted = true;
447        } else {
448            toEL = opModeToEL(nextMode());
449        }
450
451        if (fromEL > toEL)
452            toEL = fromEL;
453
454        if (toEL == ArmSystem::highestEL(tc) || ELIs64(tc, toEL)) {
455            // Invoke exception handler in AArch64 state
456            to64 = true;
457            invoke64(tc, inst);
458            return;
459        }
460    }
461
462    // ARMv7 (ARM ARM issue C B1.9)
463
464    bool have_security       = ArmSystem::haveSecurity(tc);
465    bool have_virtualization = ArmSystem::haveVirtualization(tc);
466
467    FaultBase::invoke(tc);
468    if (!FullSystem)
469        return;
470    countStat()++;
471
472    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
473    SCR scr = tc->readMiscReg(MISCREG_SCR);
474    CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR);
475    saved_cpsr.nz = tc->readCCReg(CCREG_NZ);
476    saved_cpsr.c = tc->readCCReg(CCREG_C);
477    saved_cpsr.v = tc->readCCReg(CCREG_V);
478    saved_cpsr.ge = tc->readCCReg(CCREG_GE);
479
480    Addr curPc M5_VAR_USED = tc->pcState().pc();
481    ITSTATE it = tc->pcState().itstate();
482    saved_cpsr.it2 = it.top6;
483    saved_cpsr.it1 = it.bottom2;
484
485    // if we have a valid instruction then use it to annotate this fault with
486    // extra information. This is used to generate the correct fault syndrome
487    // information
488    if (inst) {
489        ArmStaticInst *armInst = static_cast<ArmStaticInst *>(inst.get());
490        armInst->annotateFault(this);
491    }
492
493    if (have_security && routeToMonitor(tc)) {
494        cpsr.mode = MODE_MON;
495    } else if (have_virtualization && routeToHyp(tc)) {
496        cpsr.mode = MODE_HYP;
497        hypRouted = true;
498    } else {
499        cpsr.mode = nextMode();
500    }
501
502    // Ensure Secure state if initially in Monitor mode
503    if (have_security && saved_cpsr.mode == MODE_MON) {
504        SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
505        if (scr.ns) {
506            scr.ns = 0;
507            tc->setMiscRegNoEffect(MISCREG_SCR, scr);
508        }
509    }
510
511    // some bits are set differently if we have been routed to hyp mode
512    if (cpsr.mode == MODE_HYP) {
513        SCTLR hsctlr = tc->readMiscReg(MISCREG_HSCTLR);
514        cpsr.t = hsctlr.te;
515        cpsr.e = hsctlr.ee;
516        if (!scr.ea)  {cpsr.a = 1;}
517        if (!scr.fiq) {cpsr.f = 1;}
518        if (!scr.irq) {cpsr.i = 1;}
519    } else if (cpsr.mode == MODE_MON) {
520        // Special case handling when entering monitor mode
521        cpsr.t = sctlr.te;
522        cpsr.e = sctlr.ee;
523        cpsr.a = 1;
524        cpsr.f = 1;
525        cpsr.i = 1;
526    } else {
527        cpsr.t = sctlr.te;
528        cpsr.e = sctlr.ee;
529
530        // The *Disable functions are virtual and different per fault
531        cpsr.a = cpsr.a | abortDisable(tc);
532        cpsr.f = cpsr.f | fiqDisable(tc);
533        cpsr.i = 1;
534    }
535    cpsr.it1 = cpsr.it2 = 0;
536    cpsr.j = 0;
537    tc->setMiscReg(MISCREG_CPSR, cpsr);
538
539    // Make sure mailbox sets to one always
540    tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
541
542    // Clear the exclusive monitor
543    tc->setMiscReg(MISCREG_LOCKFLAG, 0);
544
545    if (cpsr.mode == MODE_HYP) {
546        tc->setMiscReg(MISCREG_ELR_HYP, curPc +
547                (saved_cpsr.t ? thumbPcOffset(true)  : armPcOffset(true)));
548    } else {
549        tc->setIntReg(INTREG_LR, curPc +
550                (saved_cpsr.t ? thumbPcOffset(false) : armPcOffset(false)));
551    }
552
553    switch (cpsr.mode) {
554      case MODE_FIQ:
555        tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
556        break;
557      case MODE_IRQ:
558        tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
559        break;
560      case MODE_SVC:
561        tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
562        break;
563      case MODE_MON:
564        assert(have_security);
565        tc->setMiscReg(MISCREG_SPSR_MON, saved_cpsr);
566        break;
567      case MODE_ABORT:
568        tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
569        break;
570      case MODE_UNDEFINED:
571        tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
572        if (ec(tc) != EC_UNKNOWN)
573            setSyndrome(tc, MISCREG_HSR);
574        break;
575      case MODE_HYP:
576        assert(have_virtualization);
577        tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr);
578        setSyndrome(tc, MISCREG_HSR);
579        break;
580      default:
581        panic("unknown Mode\n");
582    }
583
584    Addr newPc = getVector(tc);
585    DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
586            name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc);
587    PCState pc(newPc);
588    pc.thumb(cpsr.t);
589    pc.nextThumb(pc.thumb());
590    pc.jazelle(cpsr.j);
591    pc.nextJazelle(pc.jazelle());
592    pc.aarch64(!cpsr.width);
593    pc.nextAArch64(!cpsr.width);
594    tc->pcState(pc);
595}
596
597void
598ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst)
599{
600    // Determine actual misc. register indices for ELR_ELx and SPSR_ELx
601    MiscRegIndex elr_idx, spsr_idx;
602    switch (toEL) {
603      case EL1:
604        elr_idx = MISCREG_ELR_EL1;
605        spsr_idx = MISCREG_SPSR_EL1;
606        break;
607      case EL2:
608        assert(ArmSystem::haveVirtualization(tc));
609        elr_idx = MISCREG_ELR_EL2;
610        spsr_idx = MISCREG_SPSR_EL2;
611        break;
612      case EL3:
613        assert(ArmSystem::haveSecurity(tc));
614        elr_idx = MISCREG_ELR_EL3;
615        spsr_idx = MISCREG_SPSR_EL3;
616        break;
617      default:
618        panic("Invalid target exception level");
619        break;
620    }
621
622    // Save process state into SPSR_ELx
623    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
624    CPSR spsr = cpsr;
625    spsr.nz = tc->readCCReg(CCREG_NZ);
626    spsr.c = tc->readCCReg(CCREG_C);
627    spsr.v = tc->readCCReg(CCREG_V);
628    if (from64) {
629        // Force some bitfields to 0
630        spsr.q = 0;
631        spsr.it1 = 0;
632        spsr.j = 0;
633        spsr.res0_23_22 = 0;
634        spsr.ge = 0;
635        spsr.it2 = 0;
636        spsr.t = 0;
637    } else {
638        spsr.ge = tc->readCCReg(CCREG_GE);
639        ITSTATE it = tc->pcState().itstate();
640        spsr.it2 = it.top6;
641        spsr.it1 = it.bottom2;
642        // Force some bitfields to 0
643        spsr.res0_23_22 = 0;
644        spsr.ss = 0;
645    }
646    tc->setMiscReg(spsr_idx, spsr);
647
648    // Save preferred return address into ELR_ELx
649    Addr curr_pc = tc->pcState().pc();
650    Addr ret_addr = curr_pc;
651    if (from64)
652        ret_addr += armPcElrOffset();
653    else
654        ret_addr += spsr.t ? thumbPcElrOffset() : armPcElrOffset();
655    tc->setMiscReg(elr_idx, ret_addr);
656
657    // Update process state
658    OperatingMode64 mode = 0;
659    mode.spX = 1;
660    mode.el = toEL;
661    mode.width = 0;
662    cpsr.mode = mode;
663    cpsr.daif = 0xf;
664    cpsr.il = 0;
665    cpsr.ss = 0;
666    tc->setMiscReg(MISCREG_CPSR, cpsr);
667
668    // Set PC to start of exception handler
669    Addr new_pc = purifyTaggedAddr(getVector64(tc), tc, toEL);
670    DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x "
671            "elr:%#x newVec: %#x\n", name(), cpsr, curr_pc, ret_addr, new_pc);
672    PCState pc(new_pc);
673    pc.aarch64(!cpsr.width);
674    pc.nextAArch64(!cpsr.width);
675    tc->pcState(pc);
676
677    // If we have a valid instruction then use it to annotate this fault with
678    // extra information. This is used to generate the correct fault syndrome
679    // information
680    if (inst)
681        static_cast<ArmStaticInst *>(inst.get())->annotateFault(this);
682    // Save exception syndrome
683    if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ))
684        setSyndrome(tc, getSyndromeReg64());
685}
686
687void
688Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
689{
690    if (FullSystem) {
691        tc->getCpuPtr()->clearInterrupts(tc->threadId());
692        tc->clearArchRegs();
693    }
694    if (!ArmSystem::highestELIs64(tc)) {
695        ArmFault::invoke(tc, inst);
696        tc->setMiscReg(MISCREG_VMPIDR,
697                       getMPIDR(dynamic_cast<ArmSystem*>(tc->getSystemPtr()), tc));
698
699        // Unless we have SMC code to get us there, boot in HYP!
700        if (ArmSystem::haveVirtualization(tc) &&
701            !ArmSystem::haveSecurity(tc)) {
702            CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
703            cpsr.mode = MODE_HYP;
704            tc->setMiscReg(MISCREG_CPSR, cpsr);
705        }
706    } else {
707        // Advance the PC to the IMPLEMENTATION DEFINED reset value
708        PCState pc = ArmSystem::resetAddr64(tc);
709        pc.aarch64(true);
710        pc.nextAArch64(true);
711        tc->pcState(pc);
712    }
713}
714
715void
716UndefinedInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst)
717{
718    if (FullSystem) {
719        ArmFault::invoke(tc, inst);
720        return;
721    }
722
723    // If the mnemonic isn't defined this has to be an unknown instruction.
724    assert(unknown || mnemonic != NULL);
725    if (disabled) {
726        panic("Attempted to execute disabled instruction "
727                "'%s' (inst 0x%08x)", mnemonic, machInst);
728    } else if (unknown) {
729        panic("Attempted to execute unknown instruction (inst 0x%08x)",
730              machInst);
731    } else {
732        panic("Attempted to execute unimplemented instruction "
733                "'%s' (inst 0x%08x)", mnemonic, machInst);
734    }
735}
736
737bool
738UndefinedInstruction::routeToHyp(ThreadContext *tc) const
739{
740    bool toHyp;
741
742    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
743    HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
744    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
745
746    // if in Hyp mode then stay in Hyp mode
747    toHyp  = scr.ns && (cpsr.mode == MODE_HYP);
748    // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
749    toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER);
750    return toHyp;
751}
752
753uint32_t
754UndefinedInstruction::iss() const
755{
756
757    // If UndefinedInstruction is routed to hypervisor, iss field is 0.
758    if (hypRouted) {
759        return 0;
760    }
761
762    if (overrideEc == EC_INVALID)
763        return issRaw;
764
765    uint32_t new_iss = 0;
766    uint32_t op0, op1, op2, CRn, CRm, Rt, dir;
767
768    dir = bits(machInst, 21, 21);
769    op0 = bits(machInst, 20, 19);
770    op1 = bits(machInst, 18, 16);
771    CRn = bits(machInst, 15, 12);
772    CRm = bits(machInst, 11, 8);
773    op2 = bits(machInst, 7, 5);
774    Rt = bits(machInst, 4, 0);
775
776    new_iss = op0 << 20 | op2 << 17 | op1 << 14 | CRn << 10 |
777            Rt << 5 | CRm << 1 | dir;
778
779    return new_iss;
780}
781
782void
783SupervisorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst)
784{
785    if (FullSystem) {
786        ArmFault::invoke(tc, inst);
787        return;
788    }
789
790    // As of now, there isn't a 32 bit thumb version of this instruction.
791    assert(!machInst.bigThumb);
792    uint32_t callNum;
793    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
794    OperatingMode mode = (OperatingMode)(uint8_t)cpsr.mode;
795    if (opModeIs64(mode))
796        callNum = tc->readIntReg(INTREG_X8);
797    else
798        callNum = tc->readIntReg(INTREG_R7);
799    Fault fault;
800    tc->syscall(callNum, &fault);
801
802    // Advance the PC since that won't happen automatically.
803    PCState pc = tc->pcState();
804    assert(inst);
805    inst->advancePC(pc);
806    tc->pcState(pc);
807}
808
809bool
810SupervisorCall::routeToHyp(ThreadContext *tc) const
811{
812    bool toHyp;
813
814    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
815    HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
816    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
817
818    // if in Hyp mode then stay in Hyp mode
819    toHyp  = scr.ns && (cpsr.mode == MODE_HYP);
820    // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
821    toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER);
822    return toHyp;
823}
824
825ExceptionClass
826SupervisorCall::ec(ThreadContext *tc) const
827{
828    return (overrideEc != EC_INVALID) ? overrideEc :
829        (from64 ? EC_SVC_64 : vals.ec);
830}
831
832uint32_t
833SupervisorCall::iss() const
834{
835    // Even if we have a 24 bit imm from an arm32 instruction then we only use
836    // the bottom 16 bits for the ISS value (it doesn't hurt for AArch64 SVC).
837    return issRaw & 0xFFFF;
838}
839
840uint32_t
841SecureMonitorCall::iss() const
842{
843    if (from64)
844        return bits(machInst, 20, 5);
845    return 0;
846}
847
848ExceptionClass
849UndefinedInstruction::ec(ThreadContext *tc) const
850{
851    // If UndefinedInstruction is routed to hypervisor,
852    // HSR.EC field is 0.
853    if (hypRouted)
854        return EC_UNKNOWN;
855    else
856        return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
857}
858
859
860HypervisorCall::HypervisorCall(ExtMachInst _machInst, uint32_t _imm) :
861        ArmFaultVals<HypervisorCall>(_machInst, _imm)
862{}
863
864ExceptionClass
865HypervisorCall::ec(ThreadContext *tc) const
866{
867    return from64 ? EC_HVC_64 : vals.ec;
868}
869
870ExceptionClass
871HypervisorTrap::ec(ThreadContext *tc) const
872{
873    return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
874}
875
876template<class T>
877FaultOffset
878ArmFaultVals<T>::offset(ThreadContext *tc)
879{
880    bool isHypTrap = false;
881
882    // Normally we just use the exception vector from the table at the top if
883    // this file, however if this exception has caused a transition to hype
884    // mode, and its an exception type that would only do this if it has been
885    // trapped then we use the hyp trap vector instead of the normal vector
886    if (vals.hypTrappable) {
887        CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
888        if (cpsr.mode == MODE_HYP) {
889            CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
890            isHypTrap = spsr.mode != MODE_HYP;
891        }
892    }
893    return isHypTrap ? 0x14 : vals.offset;
894}
895
896// void
897// SupervisorCall::setSyndrome64(ThreadContext *tc, MiscRegIndex esr_idx)
898// {
899//     ESR esr = 0;
900//     esr.ec = machInst.aarch64 ? SvcAArch64 : SvcAArch32;
901//     esr.il = !machInst.thumb;
902//     if (machInst.aarch64)
903//         esr.imm16 = bits(machInst.instBits, 20, 5);
904//     else if (machInst.thumb)
905//         esr.imm16 = bits(machInst.instBits, 7, 0);
906//     else
907//         esr.imm16 = bits(machInst.instBits, 15, 0);
908//     tc->setMiscReg(esr_idx, esr);
909// }
910
911void
912SecureMonitorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst)
913{
914    if (FullSystem) {
915        ArmFault::invoke(tc, inst);
916        return;
917    }
918}
919
920ExceptionClass
921SecureMonitorCall::ec(ThreadContext *tc) const
922{
923    return (from64 ? EC_SMC_64 : vals.ec);
924}
925
926bool
927SupervisorTrap::routeToHyp(ThreadContext *tc) const
928{
929    bool toHyp = false;
930
931    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
932    HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
933    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
934
935    // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
936    toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0);
937    return toHyp;
938}
939
940uint32_t
941SupervisorTrap::iss() const
942{
943    // If SupervisorTrap is routed to hypervisor, iss field is 0.
944    if (hypRouted) {
945        return 0;
946    }
947    return issRaw;
948}
949
950ExceptionClass
951SupervisorTrap::ec(ThreadContext *tc) const
952{
953    if (hypRouted)
954        return EC_UNKNOWN;
955    else
956        return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
957}
958
959ExceptionClass
960SecureMonitorTrap::ec(ThreadContext *tc) const
961{
962    return (overrideEc != EC_INVALID) ? overrideEc :
963        (from64 ? EC_SMC_64 : vals.ec);
964}
965
966template<class T>
967void
968AbortFault<T>::invoke(ThreadContext *tc, const StaticInstPtr &inst)
969{
970    if (tranMethod == ArmFault::UnknownTran) {
971        tranMethod = longDescFormatInUse(tc) ? ArmFault::LpaeTran
972                                             : ArmFault::VmsaTran;
973
974        if ((tranMethod == ArmFault::VmsaTran) && this->routeToMonitor(tc)) {
975            // See ARM ARM B3-1416
976            bool override_LPAE = false;
977            TTBCR ttbcr_s = tc->readMiscReg(MISCREG_TTBCR_S);
978            TTBCR M5_VAR_USED ttbcr_ns = tc->readMiscReg(MISCREG_TTBCR_NS);
979            if (ttbcr_s.eae) {
980                override_LPAE = true;
981            } else {
982                // Unimplemented code option, not seen in testing.  May need
983                // extension according to the manual exceprt above.
984                DPRINTF(Faults, "Warning: Incomplete translation method "
985                        "override detected.\n");
986            }
987            if (override_LPAE)
988                tranMethod = ArmFault::LpaeTran;
989        }
990    }
991
992    if (source == ArmFault::AsynchronousExternalAbort) {
993        tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
994    }
995    // Get effective fault source encoding
996    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
997    FSR  fsr  = getFsr(tc);
998
999    // source must be determined BEFORE invoking generic routines which will
1000    // try to set hsr etc. and are based upon source!
1001    ArmFaultVals<T>::invoke(tc, inst);
1002
1003    if (!this->to64) {  // AArch32
1004        if (cpsr.mode == MODE_HYP) {
1005            tc->setMiscReg(T::HFarIndex, faultAddr);
1006        } else if (stage2) {
1007            tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf);
1008            tc->setMiscReg(T::HFarIndex,  OVAddr);
1009        } else {
1010            tc->setMiscReg(T::FsrIndex, fsr);
1011            tc->setMiscReg(T::FarIndex, faultAddr);
1012        }
1013        DPRINTF(Faults, "Abort Fault source=%#x fsr=%#x faultAddr=%#x "\
1014                "tranMethod=%#x\n", source, fsr, faultAddr, tranMethod);
1015    } else {  // AArch64
1016        // Set the FAR register.  Nothing else to do if we are in AArch64 state
1017        // because the syndrome register has already been set inside invoke64()
1018        if (stage2) {
1019            // stage 2 fault, set HPFAR_EL2 to the faulting IPA
1020            // and FAR_EL2 to the Original VA
1021            tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), OVAddr);
1022            tc->setMiscReg(MISCREG_HPFAR_EL2, bits(faultAddr, 47, 12) << 4);
1023
1024            DPRINTF(Faults, "Abort Fault (Stage 2) VA: 0x%x IPA: 0x%x\n",
1025                    OVAddr, faultAddr);
1026        } else {
1027            tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), faultAddr);
1028        }
1029    }
1030}
1031
1032template<class T>
1033FSR
1034AbortFault<T>::getFsr(ThreadContext *tc)
1035{
1036    FSR fsr = 0;
1037
1038    if (((CPSR) tc->readMiscRegNoEffect(MISCREG_CPSR)).width) {
1039        // AArch32
1040        assert(tranMethod != ArmFault::UnknownTran);
1041        if (tranMethod == ArmFault::LpaeTran) {
1042            srcEncoded = ArmFault::longDescFaultSources[source];
1043            fsr.status = srcEncoded;
1044            fsr.lpae   = 1;
1045        } else {
1046            srcEncoded = ArmFault::shortDescFaultSources[source];
1047            fsr.fsLow  = bits(srcEncoded, 3, 0);
1048            fsr.fsHigh = bits(srcEncoded, 4);
1049            fsr.domain = static_cast<uint8_t>(domain);
1050        }
1051        fsr.wnr = (write ? 1 : 0);
1052        fsr.ext = 0;
1053    } else {
1054        // AArch64
1055        srcEncoded = ArmFault::aarch64FaultSources[source];
1056    }
1057    if (srcEncoded == ArmFault::FaultSourceInvalid) {
1058        panic("Invalid fault source\n");
1059    }
1060    return fsr;
1061}
1062
1063template<class T>
1064bool
1065AbortFault<T>::abortDisable(ThreadContext *tc)
1066{
1067    if (ArmSystem::haveSecurity(tc)) {
1068        SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1069        return (!scr.ns || scr.aw);
1070    }
1071    return true;
1072}
1073
1074template<class T>
1075void
1076AbortFault<T>::annotate(ArmFault::AnnotationIDs id, uint64_t val)
1077{
1078    switch (id)
1079    {
1080      case ArmFault::S1PTW:
1081        s1ptw = val;
1082        break;
1083      case ArmFault::OVA:
1084        OVAddr = val;
1085        break;
1086
1087      // Just ignore unknown ID's
1088      default:
1089        break;
1090    }
1091}
1092
1093template<class T>
1094uint32_t
1095AbortFault<T>::iss() const
1096{
1097    uint32_t val;
1098
1099    val  = srcEncoded & 0x3F;
1100    val |= write << 6;
1101    val |= s1ptw << 7;
1102    return (val);
1103}
1104
1105template<class T>
1106bool
1107AbortFault<T>::isMMUFault() const
1108{
1109    // NOTE: Not relying on LL information being aligned to lowest bits here
1110    return
1111         (source == ArmFault::AlignmentFault)     ||
1112        ((source >= ArmFault::TranslationLL) &&
1113         (source <  ArmFault::TranslationLL + 4)) ||
1114        ((source >= ArmFault::AccessFlagLL) &&
1115         (source <  ArmFault::AccessFlagLL + 4))  ||
1116        ((source >= ArmFault::DomainLL) &&
1117         (source <  ArmFault::DomainLL + 4))      ||
1118        ((source >= ArmFault::PermissionLL) &&
1119         (source <  ArmFault::PermissionLL + 4));
1120}
1121
1122ExceptionClass
1123PrefetchAbort::ec(ThreadContext *tc) const
1124{
1125    if (to64) {
1126        // AArch64
1127        if (toEL == fromEL)
1128            return EC_PREFETCH_ABORT_CURR_EL;
1129        else
1130            return EC_PREFETCH_ABORT_LOWER_EL;
1131    } else {
1132        // AArch32
1133        // Abort faults have different EC codes depending on whether
1134        // the fault originated within HYP mode, or not. So override
1135        // the method and add the extra adjustment of the EC value.
1136
1137        ExceptionClass ec = ArmFaultVals<PrefetchAbort>::vals.ec;
1138
1139        CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
1140        if (spsr.mode == MODE_HYP) {
1141            ec = ((ExceptionClass) (((uint32_t) ec) + 1));
1142        }
1143        return ec;
1144    }
1145}
1146
1147bool
1148PrefetchAbort::routeToMonitor(ThreadContext *tc) const
1149{
1150    SCR scr = 0;
1151    if (from64)
1152        scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1153    else
1154        scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1155
1156    return scr.ea && !isMMUFault();
1157}
1158
1159bool
1160PrefetchAbort::routeToHyp(ThreadContext *tc) const
1161{
1162    bool toHyp;
1163
1164    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
1165    HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
1166    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1167    HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
1168
1169    // if in Hyp mode then stay in Hyp mode
1170    toHyp  = scr.ns && (cpsr.mode == MODE_HYP);
1171    // otherwise, check whether to take to Hyp mode through Hyp Trap vector
1172    toHyp |= (stage2 ||
1173                ( (source ==               DebugEvent) && hdcr.tde && (cpsr.mode !=  MODE_HYP)) ||
1174                ( (source == SynchronousExternalAbort) && hcr.tge  && (cpsr.mode == MODE_USER))
1175             ) && !inSecureState(tc);
1176    return toHyp;
1177}
1178
1179ExceptionClass
1180DataAbort::ec(ThreadContext *tc) const
1181{
1182    if (to64) {
1183        // AArch64
1184        if (source == ArmFault::AsynchronousExternalAbort) {
1185            panic("Asynchronous External Abort should be handled with "
1186                    "SystemErrors (SErrors)!");
1187        }
1188        if (toEL == fromEL)
1189            return EC_DATA_ABORT_CURR_EL;
1190        else
1191            return EC_DATA_ABORT_LOWER_EL;
1192    } else {
1193        // AArch32
1194        // Abort faults have different EC codes depending on whether
1195        // the fault originated within HYP mode, or not. So override
1196        // the method and add the extra adjustment of the EC value.
1197
1198        ExceptionClass ec = ArmFaultVals<DataAbort>::vals.ec;
1199
1200        CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
1201        if (spsr.mode == MODE_HYP) {
1202            ec = ((ExceptionClass) (((uint32_t) ec) + 1));
1203        }
1204        return ec;
1205    }
1206}
1207
1208bool
1209DataAbort::routeToMonitor(ThreadContext *tc) const
1210{
1211    SCR scr = 0;
1212    if (from64)
1213        scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1214    else
1215        scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1216
1217    return scr.ea && !isMMUFault();
1218}
1219
1220bool
1221DataAbort::routeToHyp(ThreadContext *tc) const
1222{
1223    bool toHyp;
1224
1225    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
1226    HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
1227    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1228    HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
1229
1230    // if in Hyp mode then stay in Hyp mode
1231    toHyp  = scr.ns && (cpsr.mode == MODE_HYP);
1232    // otherwise, check whether to take to Hyp mode through Hyp Trap vector
1233    toHyp |= (stage2 ||
1234                ( (cpsr.mode != MODE_HYP) && ( ((source == AsynchronousExternalAbort) && hcr.amo) ||
1235                                               ((source == DebugEvent) && hdcr.tde) )
1236                ) ||
1237                ( (cpsr.mode == MODE_USER) && hcr.tge &&
1238                  ((source == AlignmentFault)            ||
1239                   (source == SynchronousExternalAbort))
1240                )
1241             ) && !inSecureState(tc);
1242    return toHyp;
1243}
1244
1245uint32_t
1246DataAbort::iss() const
1247{
1248    uint32_t val;
1249
1250    // Add on the data abort specific fields to the generic abort ISS value
1251    val  = AbortFault<DataAbort>::iss();
1252    // ISS is valid if not caused by a stage 1 page table walk, and when taken
1253    // to AArch64 only when directed to EL2
1254    if (!s1ptw && (!to64 || toEL == EL2)) {
1255        val |= isv << 24;
1256        if (isv) {
1257            val |= sas << 22;
1258            val |= sse << 21;
1259            val |= srt << 16;
1260            // AArch64 only. These assignments are safe on AArch32 as well
1261            // because these vars are initialized to false
1262            val |= sf << 15;
1263            val |= ar << 14;
1264        }
1265    }
1266    return (val);
1267}
1268
1269void
1270DataAbort::annotate(AnnotationIDs id, uint64_t val)
1271{
1272    AbortFault<DataAbort>::annotate(id, val);
1273    switch (id)
1274    {
1275      case SAS:
1276        isv = true;
1277        sas = val;
1278        break;
1279      case SSE:
1280        isv = true;
1281        sse = val;
1282        break;
1283      case SRT:
1284        isv = true;
1285        srt = val;
1286        break;
1287      case SF:
1288        isv = true;
1289        sf  = val;
1290        break;
1291      case AR:
1292        isv = true;
1293        ar  = val;
1294        break;
1295      // Just ignore unknown ID's
1296      default:
1297        break;
1298    }
1299}
1300
1301void
1302VirtualDataAbort::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1303{
1304    AbortFault<VirtualDataAbort>::invoke(tc, inst);
1305    HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1306    hcr.va = 0;
1307    tc->setMiscRegNoEffect(MISCREG_HCR, hcr);
1308}
1309
1310bool
1311Interrupt::routeToMonitor(ThreadContext *tc) const
1312{
1313    assert(ArmSystem::haveSecurity(tc));
1314    SCR scr = 0;
1315    if (from64)
1316        scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1317    else
1318        scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1319    return scr.irq;
1320}
1321
1322bool
1323Interrupt::routeToHyp(ThreadContext *tc) const
1324{
1325    bool toHyp;
1326
1327    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
1328    HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
1329    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1330    // Determine whether IRQs are routed to Hyp mode.
1331    toHyp = (!scr.irq && hcr.imo && !inSecureState(tc)) ||
1332            (cpsr.mode == MODE_HYP);
1333    return toHyp;
1334}
1335
1336bool
1337Interrupt::abortDisable(ThreadContext *tc)
1338{
1339    if (ArmSystem::haveSecurity(tc)) {
1340        SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1341        return (!scr.ns || scr.aw);
1342    }
1343    return true;
1344}
1345
1346VirtualInterrupt::VirtualInterrupt()
1347{}
1348
1349bool
1350FastInterrupt::routeToMonitor(ThreadContext *tc) const
1351{
1352    assert(ArmSystem::haveSecurity(tc));
1353    SCR scr = 0;
1354    if (from64)
1355        scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1356    else
1357        scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1358    return scr.fiq;
1359}
1360
1361bool
1362FastInterrupt::routeToHyp(ThreadContext *tc) const
1363{
1364    bool toHyp;
1365
1366    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
1367    HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
1368    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1369    // Determine whether IRQs are routed to Hyp mode.
1370    toHyp = (!scr.fiq && hcr.fmo && !inSecureState(tc)) ||
1371            (cpsr.mode == MODE_HYP);
1372    return toHyp;
1373}
1374
1375bool
1376FastInterrupt::abortDisable(ThreadContext *tc)
1377{
1378    if (ArmSystem::haveSecurity(tc)) {
1379        SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1380        return (!scr.ns || scr.aw);
1381    }
1382    return true;
1383}
1384
1385bool
1386FastInterrupt::fiqDisable(ThreadContext *tc)
1387{
1388    if (ArmSystem::haveVirtualization(tc)) {
1389        return true;
1390    } else if (ArmSystem::haveSecurity(tc)) {
1391        SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1392        return (!scr.ns || scr.fw);
1393    }
1394    return true;
1395}
1396
1397VirtualFastInterrupt::VirtualFastInterrupt()
1398{}
1399
1400void
1401PCAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1402{
1403    ArmFaultVals<PCAlignmentFault>::invoke(tc, inst);
1404    assert(from64);
1405    // Set the FAR
1406    tc->setMiscReg(getFaultAddrReg64(), faultPC);
1407}
1408
1409SPAlignmentFault::SPAlignmentFault()
1410{}
1411
1412SystemError::SystemError()
1413{}
1414
1415void
1416SystemError::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1417{
1418    tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
1419    ArmFault::invoke(tc, inst);
1420}
1421
1422bool
1423SystemError::routeToMonitor(ThreadContext *tc) const
1424{
1425    assert(ArmSystem::haveSecurity(tc));
1426    assert(from64);
1427    SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1428    return scr.ea;
1429}
1430
1431bool
1432SystemError::routeToHyp(ThreadContext *tc) const
1433{
1434    bool toHyp;
1435    assert(from64);
1436
1437    SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1438    HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
1439
1440    toHyp = (!scr.ea && hcr.amo && !inSecureState(tc)) ||
1441            (!scr.ea && !scr.rw && !hcr.amo && !inSecureState(tc));
1442    return toHyp;
1443}
1444
1445
1446SoftwareBreakpoint::SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss)
1447    : ArmFaultVals<SoftwareBreakpoint>(_mach_inst, _iss)
1448{}
1449
1450bool
1451SoftwareBreakpoint::routeToHyp(ThreadContext *tc) const
1452{
1453    assert(from64);
1454
1455    const bool have_el2 = ArmSystem::haveVirtualization(tc);
1456
1457    const HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1458    const HDCR mdcr  = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1459
1460    return have_el2 && !inSecureState(tc) && fromEL <= EL1 &&
1461        (hcr.tge || mdcr.tde);
1462}
1463
1464void
1465ArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) {
1466    DPRINTF(Faults, "Invoking ArmSev Fault\n");
1467    if (!FullSystem)
1468        return;
1469
1470    // Set sev_mailbox to 1, clear the pending interrupt from remote
1471    // SEV execution and let pipeline continue as pcState is still
1472    // valid.
1473    tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
1474    tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_SEV, 0);
1475}
1476
1477// Instantiate all the templates to make the linker happy
1478template class ArmFaultVals<Reset>;
1479template class ArmFaultVals<UndefinedInstruction>;
1480template class ArmFaultVals<SupervisorCall>;
1481template class ArmFaultVals<SecureMonitorCall>;
1482template class ArmFaultVals<HypervisorCall>;
1483template class ArmFaultVals<PrefetchAbort>;
1484template class ArmFaultVals<DataAbort>;
1485template class ArmFaultVals<VirtualDataAbort>;
1486template class ArmFaultVals<HypervisorTrap>;
1487template class ArmFaultVals<Interrupt>;
1488template class ArmFaultVals<VirtualInterrupt>;
1489template class ArmFaultVals<FastInterrupt>;
1490template class ArmFaultVals<VirtualFastInterrupt>;
1491template class ArmFaultVals<SupervisorTrap>;
1492template class ArmFaultVals<SecureMonitorTrap>;
1493template class ArmFaultVals<PCAlignmentFault>;
1494template class ArmFaultVals<SPAlignmentFault>;
1495template class ArmFaultVals<SystemError>;
1496template class ArmFaultVals<SoftwareBreakpoint>;
1497template class ArmFaultVals<ArmSev>;
1498template class AbortFault<PrefetchAbort>;
1499template class AbortFault<DataAbort>;
1500template class AbortFault<VirtualDataAbort>;
1501
1502
1503IllegalInstSetStateFault::IllegalInstSetStateFault()
1504{}
1505
1506
1507} // namespace ArmISA
1508