faults.cc revision 8518:9c87727099ce 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 *          Gabe Black
43 */
44
45#include "arch/arm/faults.hh"
46#include "base/trace.hh"
47#include "cpu/base.hh"
48#include "cpu/thread_context.hh"
49#include "debug/Faults.hh"
50
51namespace ArmISA
52{
53
54template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals =
55    {"reset", 0x00, MODE_SVC, 0, 0, true, true};
56
57template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals =
58    {"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ;
59
60template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals =
61    {"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false};
62
63template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals =
64    {"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false};
65
66template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals =
67    {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false};
68
69template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals =
70    {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false};
71
72template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals =
73    {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true};
74
75template<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals =
76    {"Pipe Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values
77
78template<> ArmFault::FaultVals ArmFaultVals<ReExec>::vals =
79    {"ReExec Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values
80
81template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals =
82    {"ArmSev Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values
83Addr
84ArmFault::getVector(ThreadContext *tc)
85{
86    // ARM ARM B1-3
87
88    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
89
90    // panic if SCTLR.VE because I have no idea what to do with vectored
91    // interrupts
92    assert(!sctlr.ve);
93
94    if (!sctlr.v)
95        return offset();
96    return offset() + HighVecs;
97
98}
99
100#if FULL_SYSTEM
101
102void
103ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
104{
105    // ARM ARM B1.6.3
106    FaultBase::invoke(tc);
107    countStat()++;
108
109    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
110    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
111    CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR);
112    saved_cpsr.nz = tc->readIntReg(INTREG_CONDCODES_NZ);
113    saved_cpsr.c = tc->readIntReg(INTREG_CONDCODES_C);
114    saved_cpsr.v = tc->readIntReg(INTREG_CONDCODES_V);
115    saved_cpsr.ge = tc->readIntReg(INTREG_CONDCODES_GE);
116
117    Addr curPc M5_VAR_USED = tc->pcState().pc();
118    ITSTATE it = tc->pcState().itstate();
119    saved_cpsr.it2 = it.top6;
120    saved_cpsr.it1 = it.bottom2;
121
122    cpsr.mode = nextMode();
123    cpsr.it1 = cpsr.it2 = 0;
124    cpsr.j = 0;
125
126    cpsr.t = sctlr.te;
127    cpsr.a = cpsr.a | abortDisable();
128    cpsr.f = cpsr.f | fiqDisable();
129    cpsr.i = 1;
130    cpsr.e = sctlr.ee;
131    tc->setMiscReg(MISCREG_CPSR, cpsr);
132    // Make sure mailbox sets to one always
133    tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
134    tc->setIntReg(INTREG_LR, curPc +
135            (saved_cpsr.t ? thumbPcOffset() : armPcOffset()));
136
137    switch (nextMode()) {
138      case MODE_FIQ:
139        tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
140        break;
141      case MODE_IRQ:
142        tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
143        break;
144      case MODE_SVC:
145        tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
146        break;
147      case MODE_UNDEFINED:
148        tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
149        break;
150      case MODE_ABORT:
151        tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
152        break;
153      default:
154        panic("unknown Mode\n");
155    }
156
157    Addr newPc = getVector(tc);
158    DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
159            name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc);
160    PCState pc(newPc);
161    pc.thumb(cpsr.t);
162    pc.nextThumb(pc.thumb());
163    pc.jazelle(cpsr.j);
164    pc.nextJazelle(pc.jazelle());
165    tc->pcState(pc);
166}
167
168void
169Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
170{
171    tc->getCpuPtr()->clearInterrupts();
172    tc->clearArchRegs();
173    ArmFault::invoke(tc, inst);
174}
175
176#else
177
178void
179UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
180{
181    // If the mnemonic isn't defined this has to be an unknown instruction.
182    assert(unknown || mnemonic != NULL);
183    if (disabled) {
184        panic("Attempted to execute disabled instruction "
185                "'%s' (inst 0x%08x)", mnemonic, machInst);
186    } else if (unknown) {
187        panic("Attempted to execute unknown instruction (inst 0x%08x)",
188              machInst);
189    } else {
190        panic("Attempted to execute unimplemented instruction "
191                "'%s' (inst 0x%08x)", mnemonic, machInst);
192    }
193}
194
195void
196SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
197{
198    // As of now, there isn't a 32 bit thumb version of this instruction.
199    assert(!machInst.bigThumb);
200    uint32_t callNum;
201    callNum = tc->readIntReg(INTREG_R7);
202    tc->syscall(callNum);
203
204    // Advance the PC since that won't happen automatically.
205    PCState pc = tc->pcState();
206    assert(inst);
207    inst->advancePC(pc);
208    tc->pcState(pc);
209}
210
211#endif // FULL_SYSTEM
212
213template<class T>
214void
215AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
216{
217    ArmFaultVals<T>::invoke(tc, inst);
218    FSR fsr = 0;
219    fsr.fsLow = bits(status, 3, 0);
220    fsr.fsHigh = bits(status, 4);
221    fsr.domain = domain;
222    fsr.wnr = (write ? 1 : 0);
223    fsr.ext = 0;
224    tc->setMiscReg(T::FsrIndex, fsr);
225    tc->setMiscReg(T::FarIndex, faultAddr);
226
227    DPRINTF(Faults, "Abort Fault fsr=%#x faultAddr=%#x\n", fsr, faultAddr);
228}
229
230void
231FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) {
232    DPRINTF(Faults, "Invoking FlushPipe Fault\n");
233
234    // Set the PC to the next instruction of the faulting instruction.
235    // Net effect is simply squashing all instructions behind and
236    // start refetching from the next instruction.
237    PCState pc = tc->pcState();
238    assert(inst);
239    inst->advancePC(pc);
240    tc->pcState(pc);
241}
242
243void
244ReExec::invoke(ThreadContext *tc, StaticInstPtr inst) {
245    DPRINTF(Faults, "Invoking ReExec Fault\n");
246
247    // Set the PC to then the faulting instruction.
248    // Net effect is simply squashing all instructions including this
249    // instruction and refetching/rexecuting current instruction
250    PCState pc = tc->pcState();
251    tc->pcState(pc);
252}
253
254template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc,
255                                                StaticInstPtr inst);
256template void AbortFault<DataAbort>::invoke(ThreadContext *tc,
257                                            StaticInstPtr inst);
258
259void
260ArmSev::invoke(ThreadContext *tc, StaticInstPtr inst) {
261    DPRINTF(Faults, "Invoking ArmSev Fault\n");
262#if FULL_SYSTEM
263    // Set sev_mailbox to 1, clear the pending interrupt from remote
264    // SEV execution and let pipeline continue as pcState is still
265    // valid.
266    tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
267    tc->getCpuPtr()->clearInterrupt(INT_SEV, 0);
268#endif
269}
270
271// return via SUBS pc, lr, xxx; rfe, movs, ldm
272
273} // namespace ArmISA
274