14826Ssaidi@eecs.umich.edu/* 24826Ssaidi@eecs.umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 34826Ssaidi@eecs.umich.edu * All rights reserved. 44826Ssaidi@eecs.umich.edu * 54826Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 64826Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 74826Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 84826Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 94826Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 104826Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 114826Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 124826Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 134826Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 144826Ssaidi@eecs.umich.edu * this software without specific prior written permission. 154826Ssaidi@eecs.umich.edu * 164826Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174826Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184826Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194826Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204826Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214826Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224826Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234826Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244826Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254826Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264826Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274826Ssaidi@eecs.umich.edu * 284826Ssaidi@eecs.umich.edu * Authors: Gabe Black 294826Ssaidi@eecs.umich.edu * Ali Saidi 304826Ssaidi@eecs.umich.edu */ 314826Ssaidi@eecs.umich.edu 3211793Sbrandon.potter@amd.com#include "arch/sparc/utility.hh" 3311793Sbrandon.potter@amd.com 347678Sgblack@eecs.umich.edu#include "arch/sparc/faults.hh" 354826Ssaidi@eecs.umich.edu#include "arch/sparc/vtophys.hh" 368706Sandreas.hansson@arm.com#include "mem/fs_translating_port_proxy.hh" 374826Ssaidi@eecs.umich.edu 384826Ssaidi@eecs.umich.edunamespace SparcISA { 394826Ssaidi@eecs.umich.edu 404826Ssaidi@eecs.umich.edu 417741Sgblack@eecs.umich.edu// The caller uses %o0-%05 for the first 6 arguments even if their floating 427741Sgblack@eecs.umich.edu// point. Double precision floating point values take two registers/args. 437741Sgblack@eecs.umich.edu// Quads, structs, and unions are passed as pointers. All arguments beyond 447741Sgblack@eecs.umich.edu// the sixth are passed on the stack past the 16 word window save area, 457741Sgblack@eecs.umich.edu// space for the struct/union return pointer, and space reserved for the 467741Sgblack@eecs.umich.edu// first 6 arguments which the caller may use but doesn't have to. 477707Sgblack@eecs.umich.eduuint64_t 487707Sgblack@eecs.umich.edugetArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) 497707Sgblack@eecs.umich.edu{ 508806Sgblack@eecs.umich.edu if (!FullSystem) { 518767Sgblack@eecs.umich.edu panic("getArgument() only implemented for full system\n"); 528767Sgblack@eecs.umich.edu M5_DUMMY_RETURN 534826Ssaidi@eecs.umich.edu } 548806Sgblack@eecs.umich.edu 558806Sgblack@eecs.umich.edu const int NumArgumentRegs = 6; 568806Sgblack@eecs.umich.edu if (number < NumArgumentRegs) { 578806Sgblack@eecs.umich.edu return tc->readIntReg(8 + number); 588806Sgblack@eecs.umich.edu } else { 598806Sgblack@eecs.umich.edu Addr sp = tc->readIntReg(StackPointerReg); 6014020Sgabeblack@google.com PortProxy &vp = tc->getVirtProxy(); 618852Sandreas.hansson@arm.com uint64_t arg = vp.read<uint64_t>(sp + 92 + 628806Sgblack@eecs.umich.edu (number-NumArgumentRegs) * sizeof(uint64_t)); 638806Sgblack@eecs.umich.edu return arg; 648806Sgblack@eecs.umich.edu } 654826Ssaidi@eecs.umich.edu} 666329Sgblack@eecs.umich.edu 676329Sgblack@eecs.umich.eduvoid 686329Sgblack@eecs.umich.educopyMiscRegs(ThreadContext *src, ThreadContext *dest) 696329Sgblack@eecs.umich.edu{ 706329Sgblack@eecs.umich.edu 716329Sgblack@eecs.umich.edu uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL); 726329Sgblack@eecs.umich.edu 736329Sgblack@eecs.umich.edu // Read all the trap level dependent registers and save them off 747741Sgblack@eecs.umich.edu for (int i = 1; i <= MaxTL; i++) { 756329Sgblack@eecs.umich.edu src->setMiscRegNoEffect(MISCREG_TL, i); 766329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TL, i); 776329Sgblack@eecs.umich.edu 787741Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TT, 797741Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_TT)); 807741Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TPC, 817741Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_TPC)); 827741Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TNPC, 837741Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_TNPC)); 847741Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TSTATE, 857741Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_TSTATE)); 866329Sgblack@eecs.umich.edu } 876329Sgblack@eecs.umich.edu 886329Sgblack@eecs.umich.edu // Save off the traplevel 896329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TL, tl); 906329Sgblack@eecs.umich.edu src->setMiscRegNoEffect(MISCREG_TL, tl); 916329Sgblack@eecs.umich.edu 926329Sgblack@eecs.umich.edu 936329Sgblack@eecs.umich.edu // ASRs 947741Sgblack@eecs.umich.edu// dest->setMiscRegNoEffect(MISCREG_Y, 957741Sgblack@eecs.umich.edu// src->readMiscRegNoEffect(MISCREG_Y)); 967741Sgblack@eecs.umich.edu// dest->setMiscRegNoEffect(MISCREG_CCR, 977741Sgblack@eecs.umich.edu// src->readMiscRegNoEffect(MISCREG_CCR)); 989375Sgblack@eecs.umich.edu dest->setMiscReg(MISCREG_ASI, 997741Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_ASI)); 1007741Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TICK, 1017741Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_TICK)); 1027741Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_FPRS, 1037741Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_FPRS)); 1047741Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SOFTINT, 1057741Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SOFTINT)); 1067741Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TICK_CMPR, 1077741Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_TICK_CMPR)); 1087741Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_STICK, 1097741Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_STICK)); 1107741Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_STICK_CMPR, 1117741Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_STICK_CMPR)); 1126329Sgblack@eecs.umich.edu 1136329Sgblack@eecs.umich.edu // Priv Registers 1147741Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TICK, 1157741Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_TICK)); 1167741Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TBA, 1177741Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_TBA)); 1187741Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_PSTATE, 1197741Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_PSTATE)); 1207741Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_PIL, 1217741Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_PIL)); 1227741Sgblack@eecs.umich.edu dest->setMiscReg(MISCREG_CWP, 1237741Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_CWP)); 1247741Sgblack@eecs.umich.edu// dest->setMiscRegNoEffect(MISCREG_CANSAVE, 1257741Sgblack@eecs.umich.edu// src->readMiscRegNoEffect(MISCREG_CANSAVE)); 1267741Sgblack@eecs.umich.edu// dest->setMiscRegNoEffect(MISCREG_CANRESTORE, 1277741Sgblack@eecs.umich.edu// src->readMiscRegNoEffect(MISCREG_CANRESTORE)); 1287741Sgblack@eecs.umich.edu// dest->setMiscRegNoEffect(MISCREG_OTHERWIN, 1297741Sgblack@eecs.umich.edu// src->readMiscRegNoEffect(MISCREG_OTHERWIN)); 1307741Sgblack@eecs.umich.edu// dest->setMiscRegNoEffect(MISCREG_CLEANWIN, 1317741Sgblack@eecs.umich.edu// src->readMiscRegNoEffect(MISCREG_CLEANWIN)); 1327741Sgblack@eecs.umich.edu// dest->setMiscRegNoEffect(MISCREG_WSTATE, 1337741Sgblack@eecs.umich.edu// src->readMiscRegNoEffect(MISCREG_WSTATE)); 1346337Sgblack@eecs.umich.edu dest->setMiscReg(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL)); 1356329Sgblack@eecs.umich.edu 1366329Sgblack@eecs.umich.edu // Hyperprivilged registers 1377741Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_HPSTATE, 1387741Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_HPSTATE)); 1397741Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_HINTP, 1407741Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_HINTP)); 1417741Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_HTBA, 1427741Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_HTBA)); 1436329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, 1446329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); 1456329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR, 1466329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR)); 1476329Sgblack@eecs.umich.edu 1486329Sgblack@eecs.umich.edu // FSR 1497741Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_FSR, 1507741Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_FSR)); 1516329Sgblack@eecs.umich.edu 1527741Sgblack@eecs.umich.edu // Strand Status Register 1536329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, 1546329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); 1556329Sgblack@eecs.umich.edu 1566329Sgblack@eecs.umich.edu // MMU Registers 1576329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT, 1586329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT)); 1596329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT, 1606329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT)); 1616329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID, 1626329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_MMU_PART_ID)); 1636329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 1646329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL)); 1656329Sgblack@eecs.umich.edu 1666329Sgblack@eecs.umich.edu // Scratchpad Registers 1676329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0, 1686329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0)); 1696329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1, 1706329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1)); 1716329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2, 1726329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2)); 1736329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3, 1746329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3)); 1756329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4, 1766329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4)); 1776329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5, 1786329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5)); 1796329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6, 1806329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6)); 1816329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7, 1826329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7)); 1836329Sgblack@eecs.umich.edu 1846329Sgblack@eecs.umich.edu // Queue Registers 1856329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD, 1866329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD)); 1876329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL, 1886329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL)); 1896329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD, 1906329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD)); 1916329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL, 1926329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL)); 1936329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD, 1946329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD)); 1956329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL, 1966329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL)); 1976329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD, 1986329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD)); 1996329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL, 2006329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL)); 2016329Sgblack@eecs.umich.edu} 2026329Sgblack@eecs.umich.edu 2036329Sgblack@eecs.umich.eduvoid 2046329Sgblack@eecs.umich.educopyRegs(ThreadContext *src, ThreadContext *dest) 2056329Sgblack@eecs.umich.edu{ 2067741Sgblack@eecs.umich.edu // First loop through the integer registers. 2076329Sgblack@eecs.umich.edu int old_gl = src->readMiscRegNoEffect(MISCREG_GL); 2086329Sgblack@eecs.umich.edu int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP); 2097741Sgblack@eecs.umich.edu // Globals 2106329Sgblack@eecs.umich.edu for (int x = 0; x < MaxGL; ++x) { 2116337Sgblack@eecs.umich.edu src->setMiscReg(MISCREG_GL, x); 2126337Sgblack@eecs.umich.edu dest->setMiscReg(MISCREG_GL, x); 2136329Sgblack@eecs.umich.edu // Skip %g0 which is always zero. 2146329Sgblack@eecs.umich.edu for (int y = 1; y < 8; y++) 2156329Sgblack@eecs.umich.edu dest->setIntReg(y, src->readIntReg(y)); 2166329Sgblack@eecs.umich.edu } 2177741Sgblack@eecs.umich.edu // Locals and ins. Outs are all also ins. 2186329Sgblack@eecs.umich.edu for (int x = 0; x < NWindows; ++x) { 2196337Sgblack@eecs.umich.edu src->setMiscReg(MISCREG_CWP, x); 2206337Sgblack@eecs.umich.edu dest->setMiscReg(MISCREG_CWP, x); 2216329Sgblack@eecs.umich.edu for (int y = 16; y < 32; y++) 2226329Sgblack@eecs.umich.edu dest->setIntReg(y, src->readIntReg(y)); 2236329Sgblack@eecs.umich.edu } 2247741Sgblack@eecs.umich.edu // Microcode reg and pseudo int regs (misc regs in the integer regfile). 2256329Sgblack@eecs.umich.edu for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y) 2266329Sgblack@eecs.umich.edu dest->setIntReg(y, src->readIntReg(y)); 2276329Sgblack@eecs.umich.edu 2287741Sgblack@eecs.umich.edu // Restore src's GL, CWP 2296337Sgblack@eecs.umich.edu src->setMiscReg(MISCREG_GL, old_gl); 2306337Sgblack@eecs.umich.edu src->setMiscReg(MISCREG_CWP, old_cwp); 2316329Sgblack@eecs.umich.edu 2326329Sgblack@eecs.umich.edu 2336329Sgblack@eecs.umich.edu // Then loop through the floating point registers. 2346329Sgblack@eecs.umich.edu for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) { 23513611Sgabeblack@google.com dest->setFloatReg(i, src->readFloatReg(i)); 2366329Sgblack@eecs.umich.edu } 2376329Sgblack@eecs.umich.edu 2389920Syasuko.eckert@amd.com // Would need to add condition-code regs if implemented 2399920Syasuko.eckert@amd.com assert(NumCCRegs == 0); 2409920Syasuko.eckert@amd.com 2416329Sgblack@eecs.umich.edu // Copy misc. registers 2426329Sgblack@eecs.umich.edu copyMiscRegs(src, dest); 2436329Sgblack@eecs.umich.edu 2446329Sgblack@eecs.umich.edu // Lastly copy PC/NPC 2457720Sgblack@eecs.umich.edu dest->pcState(src->pcState()); 2466329Sgblack@eecs.umich.edu} 2477678Sgblack@eecs.umich.edu 2487678Sgblack@eecs.umich.eduvoid 2497693SAli.Saidi@ARM.comskipFunction(ThreadContext *tc) 2507693SAli.Saidi@ARM.com{ 25113915Sgabeblack@google.com PCState newPC = tc->pcState(); 2527720Sgblack@eecs.umich.edu newPC.set(tc->readIntReg(ReturnAddressReg)); 2537720Sgblack@eecs.umich.edu tc->pcState(newPC); 2547693SAli.Saidi@ARM.com} 2557693SAli.Saidi@ARM.com 2567693SAli.Saidi@ARM.com 2577693SAli.Saidi@ARM.comvoid 2587678Sgblack@eecs.umich.eduinitCPU(ThreadContext *tc, int cpuId) 2597678Sgblack@eecs.umich.edu{ 26010474Sandreas.hansson@arm.com static Fault por = std::make_shared<PowerOnReset>(); 2617678Sgblack@eecs.umich.edu if (cpuId == 0) 2627678Sgblack@eecs.umich.edu por->invoke(tc); 2637678Sgblack@eecs.umich.edu} 2647678Sgblack@eecs.umich.edu 2657741Sgblack@eecs.umich.edu} // namespace SPARC_ISA 266