/gem5/ext/nomali/lib/ |
H A D | mali_midgard.cc | 46 MaliMidgard::setupControlIdRegisters(RegVector ®s) argument 48 regs[RegAddr(L2_FEATURES)] = 54 regs[RegAddr(TILER_FEATURES)] = 59 regs[RegAddr(MEM_FEATURES)] = 0x1; 61 regs[RegAddr(MMU_FEATURES)] = 0x2830; 62 regs[RegAddr(AS_PRESENT)] = 0xff; 63 regs[RegAddr(JS_PRESENT)] = 0x7; 64 regs[RegAddr(JS0_FEATURES)] = 0x20e; 65 regs[RegAddr(JS1_FEATURES)] = 0x1fe; 66 regs[RegAdd [all...] |
H A D | mali_t7xx.cc | 33 MaliT7xxBase::setupControlIdRegisters(RegVector ®s) argument 35 MaliMidgard::setupControlIdRegisters(regs); 37 regs[RegAddr(L2_FEATURES)] =
|
H A D | jobslot.cc | 73 regs[addr] = value; 100 return regs[RegAddr(JSn_COMMAND_NEXT)] == JSn_COMMAND_START; 107 if (regs[RegAddr(JSn_COMMAND_NEXT)] != JSn_COMMAND_START ) 111 regs[RegAddr(JSn_STATUS)] = STATUS_ACTIVE.value; 115 regs.set64(RegAddr(JSn_HEAD_LO), regs.get64(RegAddr(JSn_HEAD_NEXT_LO))); 116 regs.set64(RegAddr(JSn_TAIL_LO), regs.get64(RegAddr(JSn_HEAD_NEXT_LO))); 117 regs.set64(RegAddr(JSn_AFFINITY_LO), 118 regs [all...] |
H A D | mali_t6xx.cc | 33 MaliT6xxBase::setupControlIdRegisters(RegVector ®s) argument 35 MaliMidgard::setupControlIdRegisters(regs); 37 regs[RegAddr(L2_FEATURES)] =
|
H A D | mali_t7xx.hh | 35 void setupControlIdRegisters(RegVector ®s) override;
|
H A D | gpublock.cc | 28 : gpu(_gpu), regs(BLOCK_NUM_REGS) 33 : gpu(_gpu), regs(no_regs) 39 regs(std::move(rhs.regs)) 50 for (auto &r : regs) 69 return regs[addr]; 75 regs[addr] = value; 132 regs[addrIrqRawStat] |= ints; 143 regs[addrIrqRawStat] &= ~ints; 152 return regs[addrIrqRawSta [all...] |
H A D | mali_t6xx.hh | 35 void setupControlIdRegisters(RegVector ®s) override;
|
H A D | mali_midgard.hh | 58 virtual void setupControlIdRegisters(RegVector ®s);
|
/gem5/src/dev/arm/ |
H A D | smmu_v3_cmdexec.cc | 63 smmu.regs.cmdq_base & Q_BASE_SIZE_MASK); 67 (smmu.regs.cmdq_base & Q_BASE_SIZE_MASK) + 1); 69 if ((smmu.regs.cmdq_cons & size_mask_wrap) == 70 (smmu.regs.cmdq_prod & size_mask_wrap)) 74 (smmu.regs.cmdq_base & Q_BASE_ADDR_MASK) + 75 (smmu.regs.cmdq_cons & size_mask) * sizeof(SMMUCommand); 78 smmu.regs.cmdq_cons = (smmu.regs.cmdq_cons + 1) & size_mask_wrap;
|
H A D | smmu_v3.cc | 106 memset(®s, 0, sizeof(regs)); 109 regs.idr0 = params->smmu_idr0; 110 regs.idr1 = params->smmu_idr1; 111 regs.idr2 = params->smmu_idr2; 112 regs.idr3 = params->smmu_idr3; 113 regs.idr4 = params->smmu_idr4; 114 regs.idr5 = params->smmu_idr5; 115 regs.iidr = params->smmu_iidr; 116 regs [all...] |
/gem5/src/dev/net/ |
H A D | ns_gige.cc | 221 reg = regs.command; 227 reg = regs.config; 231 reg = regs.mear; 235 reg = regs.ptscr; 239 reg = regs.isr; 244 reg = regs.imr; 248 reg = regs.ier; 252 reg = regs.ihr; 256 reg = regs.txdp; 260 reg = regs [all...] |
H A D | i8254xGBe.cc | 81 regs.ctrl.fd(1); 82 regs.ctrl.lrst(1); 83 regs.ctrl.speed(2); 84 regs.ctrl.frcspd(1); 85 regs.sts.speed(3); // Say we're 1000Mbps 86 regs.sts.fd(1); // full duplex 87 regs.sts.lu(1); // link up 88 regs.eecd.fwe(1); 89 regs.eecd.ee_type(1); 90 regs [all...] |
H A D | sinic.cc | 179 rxdone = set_RxDone_High(rxdone, rxFifo.size() > regs.RxFifoHigh); 181 regs.RxData = vnic.RxData; 182 regs.RxDone = rxdone; 183 regs.RxWait = rxdone; 188 txdone = set_TxDone_Full(txdone, txFifo.avail() < regs.TxMaxCopy); 189 txdone = set_TxDone_Low(txdone, txFifo.size() < regs.TxFifoLow); 190 regs.TxData = vnic.TxData; 191 regs.TxDone = txdone; 192 regs.TxWait = txdone; 202 regs [all...] |
H A D | i8254xGBe.hh | 63 iGbReg::Regs regs; member in class:IGbE 341 Addr descBase() const override { return igbe->regs.rdba(); } 342 long descHead() const override { return igbe->regs.rdh(); } 343 long descLen() const override { return igbe->regs.rdlen() >> 4; } 344 long descTail() const override { return igbe->regs.rdt(); } 345 void updateHead(long h) override { igbe->regs.rdh(h); } 402 Addr descBase() const override { return igbe->regs.tdba(); } 403 long descHead() const override { return igbe->regs.tdh(); } 404 long descTail() const override { return igbe->regs.tdt(); } 405 long descLen() const override { return igbe->regs [all...] |
/gem5/src/arch/arm/kvm/ |
H A D | base_cpu.cc | 133 std::unique_ptr<struct kvm_reg_list> regs; local 136 regs.reset((struct kvm_reg_list *)operator new(size)); 137 regs->n = regs_probe.n; 138 if (!getRegList(*regs)) 141 _regIndexList.assign(regs->reg, regs->reg + regs->n); 155 BaseArmKvmCPU::getRegList(struct kvm_reg_list ®s) const 157 if (ioctl(KVM_GET_REG_LIST, (void *)®s) == -1) {
|
H A D | base_cpu.hh | 101 * size is written to regs.n in this case). True on success. 103 bool getRegList(struct kvm_reg_list ®s) const;
|
/gem5/src/cpu/kvm/ |
H A D | x86_cpu.hh | 125 void getDebugRegisters(struct kvm_debugregs ®s) const; 126 void setDebugRegisters(const struct kvm_debugregs ®s); 127 void getXCRs(struct kvm_xcrs ®s) const; 128 void setXCRs(const struct kvm_xcrs ®s); 212 void updateThreadContextRegs(const struct kvm_regs ®s,
|
/gem5/src/arch/x86/ |
H A D | interrupts.hh | 56 #include "arch/x86/regs/apic.hh" 79 uint32_t regs[NUM_APIC_REGS]; member in class:X86ISA::Interrupts 131 if (regs[base + offset] != 0) { 132 return offset * 32 + findMsbSet(regs[base + offset]); 153 regs[base + (vector / 32)] |= (1 << (vector % 32)); 159 regs[base + (vector / 32)] &= ~(1 << (vector % 32)); 165 return bits(regs[base + (vector / 32)], vector % 32); 213 LVTEntry entry = regs[APIC_LVT_TIMER]; 242 regs[reg] = val;
|
H A D | interrupts.cc | 57 #include "arch/x86/regs/apic.hh" 215 uint32_t val = regs[reg]; 284 regs[APIC_ID] = (initialApicId << 24); 340 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 343 regs[APIC_INTERRUPT_COMMAND_LOW] = low; 386 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 393 divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]); 406 return regs[reg]; 454 regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1); 455 regs[APIC_INTERNAL_STAT [all...] |
/gem5/src/dev/x86/ |
H A D | cmos.cc | 95 val = regs[reg]; 113 regs[reg] = val; 127 SERIALIZE_ARRAY(regs, numRegs); 137 UNSERIALIZE_ARRAY(regs, numRegs);
|
H A D | cmos.hh | 51 uint8_t regs[numRegs]; member in class:X86ISA::Cmos 81 memset(regs, 0, numRegs * sizeof(uint8_t));
|
/gem5/util/statetrace/arch/i686/ |
H A D | tracechild.cc | 75 oldregs = regs; 76 if (ptrace(PTRACE_GETREGS, pid, 0, ®s) != 0) 92 return getRegs(regs, num);
|
/gem5/util/statetrace/arch/sparc/ |
H A D | tracechild.hh | 45 struct regs; 70 regs theregs; 71 regs oldregs;
|
/gem5/src/dev/pci/ |
H A D | copy_engine.cc | 66 // All Reg regs are initialized to 0 by default 67 regs.chanCount = p->ChanCnt; 68 regs.xferCap = findMsbSet(p->XferCap); 69 regs.attnStatus = 0; 71 if (regs.chanCount > 64) 74 for (int x = 0; x < regs.chanCount; x++) { 195 assert(size == sizeof(regs.chanCount)); 196 pkt->setLE<uint8_t>(regs.chanCount); 199 assert(size == sizeof(regs.xferCap)); 200 pkt->setLE<uint8_t>(regs [all...] |
/gem5/util/statetrace/arch/arm/ |
H A D | tracechild.cc | 59 memset(®s, 0, sizeof(regs)); 60 memset(&oldregs, 0, sizeof(regs)); 68 assert(sizeof(regs.uregs)/sizeof(regs.uregs[0]) > CPSR); 123 oldregs = regs; 124 if (ptrace(PTRACE_GETREGS, pid, 0, ®s) != 0) { 147 return getRegs(regs, num);
|