#
14252:1659a606447f |
|
06-Sep-2019 |
Gabe Black <gabeblack@google.com> |
dev: Scrub out some lingering uses of MemObject.
MemObject doesn't do anything any more, and is basically just an alias for ClockedObject.
Change-Id: Ic0e1658609e4e1d7f4b829fbc421f222e4869dee Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20719 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
|
#
14221:2954f631ee64 |
|
20-Aug-2019 |
Adrian Herrera <adrian.herrera@arm.com> |
dev-arm: Implement invalidateVA/VAA in SMMUv3 WalkCache
This patch implements VA/VAA invalidations in the SMMUv3 model.
As per SMMUv3.0 spec, if leaf bit is specified in the invalidation command, only leaf entries within the walk cache need to be invalidated, otherwise entries with intermediate translations are also invalidated.
Change-Id: I0eb1e1f1d8c00671a3c23d2a8fb756f2020d8d46 Reviewed-by: Michiel van Tol <michiel.vantol@arm.com> Reviewed-by: Marc Mari Barcelo <marc.maribarcelo@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20258 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
|
#
14132:d6093eeca3af |
|
25-Jul-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
dev-arm: Perform SMMUv3 CFG Invalidation at device interface
In the current SMMUv3 model, multiple micro/mainTLB are present at the device interface (SMMUv3SlaveInterface), caching translations specific to a device. Those distributed TLBs are checked for a translation before checking for centralized TLBs (shared by devices), like the configuration cache, walk cache etc. This means that if a hit in these TLBs occurs, there won't be a need to enter configuration stage (which is where the STE and CD are retrieved). So if we invalidate a cached configuration (in ConfigCache), we need to invalidate those interface TLB entries as well, otherwise in theory we will keep the same translation even after a change in configuration tables.
Change-Id: I4aa36ba8392a530267517bef7562318b282bee25 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel van Tol <michiel.vantol@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19813 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
|
#
14116:3868b8bdb52b |
|
23-Jul-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
dev-arm: Rewrite SMMUv3 Commands
This patch is rewriting the SMMUv3::processCommand method for the following reasons:
* Command names were not matching spec * Command encoding/opcode was wrong
The patch is not adding any new command: there is still a subset of unimplemented commands; those are:
* CMD_TLBI_EL3_ALL * CMD_TLBI_EL3_VA * CMD_TLBI_EL2_ALL * CMD_TLBI_EL2_VA * CMD_TLBI_EL2_VAA * CMD_TLBI_EL2_ASID
which require StreamWorld support, and
* CMD_ATC_INV * CMD_PRI_RESP * CMD_RESUME * CMD_STALL_TERM
which require in sequence: ATS, PRI, Stall Model support
Change-Id: Ia2dd47b5588738402d9584a00cfc88c94c253ad0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel van Tol <michiel.vantol@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19668 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
|
#
14103:1a8ac5412832 |
|
23-Jul-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
dev-arm: Polish SMMUv3 CMDQ setup
The patch is aiming to be spec compliant when it comes to setup the SMMU command queue (while CR0.CMDQEN = 0), in the following ways:
* Writes to CMDQ_CONS (read index) are allowed during initialization * Writes to CMDQ_BASE (cmdq pointer) are allowed during initialization
According to spec, If they happen when the command queue is in fuction (CR0.CMDQEN = 1), behaviour is constrained unpredictable, with the following options
1) The write is ignored 2) The register takes the value and it is unpredictable whether it affects the SMMU command queue internal state.
In the model/patch we go for option 1.
Change-Id: I1c55bc571a8b3a1c0b0a525e429ab7b1480544ff Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19633 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
|
#
14098:f4b9024d1a96 |
|
22-Jul-2019 |
Michiel Van Tol <michiel.vantol@arm.com> |
dev-arm: Add 16K granule support to SMMUv3 model
Added the necessary PageTableOps that match the 16K granule translation regime.
Change-Id: I46ef07939cb4bdc8c0bbbeeeb6a50a9ab0d64de0 Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19628 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
|
#
14064:870553bad072 |
|
18-Jun-2019 |
Adrian Herrera <adrian.herrera@arm.com> |
dev-arm: drain implementation for SMMUv3
SMMUv3 is drained when (1) no SMMU translations are pending on any of its slave interfaces and (2) no commands are stored in the Command Queue waiting to be processed.
Change-Id: I81cef5fd821fa5e509e130af02aece5239493df5 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19309 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
|
#
14039:4991b2a345a1 |
|
05-Mar-2019 |
Stanislaw Czerniawski <stacze01@arm.com> |
dev-arm: Implement a SMMUv3 model
This is an implementation of the SMMUv3 architecture.
What can it do? - Single-stage and nested translation with 4k or 64k granule. 16k would be straightforward to add. - Large pages are supported. - Works with any gem5 device as long as it is issuing packets with a valid (Sub)StreamId
What it can't do? - Fragment stage 1 page when the underlying stage 2 page is smaller. S1 page size > S2 page size is not supported - Invalidations take zero time. This wouldn't be hard to fix. - Checkpointing is not supported - Stall/resume for faulting transactions is not supported
Additional contributors: - Michiel W. van Tol <Michiel.VanTol@arm.com> - Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Ibc606fccd9199b2c1ba739c6335c846ffaa4d564 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19008 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
|