1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#include "dev/x86/cmos.hh" 32 33#include "debug/CMOS.hh" 34#include "dev/x86/intdev.hh" 35#include "mem/packet_access.hh" 36 37void 38X86ISA::Cmos::X86RTC::handleEvent() 39{ 40 for (auto *wire: intPin) { 41 wire->raise(); 42 //XXX This is a hack. 43 wire->lower(); 44 } 45} 46 47Tick 48X86ISA::Cmos::read(PacketPtr pkt) 49{ 50 assert(pkt->getSize() == 1); 51 switch(pkt->getAddr() - pioAddr) 52 { 53 case 0x0: 54 pkt->setLE(address); 55 break; 56 case 0x1: 57 pkt->setLE(readRegister(address)); 58 break; 59 default: 60 panic("Read from undefined CMOS port.\n"); 61 } 62 pkt->makeAtomicResponse(); 63 return latency; 64} 65 66Tick 67X86ISA::Cmos::write(PacketPtr pkt) 68{ 69 assert(pkt->getSize() == 1); 70 switch(pkt->getAddr() - pioAddr) 71 { 72 case 0x0: 73 address = pkt->getLE<uint8_t>(); 74 break; 75 case 0x1: 76 writeRegister(address, pkt->getLE<uint8_t>()); 77 break; 78 default: 79 panic("Write to undefined CMOS port.\n"); 80 } 81 pkt->makeAtomicResponse(); 82 return latency; 83} 84 85uint8_t 86X86ISA::Cmos::readRegister(uint8_t reg) 87{ 88 assert(reg < numRegs); 89 uint8_t val; 90 if (reg <= 0xD) { 91 val = rtc.readData(reg); 92 DPRINTF(CMOS, 93 "Reading CMOS RTC reg %x as %x.\n", reg, val); 94 } else { 95 val = regs[reg]; 96 DPRINTF(CMOS, 97 "Reading non-volitile CMOS address %x as %x.\n", reg, val); 98 } 99 return val; 100} 101 102void 103X86ISA::Cmos::writeRegister(uint8_t reg, uint8_t val) 104{ 105 assert(reg < numRegs); 106 if (reg <= 0xD) { 107 DPRINTF(CMOS, "Writing CMOS RTC reg %x with %x.\n", 108 reg, val); 109 rtc.writeData(reg, val); 110 } else { 111 DPRINTF(CMOS, "Writing non-volitile CMOS address %x with %x.\n", 112 reg, val); 113 regs[reg] = val; 114 } 115} 116 117void 118X86ISA::Cmos::startup() 119{ 120 rtc.startup(); 121} 122 123void 124X86ISA::Cmos::serialize(CheckpointOut &cp) const 125{ 126 SERIALIZE_SCALAR(address); 127 SERIALIZE_ARRAY(regs, numRegs); 128 129 // Serialize the timer 130 rtc.serialize("rtc", cp); 131} 132 133void 134X86ISA::Cmos::unserialize(CheckpointIn &cp) 135{ 136 UNSERIALIZE_SCALAR(address); 137 UNSERIALIZE_ARRAY(regs, numRegs); 138 139 // Serialize the timer 140 rtc.unserialize("rtc", cp); 141} 142 143X86ISA::Cmos * 144CmosParams::create() 145{ 146 return new X86ISA::Cmos(this); 147} 148