Lines Matching refs:regs
57 #include "arch/x86/regs/apic.hh"
215 uint32_t val = regs[reg];
284 regs[APIC_ID] = (initialApicId << 24);
340 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
343 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
386 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
393 divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
406 return regs[reg];
454 regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
455 regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
461 if (regs[APIC_INTERNAL_STATE] & 0x1) {
462 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
465 regs[APIC_INTERNAL_STATE] |= ULL(0x1);
473 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
480 InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
548 regs[APIC_INTERRUPT_COMMAND_LOW] = low;
550 newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
562 (regs[reg] & readOnlyMask);
570 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
594 regs[reg] = newVal;
612 memset(regs, 0, sizeof(regs));
614 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
634 bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
647 bits(regs[APIC_TASK_PRIORITY], 7, 4));
722 SERIALIZE_ARRAY(regs, NUM_APIC_REGS);
747 UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS);