dev/net/i8254xGBe.cc

81     regs.ctrl.fd(1);
82     regs.ctrl.lrst(1);
83     regs.ctrl.speed(2);
84     regs.ctrl.frcspd(1);
85     regs.sts.speed(3); // Say we're 1000Mbps
86     regs.sts.fd(1); // full duplex
87     regs.sts.lu(1); // link up
88     regs.eecd.fwe(1);
89     regs.eecd.ee_type(1);
90     regs.imr = 0;
91     regs.iam = 0;
92     regs.rxdctl.gran(1);
93     regs.rxdctl.wthresh(1);
94     regs.fcrth(1);
95     regs.tdwba = 0;
96     regs.rlpml = 0;
97     regs.sw_fw_sync = 0;
99     regs.pba.rxa(0x30);
100     regs.pba.txa(0x10);
193         pkt->setLE<uint32_t>(regs.ctrl());
196         pkt->setLE<uint32_t>(regs.sts());
199         pkt->setLE<uint32_t>(regs.eecd());
202         pkt->setLE<uint32_t>(regs.eerd());
205         pkt->setLE<uint32_t>(regs.ctrl_ext());
208         pkt->setLE<uint32_t>(regs.mdic());
212                 regs.icr(), regs.imr, regs.iam, regs.ctrl_ext.iame());
213         pkt->setLE<uint32_t>(regs.icr());
214         if (regs.icr.int_assert() || regs.imr == 0) {
215             regs.icr = regs.icr() & ~mask(30);
216             DPRINTF(Ethernet, "Cleared ICR. ICR=%#x\n", regs.icr());
218         if (regs.ctrl_ext.iame() && regs.icr.int_assert())
219             regs.imr &= ~regs.iam;
228         pkt->setLE<uint32_t>(regs.itr());
231         pkt->setLE<uint32_t>(regs.rctl());
234         pkt->setLE<uint32_t>(regs.fcttv());
237         pkt->setLE<uint32_t>(regs.tctl());
240         pkt->setLE<uint32_t>(regs.pba());
249         pkt->setLE<uint32_t>(regs.fcrtl());
252         pkt->setLE<uint32_t>(regs.fcrth());
255         pkt->setLE<uint32_t>(regs.rdba.rdbal());
258         pkt->setLE<uint32_t>(regs.rdba.rdbah());
261         pkt->setLE<uint32_t>(regs.rdlen());
264         pkt->setLE<uint32_t>(regs.srrctl());
267         pkt->setLE<uint32_t>(regs.rdh());
270         pkt->setLE<uint32_t>(regs.rdt());
273         pkt->setLE<uint32_t>(regs.rdtr());
274         if (regs.rdtr.fpd()) {
279             regs.rdtr.fpd(0);
283         pkt->setLE<uint32_t>(regs.rxdctl());
286         pkt->setLE<uint32_t>(regs.radv());
289         pkt->setLE<uint32_t>(regs.tdba.tdbal());
292         pkt->setLE<uint32_t>(regs.tdba.tdbah());
295         pkt->setLE<uint32_t>(regs.tdlen());
298         pkt->setLE<uint32_t>(regs.tdh());
301         pkt->setLE<uint32_t>(regs.txdca_ctl());
304         pkt->setLE<uint32_t>(regs.tdt());
307         pkt->setLE<uint32_t>(regs.tidv());
310         pkt->setLE<uint32_t>(regs.txdctl());
313         pkt->setLE<uint32_t>(regs.tadv());
316         pkt->setLE<uint32_t>(regs.tdwba & mask(32));
319         pkt->setLE<uint32_t>(regs.tdwba >> 32);
322         pkt->setLE<uint32_t>(regs.rxcsum());
325         pkt->setLE<uint32_t>(regs.rlpml);
328         pkt->setLE<uint32_t>(regs.rfctl());
331         pkt->setLE<uint32_t>(regs.manc());
334         pkt->setLE<uint32_t>(regs.swsm());
335         regs.swsm.smbi(1);
338         pkt->setLE<uint32_t>(regs.fwsm());
341         pkt->setLE<uint32_t>(regs.sw_fw_sync);
386         regs.ctrl = val;
387         if (regs.ctrl.tfce())
389         if (regs.ctrl.rfce())
393         regs.ctrl_ext = val;
396         regs.sts = val;
400         oldClk = regs.eecd.sk();
401         regs.eecd = val;
403         if (!oldClk && regs.eecd.sk()) {
405                 eeOpcode = eeOpcode << 1 | regs.eecd.din();
408                 eeAddr = eeAddr << 1 | regs.eecd.din();
415                 regs.eecd.dout((flash[eeAddr>>1] >> (15-eeDataBits)) & 0x1);
418                 regs.eecd.dout(0);
447         regs.eecd.ee_gnt(regs.eecd.ee_req());
450         regs.eerd = val;
451         if (regs.eerd.start()) {
452             regs.eerd.done(1);
453             assert(regs.eerd.addr() < EEPROM_SIZE);
454             regs.eerd.data(flash[regs.eerd.addr()]);
455             regs.eerd.start(0);
457                     regs.eerd.addr(), regs.eerd.data());
461         regs.mdic = val;
462         if (regs.mdic.i())
464         if (regs.mdic.phyadd() != 1)
467                 regs.mdic.op() == 1 ? "Writing" : "Reading",
468                 regs.mdic.regadd());
469         switch (regs.mdic.regadd()) {
471             regs.mdic.data(0x796D); // link up
474             regs.mdic.data(params()->phy_pid);
477             regs.mdic.data(params()->phy_epid);
480             regs.mdic.data(0x7C00);
483             regs.mdic.data(0x3000);
486             regs.mdic.data(0x180); // some random length
489             regs.mdic.data(0);
491         regs.mdic.r(1);
495                 regs.icr(), regs.imr, regs.iam, regs.ctrl_ext.iame());
496         if (regs.ctrl_ext.iame())
497             regs.imr &= ~regs.iam;
498         regs.icr = ~bits(val,30,0) & regs.icr();
502         regs.itr = val;
509         regs.imr |= val;
513         regs.imr &= ~val;
517         regs.iam = val;
520         oldrctl = regs.rctl;
521         regs.rctl = val;
522         if (regs.rctl.rst()) {
526             regs.rctl.rst(0);
528         if (regs.rctl.en())
533         regs.fcttv = val;
536         regs.tctl = val;
537         oldtctl = regs.tctl;
538         regs.tctl = val;
539         if (regs.tctl.en())
542         if (regs.tctl.en() && !oldtctl.en()) {
547         regs.pba.rxa(val);
548         regs.pba.txa(64 - regs.pba.rxa());
566         regs.fcrtl = val;
569         regs.fcrth = val;
572         regs.rdba.rdbal( val & ~mask(4));
576         regs.rdba.rdbah(val);
580         regs.rdlen = val & ~mask(7);
584         regs.srrctl = val;
587         regs.rdh = val;
591         regs.rdt = val;
601         regs.rdtr = val;
604         regs.radv = val;
607         regs.rxdctl = val;
610         regs.tdba.tdbal( val & ~mask(4));
614         regs.tdba.tdbah(val);
618         regs.tdlen = val & ~mask(7);
622         regs.tdh = val;
626         regs.txdca_ctl = val;
627         if (regs.txdca_ctl.enabled())
631         regs.tdt = val;
641         regs.tidv = val;
644         regs.txdctl = val;
647         regs.tadv = val;
650         regs.tdwba &= ~mask(32);
651         regs.tdwba |= val;
652         txDescCache.completionWriteback(regs.tdwba & ~mask(1),
653                                         regs.tdwba & mask(1));
656         regs.tdwba &= mask(32);
657         regs.tdwba |= (uint64_t)val << 32;
658         txDescCache.completionWriteback(regs.tdwba & ~mask(1),
659                                         regs.tdwba & mask(1));
662         regs.rxcsum = val;
665         regs.rlpml = val;
668         regs.rfctl = val;
669         if (regs.rfctl.exsten())
673         regs.manc = val;
676         regs.swsm = val;
677         if (regs.fwsm.eep_fw_semaphore())
678             regs.swsm.swesmbi(0);
681         regs.sw_fw_sync = val;
700     if (t & regs.icr() && !now)
703     regs.icr = regs.icr() | t;
705     Tick itr_interval = SimClock::Int::ns * 256 * regs.itr.interval();
708             curTick(), regs.itr.interval(), itr_interval);
710     if (regs.itr.interval() == 0 || now ||
740     if (!(regs.icr() & regs.imr)) {
753         regs.icr.rxt0(1);
757         regs.icr.rxt0(1);
761         regs.icr.txdw(1);
765         regs.icr.txdw(1);
769     regs.icr.int_assert(1);
771             regs.icr());
781     if (regs.icr.int_assert()) {
782         regs.icr.int_assert(0);
785                 regs.icr());
793     DPRINTF(Ethernet, "Checking interrupts icr: %#x imr: %#x\n", regs.icr(),
794             regs.imr);
796     if (!(regs.icr() & regs.imr)) {
800         if (regs.icr.int_assert())
804             regs.itr(), regs.itr.interval());
806     if (regs.icr() & regs.imr) {
807         if (regs.itr.interval() == 0)  {
813                 Tick t = curTick() + SimClock::Int::ns * 256 * regs.itr.interval();
1243     switch (igbe->regs.srrctl.desctype()) {
1248                 packet->length, igbe->regs.rctl.descSize());
1249         assert(packet->length < igbe->regs.rctl.descSize());
1257         buf_len = igbe->regs.rctl.lpe() ? igbe->regs.srrctl.bufLen() :
1258             igbe->regs.rctl.descSize();
1260                 packet->length, igbe->regs.srrctl(), buf_len);
1272         buf_len = igbe->regs.rctl.lpe() ? igbe->regs.srrctl.bufLen() :
1273             igbe->regs.rctl.descSize();
1274         hdr_len = igbe->regs.rctl.lpe() ? igbe->regs.srrctl.hdrLen() : 0;
1278                 igbe->regs.rctl.lpe(), packet->length, pkt_offset,
1279                 igbe->regs.srrctl(), desc->adv_read.hdr, hdr_len,
1333               igbe->regs.srrctl.desctype());
1348     uint16_t crcfixup = igbe->regs.rctl.secrc() ? 0 : 4 ;
1356     assert(igbe->regs.rxcsum.pcss() == 0);
1384         if (ip && igbe->regs.rxcsum.ipofld()) {
1396         if (tcp && igbe->regs.rxcsum.tuofld()) {
1410         if (udp && igbe->regs.rxcsum.tuofld()) {
1426     switch (igbe->regs.srrctl.desctype()) {
1438         if (igbe->regs.rxcsum.pcsd()) {
1452               igbe->regs.srrctl.desctype());
1462         if (igbe->regs.rdtr.delay()) {
1463             Tick delay = igbe->regs.rdtr.delay() * igbe->intClock();
1468         if (igbe->regs.radv.idv()) {
1469             Tick delay = igbe->regs.radv.idv() * igbe->intClock();
1477         if (!igbe->regs.rdtr.delay() && !igbe->regs.radv.idv()) {
1485         if (pktPtr->length <= igbe->regs.rsrpd.idv()) {
1913         if (igbe->regs.tidv.idv()) {
1914             Tick delay = igbe->regs.tidv.idv() * igbe->intClock();
1919         if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) {
1920             Tick delay = igbe->regs.tadv.idv() * igbe->intClock();
1950     if (igbe->regs.txdctl.wthresh() == 0) {
1954     } else if (!igbe->regs.txdctl.gran() && igbe->regs.txdctl.wthresh() <=
1959     } else if (igbe->regs.txdctl.wthresh() <= usedCache.size()) {
1976         descEnd = igbe->regs.tdh();
2135     if (!regs.tctl.en()) {
2161     if (regs.txdctl.lwthresh() &&
2162         txDescCache.descLeft() < (regs.txdctl.lwthresh() * 8)) {
2244     if (!regs.rctl.en()) {
2285     if (!regs.rctl.en()) {
2297                 descLeft, regs.rctl.rdmts(), regs.rdlen());
2300         int ratio = (1ULL << (regs.rctl.rdmts() + 1));
2301         if (descLeft * ratio <= regs.rdlen()) {
2319         assert(regs.rxdctl.gran());
2321         if (regs.rxdctl.wthresh() >= rxDescCache.descUsed()) {
2325             if (regs.rxdctl.wthresh() < (cacheBlockSize()>>4))
2326                 rxDescCache.writeback(regs.rxdctl.wthresh()-1);
2331         if ((rxDescCache.descUnused() < regs.rxdctl.pthresh()) &&
2333              regs.rxdctl.hthresh())) {
2483     regs.serialize(cp);
2534     regs.unserialize(cp);