1/*
2 * Copyright (c) 2014-2015 ARM Limited
3 * All rights reserved
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 *     http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 * Authors: Andreas Sandberg
18 */
19
20#include "mali_midgard.hh"
21
22#include "regutils.hh"
23
24namespace NoMali {
25
26MaliMidgard::MaliMidgard(unsigned gpuType,
27                         unsigned major, unsigned minor, unsigned status)
28    : MaliMidgard(GPU_ID_MAKE(gpuType, major, minor, status))
29{
30}
31
32MaliMidgard::MaliMidgard(uint32_t _gpuId)
33    : GPU(gpuControl, jobControl, mmu),
34      gpuControl(*this),
35      jobControl(*this),
36      mmu(*this),
37      gpuId(_gpuId)
38{
39}
40
41MaliMidgard::~MaliMidgard()
42{
43}
44
45void
46MaliMidgard::setupControlIdRegisters(RegVector &regs)
47{
48    regs[RegAddr(L2_FEATURES)] =
49        (0x07 << 24) |  // lg2 ext bus width
50        (0x13 << 16) |  // lg2 cache size
51        (0x02 << 8) |   // lg2 associativity
52        (0x06);         // lg2 line size
53
54    regs[RegAddr(TILER_FEATURES)] =
55        (0x8 << 8) |    // Maximum no active hierarchy levels
56        0x09;           // lg2 bin size
57
58    /* Coherent core group, but incoherent supergroup. 1 L2 slice. */
59    regs[RegAddr(MEM_FEATURES)] = 0x1;
60
61    regs[RegAddr(MMU_FEATURES)] = 0x2830;
62    regs[RegAddr(AS_PRESENT)] = 0xff;
63    regs[RegAddr(JS_PRESENT)] = 0x7;
64    regs[RegAddr(JS0_FEATURES)] = 0x20e;
65    regs[RegAddr(JS1_FEATURES)] = 0x1fe;
66    regs[RegAddr(JS2_FEATURES)] = 0x7e;
67
68    regs[RegAddr(TEXTURE_FEATURES_0)] = 0x00fe001e;
69    regs[RegAddr(TEXTURE_FEATURES_1)] = 0xffff;
70    regs[RegAddr(TEXTURE_FEATURES_2)] = 0x9f81ffff;
71
72    regs[RegAddr(THREAD_MAX_THREADS)] = 0x100;
73    regs[RegAddr(THREAD_MAX_WORKGROUP_SIZE)] = 0x100;
74    regs[RegAddr(THREAD_MAX_BARRIER_SIZE)] = 0x100;
75    regs[RegAddr(THREAD_FEATURES)] = 0x0a040400;
76
77    regs.set64(RegAddr(SHADER_PRESENT_LO), 0xf);
78    regs.set64(RegAddr(TILER_PRESENT_LO), 0x1);
79    regs.set64(RegAddr(L2_PRESENT_LO), 0x1);
80}
81
82void
83MaliMidgard::GPUControlSpec::reset()
84{
85    GPUControl::reset();
86
87    regs[RegAddr(GPU_ID)] = midgard.gpuId;
88
89    midgard.setupControlIdRegisters(regs);
90}
91
92};
93