dev/net/sinic.cc

179     rxdone = set_RxDone_High(rxdone, rxFifo.size() > regs.RxFifoHigh);
181     regs.RxData = vnic.RxData;
182     regs.RxDone = rxdone;
183     regs.RxWait = rxdone;
188     txdone = set_TxDone_Full(txdone, txFifo.avail() < regs.TxMaxCopy);
189     txdone = set_TxDone_Low(txdone, txFifo.size() < regs.TxFifoLow);
190     regs.TxData = vnic.TxData;
191     regs.TxDone = txdone;
192     regs.TxWait = txdone;
202     regs.RxStatus = set_RxStatus_Head(regs.RxStatus, head);
203     regs.RxStatus = set_RxStatus_Busy(regs.RxStatus, rxBusyCount);
204     regs.RxStatus = set_RxStatus_Mapped(regs.RxStatus, rxMappedCount);
205     regs.RxStatus = set_RxStatus_Dirty(regs.RxStatus, rxDirtyCount);
348         devIntrClear(regs.IntrStatus &
438     regs.IntrStatus |= interrupts;
442             interrupts, regs.IntrStatus, regs.IntrMask);
444     interrupts = regs.IntrStatus & regs.IntrMask;
474     regs.IntrStatus &= ~interrupts;
478             interrupts, regs.IntrStatus, regs.IntrMask);
480     if (!(regs.IntrStatus & regs.IntrMask))
487     if (regs.IntrMask == newmask)
490     regs.IntrMask = newmask;
494             regs.IntrStatus, regs.IntrMask, regs.IntrStatus & regs.IntrMask);
496     if (regs.IntrStatus & regs.IntrMask)
593     uint32_t changed = regs.Config ^ newconf;
597     regs.Config = newconf;
600         cpuIntrEnable = regs.Config & Regs::Config_IntEn;
602             if (regs.IntrStatus & regs.IntrMask)
610         txEnable = regs.Config & Regs::Config_TxEn;
616         rxEnable = regs.Config & Regs::Config_RxEn;
637     memset(&regs, 0, sizeof(regs));
639     regs.Config = 0;
641         regs.Config |= Config_RxThread;
643         regs.Config |= Config_TxThread;
645         regs.Config |= Config_RSS;
647         regs.Config |= Config_ZeroCopy;
649         regs.Config |= Config_DelayCopy;
651         regs.Config |= Config_Vaddr;
656     regs.IntrMask = Intr_Soft | Intr_RxHigh | Intr_RxPacket | Intr_TxLow;
657     regs.RxMaxCopy = params()->rx_max_copy;
658     regs.TxMaxCopy = params()->tx_max_copy;
659     regs.ZeroCopySize = params()->zero_copy_size;
660     regs.ZeroCopyMark = params()->zero_copy_threshold;
661     regs.VirtualCount = params()->virtual_count;
662     regs.RxMaxIntr = params()->rx_max_intr;
663     regs.RxFifoSize = params()->rx_fifo_size;
664     regs.TxFifoSize = params()->tx_fifo_size;
665     regs.RxFifoLow = params()->rx_fifo_low_mark;
666     regs.TxFifoLow = params()->tx_fifo_threshold;
667     regs.RxFifoHigh = params()->rx_fifo_threshold;
668     regs.TxFifoHigh = params()->tx_fifo_high_mark;
669     regs.HwAddr = params()->hardware_address;
671     if (regs.RxMaxCopy < regs.ZeroCopyMark)
674     if (regs.ZeroCopySize >= regs.ZeroCopyMark)
885         if ((Regs::get_Config_ZeroCopy(regs.Config) ||
886              Regs::get_Config_DelayCopy(regs.Config)) &&
888             if (rxDmaLen > regs.ZeroCopyMark)
889                 rxDmaLen = regs.ZeroCopySize;
946         if (rxFifo.size() < regs.RxFifoLow)
949         if (rxFifo.size() > regs.RxFifoHigh)
1029     if (txFifo.size() < regs.TxFifoLow)
1124         if (txFifo.avail() < regs.TxMaxCopy) {
1168     if (!Regs::get_Config_Filter(regs.Config))
1195     if (rxFifo.size() >= regs.RxFifoHigh)
1293     SERIALIZE_SCALAR(regs.Config);
1294     SERIALIZE_SCALAR(regs.IntrStatus);
1295     SERIALIZE_SCALAR(regs.IntrMask);
1296     SERIALIZE_SCALAR(regs.RxData);
1297     SERIALIZE_SCALAR(regs.TxData);
1398     UNSERIALIZE_SCALAR(regs.Config);
1399     UNSERIALIZE_SCALAR(regs.IntrStatus);
1400     UNSERIALIZE_SCALAR(regs.IntrMask);
1401     UNSERIALIZE_SCALAR(regs.RxData);
1402     UNSERIALIZE_SCALAR(regs.TxData);