/gem5/src/cpu/ |
H A D | intr_control.hh | 49 void clear(int cpu_id, int int_num, int index); 50 void post(int cpu_id, int int_num, int index); 53 clear(int int_num, int index = 0) argument 55 clear(0, int_num, index); 59 post(int int_num, int index = 0) argument 61 post(0, int_num, index);
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H A D | intr_control.cc | 50 IntrControl::post(int cpu_id, int int_num, int index) argument 52 DPRINTF(IntrControl, "post %d:%d (cpu %d)\n", int_num, index, cpu_id); 55 cpu->postInterrupt(tcvec[cpu_id]->threadId(), int_num, index); 59 IntrControl::clear(int cpu_id, int int_num, int index) argument 61 DPRINTF(IntrControl, "clear %d:%d (cpu %d)\n", int_num, index, cpu_id); 64 cpu->clearInterrupt(tcvec[cpu_id]->threadId(), int_num, index);
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H A D | intr_control_noisa.cc | 41 IntrControl::post(int cpu_id, int int_num, int index) argument 46 IntrControl::clear(int cpu_id, int int_num, int index) argument
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H A D | base.hh | 238 postInterrupt(ThreadID tid, int int_num, int index) argument 240 interrupts[tid]->post(int_num, index); 246 clearInterrupt(ThreadID tid, int int_num, int index) argument 248 interrupts[tid]->clear(int_num, index);
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/gem5/src/arch/mips/ |
H A D | interrupts.cc | 59 Interrupts::post(int int_num, ThreadContext* tc) argument 61 DPRINTF(Interrupt, "Interrupt %d posted\n", int_num); 62 if (int_num < 0 || int_num >= NumInterruptLevels) 63 panic("int_num out of bounds\n"); 66 intstatus |= 1 << int_num; 71 Interrupts::post(int int_num, int index) argument 77 Interrupts::clear(int int_num, ThreadContext* tc) argument 79 DPRINTF(Interrupt, "Interrupt %d cleared\n", int_num); 80 if (int_num < 89 clear(int int_num, int index) argument [all...] |
H A D | interrupts.hh | 68 // post(int int_num, int index) is responsible 74 void post(int int_num, ThreadContext *tc); 75 void post(int int_num, int index); 77 // clear(int int_num, int index) is responsible 83 void clear(int int_num, ThreadContext* tc); 84 void clear(int int_num, int index);
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/gem5/src/arch/sparc/ |
H A D | interrupts.hh | 102 post(int int_num, int index) argument 104 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 105 assert(int_num >= 0 && int_num < NumInterruptTypes); 108 interrupts[int_num] |= ULL(1) << index; 109 intStatus |= ULL(1) << int_num; 113 clear(int int_num, int index) argument 115 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 116 assert(int_num >= 0 && int_num < NumInterruptType 253 get_vec(int int_num) argument [all...] |
/gem5/src/arch/alpha/ |
H A D | interrupts.hh | 84 post(int int_num, int index) argument 86 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 88 if (int_num < 0 || int_num >= NumInterruptLevels) 89 panic("int_num out of bounds\n"); 92 panic("int_num out of bounds\n"); 94 interrupts[int_num] |= 1 << index; 95 intstatus |= (ULL(1) << int_num); 99 clear(int int_num, int index) argument 101 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, inde [all...] |
/gem5/src/arch/power/ |
H A D | interrupts.hh | 67 post(int int_num, int index) argument 73 clear(int int_num, int index) argument
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/gem5/src/dev/arm/ |
H A D | gic_v2.cc | 214 Addr int_num = daddr - GICD_IPRIORITYR.start(); 215 assert(int_num < INT_LINES_MAX); 217 int_num); 222 return getIntPriority(ctx, int_num); 224 assert((int_num + 1) < INT_LINES_MAX); 225 return (getIntPriority(ctx, int_num) | 226 getIntPriority(ctx, int_num+1) << 8); 228 assert((int_num + 3) < INT_LINES_MAX); 229 return (getIntPriority(ctx, int_num) | 230 getIntPriority(ctx, int_num [all...] |
H A D | base_gic.cc | 124 Platform *_platform, ThreadContext *tc, uint32_t int_num) 126 intNum(int_num) 149 Platform *_platform, uint32_t int_num) 150 : ArmInterruptPin(_platform, nullptr, int_num) 167 Platform *_platform, ThreadContext *tc, uint32_t int_num) 168 : ArmInterruptPin(_platform, tc, int_num) 123 ArmInterruptPin( Platform *_platform, ThreadContext *tc, uint32_t int_num) argument 148 ArmSPI( Platform *_platform, uint32_t int_num) argument 166 ArmPPI( Platform *_platform, ThreadContext *tc, uint32_t int_num) argument
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H A D | base_gic.hh | 179 uint32_t int_num); 225 ArmSPI(Platform *platform, uint32_t int_num); 236 ArmPPI(Platform *platform, ThreadContext *tc, uint32_t int_num);
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H A D | UFSHostDevice.py | 51 int_num = Param.UInt32("Interrupt number that connects to GIC") variable in class:UFSHostDevice
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H A D | amba_device.cc | 60 intNum(p->int_num), gic(p->gic), intDelay(p->int_delay) 69 pioDelay(p->pio_latency),intNum(p->int_num), gic(p->gic)
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H A D | RealView.py | 93 int_num = Param.UInt32("Interrupt number that connects to GIC") variable in class:AmbaIntDevice 104 int_num = Param.UInt32("Interrupt number that connects to GIC") variable in class:AmbaDmaDevice 357 int_num = Param.UInt32("Interrupt number that connects to GIC") variable in class:Pl011 363 0x1000, [int(self.int_num)]) 389 int_num = Param.UInt32("Interrrupt number that connects to GIC") variable in class:A9GlobalTimer 440 0x1000, [int(self.int_num)]) 457 0x1000, [int(self.int_num)]) 620 uart = Pl011(pio_addr=0x10009000, int_num=44) 630 global_timer = A9GlobalTimer(int_num=27, pio_addr=0x1f000200) 634 clcd = Pl111(pio_addr=0x10020000, int_num [all...] |
H A D | gic_v2.hh | 333 bool isGroup0(ContextID ctx, uint32_t int_num) { 334 const uint32_t group_reg = getIntGroup(ctx, intNumToWord(int_num)); 335 return !bits(group_reg, intNumToBit(int_num)); 348 bool isFiq(ContextID ctx, uint32_t int_num) { 349 const bool is_group0 = isGroup0(ctx, int_num); 421 void clearInt(ContextID ctx, uint32_t int_num);
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H A D | timer_a9global.hh | 127 Timer(std::string __name, A9GlobalTimer *parent, int int_num);
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H A D | timer_sp804.hh | 114 Timer(std::string __name, Sp804 *parent, int int_num, Tick clock);
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H A D | Gic.py | 65 def interruptCells(self, int_type, int_num, int_flag): 73 return [ int_type, int_num, int_flag ] 227 def interruptCells(self, int_type, int_num, int_flag): 237 prop[1] = int_num
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H A D | timer_a9global.cc | 54 global_timer(name() + ".globaltimer", this, p->int_num) 59 int int_num) 60 : _name(__name), parent(_parent), intNum(int_num), control(0x0), 58 Timer(std::string __name, A9GlobalTimer *_parent, int int_num) argument
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H A D | timer_sp804.cc | 57 Sp804::Timer::Timer(std::string __name, Sp804 *_parent, int int_num, Tick _clock) argument 58 : _name(__name), parent(_parent), intNum(int_num), clock(_clock), control(0x20),
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H A D | pl011.cc | 61 gic(p->gic), endOnEOT(p->end_on_eot), intNum(p->int_num),
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/gem5/src/arch/riscv/ |
H A D | interrupts.hh | 108 post(int int_num, int index) argument 110 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 111 ip[int_num] = true; 115 clear(int int_num, int index) argument 117 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 118 ip[int_num] = false;
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/gem5/src/arch/arm/ |
H A D | interrupts.hh | 90 post(int int_num, int index) argument 92 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 94 if (int_num < 0 || int_num >= NumInterruptTypes) 95 panic("int_num out of bounds\n"); 100 interrupts[int_num] = true; 101 intStatus |= ULL(1) << int_num; 105 clear(int int_num, int index) argument 107 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 109 if (int_num < [all...] |
/gem5/src/arch/x86/ |
H A D | interrupts.hh | 283 post(int int_num, int index) argument 289 clear(int int_num, int index) argument
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