17584SAli.Saidi@arm.com/* 27584SAli.Saidi@arm.com * Copyright (c) 2010 ARM Limited 37584SAli.Saidi@arm.com * All rights reserved 47584SAli.Saidi@arm.com * 57584SAli.Saidi@arm.com * The license below extends only to copyright in the software and shall 67584SAli.Saidi@arm.com * not be construed as granting a license to any other intellectual 77584SAli.Saidi@arm.com * property including but not limited to intellectual property relating 87584SAli.Saidi@arm.com * to a hardware implementation of the functionality of the software 97584SAli.Saidi@arm.com * licensed hereunder. You may use the software subject to the license 107584SAli.Saidi@arm.com * terms below provided that you ensure that this notice is replicated 117584SAli.Saidi@arm.com * unmodified and in its entirety in all distributions of the software, 127584SAli.Saidi@arm.com * modified or unmodified, in source code or in binary form. 137584SAli.Saidi@arm.com * 147584SAli.Saidi@arm.com * Redistribution and use in source and binary forms, with or without 157584SAli.Saidi@arm.com * modification, are permitted provided that the following conditions are 167584SAli.Saidi@arm.com * met: redistributions of source code must retain the above copyright 177584SAli.Saidi@arm.com * notice, this list of conditions and the following disclaimer; 187584SAli.Saidi@arm.com * redistributions in binary form must reproduce the above copyright 197584SAli.Saidi@arm.com * notice, this list of conditions and the following disclaimer in the 207584SAli.Saidi@arm.com * documentation and/or other materials provided with the distribution; 217584SAli.Saidi@arm.com * neither the name of the copyright holders nor the names of its 227584SAli.Saidi@arm.com * contributors may be used to endorse or promote products derived from 237584SAli.Saidi@arm.com * this software without specific prior written permission. 247584SAli.Saidi@arm.com * 257584SAli.Saidi@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267584SAli.Saidi@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277584SAli.Saidi@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287584SAli.Saidi@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297584SAli.Saidi@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307584SAli.Saidi@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317584SAli.Saidi@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327584SAli.Saidi@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337584SAli.Saidi@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347584SAli.Saidi@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357584SAli.Saidi@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367584SAli.Saidi@arm.com * 377584SAli.Saidi@arm.com * Authors: Ali Saidi 387584SAli.Saidi@arm.com */ 397584SAli.Saidi@arm.com 407584SAli.Saidi@arm.com#ifndef __DEV_ARM_SP804_HH__ 417584SAli.Saidi@arm.com#define __DEV_ARM_SP804_HH__ 427584SAli.Saidi@arm.com 437584SAli.Saidi@arm.com#include "dev/arm/amba_device.hh" 447584SAli.Saidi@arm.com#include "params/Sp804.hh" 457584SAli.Saidi@arm.com 467584SAli.Saidi@arm.com/** @file 477584SAli.Saidi@arm.com * This implements the dual Sp804 timer block 487584SAli.Saidi@arm.com */ 497584SAli.Saidi@arm.com 509525SAndreas.Sandberg@ARM.comclass BaseGic; 517584SAli.Saidi@arm.com 529806Sstever@gmail.comclass Sp804 : public AmbaPioDevice 537584SAli.Saidi@arm.com{ 547584SAli.Saidi@arm.com protected: 5510905Sandreas.sandberg@arm.com class Timer : public Serializable 567584SAli.Saidi@arm.com { 577584SAli.Saidi@arm.com 587584SAli.Saidi@arm.com public: 597584SAli.Saidi@arm.com enum { 607584SAli.Saidi@arm.com LoadReg = 0x00, 617584SAli.Saidi@arm.com CurrentReg = 0x04, 627584SAli.Saidi@arm.com ControlReg = 0x08, 637584SAli.Saidi@arm.com IntClear = 0x0C, 647584SAli.Saidi@arm.com RawISR = 0x10, 657584SAli.Saidi@arm.com MaskedISR = 0x14, 667584SAli.Saidi@arm.com BGLoad = 0x18, 677584SAli.Saidi@arm.com Size = 0x20 687584SAli.Saidi@arm.com }; 697584SAli.Saidi@arm.com 707584SAli.Saidi@arm.com BitUnion32(CTRL) 717584SAli.Saidi@arm.com Bitfield<0> oneShot; 727584SAli.Saidi@arm.com Bitfield<1> timerSize; 737584SAli.Saidi@arm.com Bitfield<3,2> timerPrescale; 747584SAli.Saidi@arm.com Bitfield<5> intEnable; 757584SAli.Saidi@arm.com Bitfield<6> timerMode; 767584SAli.Saidi@arm.com Bitfield<7> timerEnable; 777584SAli.Saidi@arm.com EndBitUnion(CTRL) 787584SAli.Saidi@arm.com 797584SAli.Saidi@arm.com protected: 807584SAli.Saidi@arm.com std::string _name; 817584SAli.Saidi@arm.com 827584SAli.Saidi@arm.com /** Pointer to parent class */ 837584SAli.Saidi@arm.com Sp804 *parent; 847584SAli.Saidi@arm.com 857584SAli.Saidi@arm.com /** Number of interrupt to cause/clear */ 869421Sandreas.hansson@arm.com const uint32_t intNum; 877584SAli.Saidi@arm.com 887584SAli.Saidi@arm.com /** Number of ticks in a clock input */ 899421Sandreas.hansson@arm.com const Tick clock; 907584SAli.Saidi@arm.com 917584SAli.Saidi@arm.com /** Control register as specified above */ 927584SAli.Saidi@arm.com CTRL control; 937584SAli.Saidi@arm.com 947584SAli.Saidi@arm.com /** If timer has caused an interrupt. This is irrespective of 957584SAli.Saidi@arm.com * interrupt enable */ 967584SAli.Saidi@arm.com bool rawInt; 977584SAli.Saidi@arm.com 987584SAli.Saidi@arm.com /** If an interrupt is currently pending. Logical and of CTRL.intEnable 997584SAli.Saidi@arm.com * and rawInt */ 1007584SAli.Saidi@arm.com bool pendingInt; 1017584SAli.Saidi@arm.com 1027584SAli.Saidi@arm.com /** Value to load into counter when periodic mode reaches 0 */ 1037584SAli.Saidi@arm.com uint32_t loadValue; 1047584SAli.Saidi@arm.com 1057584SAli.Saidi@arm.com /** Called when the counter reaches 0 */ 1067584SAli.Saidi@arm.com void counterAtZero(); 10712086Sspwilson2@wisc.edu EventFunctionWrapper zeroEvent; 1087584SAli.Saidi@arm.com 1097584SAli.Saidi@arm.com public: 1107584SAli.Saidi@arm.com /** Restart the counter ticking at val 1117584SAli.Saidi@arm.com * @param val the value to start at (pre-16 bit masking if en) */ 1127584SAli.Saidi@arm.com void restartCounter(uint32_t val); 1137584SAli.Saidi@arm.com 1147584SAli.Saidi@arm.com Timer(std::string __name, Sp804 *parent, int int_num, Tick clock); 1157584SAli.Saidi@arm.com 1167584SAli.Saidi@arm.com std::string name() const { return _name; } 1177584SAli.Saidi@arm.com 1187584SAli.Saidi@arm.com /** Handle read for a single timer */ 1197584SAli.Saidi@arm.com void read(PacketPtr pkt, Addr daddr); 1207584SAli.Saidi@arm.com 1217584SAli.Saidi@arm.com /** Handle write for a single timer */ 1227584SAli.Saidi@arm.com void write(PacketPtr pkt, Addr daddr); 1237733SAli.Saidi@ARM.com 12411168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 12511168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 1267584SAli.Saidi@arm.com }; 1277584SAli.Saidi@arm.com 1287584SAli.Saidi@arm.com /** Pointer to the GIC for causing an interrupt */ 1299525SAndreas.Sandberg@ARM.com BaseGic *gic; 1307584SAli.Saidi@arm.com 1317584SAli.Saidi@arm.com /** Timers that do the actual work */ 1327584SAli.Saidi@arm.com Timer timer0; 1337584SAli.Saidi@arm.com Timer timer1; 1347584SAli.Saidi@arm.com 1357584SAli.Saidi@arm.com public: 1367584SAli.Saidi@arm.com typedef Sp804Params Params; 1377584SAli.Saidi@arm.com const Params * 1387584SAli.Saidi@arm.com params() const 1397584SAli.Saidi@arm.com { 1407584SAli.Saidi@arm.com return dynamic_cast<const Params *>(_params); 1417584SAli.Saidi@arm.com } 1427584SAli.Saidi@arm.com /** 1437584SAli.Saidi@arm.com * The constructor for RealView just registers itself with the MMU. 1447584SAli.Saidi@arm.com * @param p params structure 1457584SAli.Saidi@arm.com */ 1467584SAli.Saidi@arm.com Sp804(Params *p); 1477584SAli.Saidi@arm.com 1487584SAli.Saidi@arm.com /** 1497584SAli.Saidi@arm.com * Handle a read to the device 1507584SAli.Saidi@arm.com * @param pkt The memory request. 1517584SAli.Saidi@arm.com * @param data Where to put the data. 1527584SAli.Saidi@arm.com */ 15311174Sandreas.hansson@arm.com Tick read(PacketPtr pkt) override; 1547584SAli.Saidi@arm.com 1557584SAli.Saidi@arm.com /** 1567584SAli.Saidi@arm.com * All writes are simply ignored. 1577584SAli.Saidi@arm.com * @param pkt The memory request. 1587584SAli.Saidi@arm.com * @param data the data 1597584SAli.Saidi@arm.com */ 16011174Sandreas.hansson@arm.com Tick write(PacketPtr pkt) override; 1617584SAli.Saidi@arm.com 1627584SAli.Saidi@arm.com 16311168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 16411168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 1657584SAli.Saidi@arm.com}; 1667584SAli.Saidi@arm.com 1677584SAli.Saidi@arm.com 1687584SAli.Saidi@arm.com#endif // __DEV_ARM_SP804_HH__ 1697584SAli.Saidi@arm.com 170