1/*
2 * Copyright (c) 2017 Gedare Bloom
3 * Copyright (c) 2010 ARM Limited
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are
17 * met: redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer;
19 * redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution;
22 * neither the name of the copyright holders nor the names of its
23 * contributors may be used to endorse or promote products derived from
24 * this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * Authors: Ali Saidi
39 *          Gedare Bloom
40 */
41
42#ifndef __DEV_ARM_GLOBAL_TIMER_HH__
43#define __DEV_ARM_GLOBAL_TIMER_HH__
44
45#include "dev/io_device.hh"
46#include "params/A9GlobalTimer.hh"
47
48/** @file
49 * This implements the Cortex A9-MPCore global timer from TRM rev r4p1.
50 * The global timer is an incrementing timer.
51 */
52
53class BaseGic;
54
55class A9GlobalTimer : public BasicPioDevice
56{
57  protected:
58    class Timer : public Serializable
59    {
60
61      public:
62        /* TODO: IntStatusReg, CmpValRegLow32, CmpValRegHigh32,
63         * and AutoIncrementReg are banked per-cpu. Some bits of
64         * ControlReg are also banked per-cpu, see below. */
65        enum {
66            CounterRegLow32  = 0x00,
67            CounterRegHigh32 = 0x04,
68            ControlReg       = 0x08,
69            IntStatusReg     = 0x0C,
70            CmpValRegLow32   = 0x10,
71            CmpValRegHigh32  = 0x14,
72            AutoIncrementReg = 0x18,
73            Size             = 0x1C
74        };
75
76        /* TODO: bits 1--3 are banked per-cpu */
77        BitUnion32(CTRL)
78            Bitfield<0>    enable;
79            Bitfield<1>    cmpEnable;
80            Bitfield<2>    intEnable;
81            Bitfield<3>    autoIncrement;
82            Bitfield<7,4>  reserved;
83            Bitfield<15,8> prescalar;
84        EndBitUnion(CTRL)
85
86      protected:
87        std::string _name;
88
89        /** Pointer to parent class */
90        A9GlobalTimer *parent;
91
92        /** Number of interrupt to cause/clear */
93        const uint32_t intNum;
94
95        /** Control register as specified above */
96        /* TODO: one per-cpu? */
97        CTRL control;
98
99        /** If timer has caused an interrupt. This is irrespective of
100         * interrupt enable */
101        /* TODO: one per-cpu */
102        bool rawInt;
103
104        /** If an interrupt is currently pending. Logical and of CTRL.intEnable
105         * and rawInt */
106        bool pendingInt;
107
108        /** Value of the comparator */
109        uint64_t cmpVal;
110
111        /** Value to add to comparator when counter reaches comparator */
112        /* TODO: one per-cpu */
113        uint32_t autoIncValue;
114
115        /** Called when the counter reaches the comparator */
116        void counterAtCmpVal();
117        EventWrapper<Timer, &Timer::counterAtCmpVal> cmpValEvent;
118
119      public:
120        /** Restart the counter ticking */
121        void restartCounter();
122        /**
123          * Convert a number of ticks into the time counter format
124          * @param ticks number of ticks
125          */
126        uint64_t getTimeCounterFromTicks(Tick ticks);
127        Timer(std::string __name, A9GlobalTimer *parent, int int_num);
128
129        std::string name() const { return _name; }
130
131        /** Handle read for a single timer */
132        void read(PacketPtr pkt, Addr daddr);
133
134        /** Handle write for a single timer */
135        void write(PacketPtr pkt, Addr daddr);
136
137        void serialize(CheckpointOut &cp) const override;
138        void unserialize(CheckpointIn &cp) override;
139    };
140
141    /** Pointer to the GIC for causing an interrupt */
142    BaseGic *gic;
143
144    /** Timer that does the actual work */
145    Timer global_timer;
146
147  public:
148    typedef A9GlobalTimerParams Params;
149    const Params *
150    params() const
151    {
152        return dynamic_cast<const Params *>(_params);
153    }
154    /**
155      * The constructor for RealView just registers itself with the MMU.
156      * @param p params structure
157      */
158    A9GlobalTimer(Params *p);
159
160    /**
161     * Handle a read to the device
162     * @param pkt The memory request.
163     * @return Returns latency of device read
164     */
165    Tick read(PacketPtr pkt) override;
166
167    /**
168     * Handle a write to the device.
169     * @param pkt The memory request.
170     * @return Returns latency of device write
171     */
172    Tick write(PacketPtr pkt) override;
173
174    void serialize(CheckpointOut &cp) const override;
175    void unserialize(CheckpointIn &cp) override;
176};
177
178#endif // __DEV_ARM_GLOBAL_TIMER_HH__
179