113996Sgiacomo.travaglini@arm.com# Copyright (c) 2012-2013, 2017-2019 ARM Limited 29525SAndreas.Sandberg@ARM.com# All rights reserved. 39525SAndreas.Sandberg@ARM.com# 49525SAndreas.Sandberg@ARM.com# The license below extends only to copyright in the software and shall 59525SAndreas.Sandberg@ARM.com# not be construed as granting a license to any other intellectual 69525SAndreas.Sandberg@ARM.com# property including but not limited to intellectual property relating 79525SAndreas.Sandberg@ARM.com# to a hardware implementation of the functionality of the software 89525SAndreas.Sandberg@ARM.com# licensed hereunder. You may use the software subject to the license 99525SAndreas.Sandberg@ARM.com# terms below provided that you ensure that this notice is replicated 109525SAndreas.Sandberg@ARM.com# unmodified and in its entirety in all distributions of the software, 119525SAndreas.Sandberg@ARM.com# modified or unmodified, in source code or in binary form. 129525SAndreas.Sandberg@ARM.com# 139525SAndreas.Sandberg@ARM.com# Redistribution and use in source and binary forms, with or without 149525SAndreas.Sandberg@ARM.com# modification, are permitted provided that the following conditions are 159525SAndreas.Sandberg@ARM.com# met: redistributions of source code must retain the above copyright 169525SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer; 179525SAndreas.Sandberg@ARM.com# redistributions in binary form must reproduce the above copyright 189525SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer in the 199525SAndreas.Sandberg@ARM.com# documentation and/or other materials provided with the distribution; 209525SAndreas.Sandberg@ARM.com# neither the name of the copyright holders nor the names of its 219525SAndreas.Sandberg@ARM.com# contributors may be used to endorse or promote products derived from 229525SAndreas.Sandberg@ARM.com# this software without specific prior written permission. 239525SAndreas.Sandberg@ARM.com# 249525SAndreas.Sandberg@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 259525SAndreas.Sandberg@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 269525SAndreas.Sandberg@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 279525SAndreas.Sandberg@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 289525SAndreas.Sandberg@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 299525SAndreas.Sandberg@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 309525SAndreas.Sandberg@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 319525SAndreas.Sandberg@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 329525SAndreas.Sandberg@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 339525SAndreas.Sandberg@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 349525SAndreas.Sandberg@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 359525SAndreas.Sandberg@ARM.com# 369525SAndreas.Sandberg@ARM.com# Authors: Andreas Sandberg 379525SAndreas.Sandberg@ARM.com 389525SAndreas.Sandberg@ARM.comfrom m5.params import * 399525SAndreas.Sandberg@ARM.comfrom m5.proxy import * 4013591Sciro.santilli@arm.comfrom m5.util.fdthelper import * 4110749Smatt.evans@arm.comfrom m5.SimObject import SimObject 429525SAndreas.Sandberg@ARM.com 4313996Sgiacomo.travaglini@arm.comfrom m5.objects.Device import PioDevice, BasicPioDevice 4413665Sandreas.sandberg@arm.comfrom m5.objects.Platform import Platform 459525SAndreas.Sandberg@ARM.com 469525SAndreas.Sandberg@ARM.comclass BaseGic(PioDevice): 479525SAndreas.Sandberg@ARM.com type = 'BaseGic' 489525SAndreas.Sandberg@ARM.com abstract = True 499525SAndreas.Sandberg@ARM.com cxx_header = "dev/arm/base_gic.hh" 509525SAndreas.Sandberg@ARM.com 5114152Sgiacomo.travaglini@arm.com # Used for DTB autogeneration 5214152Sgiacomo.travaglini@arm.com _state = FdtState(addr_cells=0, interrupt_cells=3) 5314152Sgiacomo.travaglini@arm.com 549525SAndreas.Sandberg@ARM.com platform = Param.Platform(Parent.any, "Platform this device is part of.") 559525SAndreas.Sandberg@ARM.com 5613505Sgiacomo.travaglini@arm.com gicd_iidr = Param.UInt32(0, 5713505Sgiacomo.travaglini@arm.com "Distributor Implementer Identification Register") 5813505Sgiacomo.travaglini@arm.com gicd_pidr = Param.UInt32(0, 5913505Sgiacomo.travaglini@arm.com "Peripheral Identification Register") 6013505Sgiacomo.travaglini@arm.com gicc_iidr = Param.UInt32(0, 6113505Sgiacomo.travaglini@arm.com "CPU Interface Identification Register") 6213505Sgiacomo.travaglini@arm.com gicv_iidr = Param.UInt32(0, 6313505Sgiacomo.travaglini@arm.com "VM CPU Interface Identification Register") 6413505Sgiacomo.travaglini@arm.com 6514152Sgiacomo.travaglini@arm.com def interruptCells(self, int_type, int_num, int_flag): 6614152Sgiacomo.travaglini@arm.com """ 6714152Sgiacomo.travaglini@arm.com Interupt cells generation helper: 6814152Sgiacomo.travaglini@arm.com Following specifications described in 6914152Sgiacomo.travaglini@arm.com 7014152Sgiacomo.travaglini@arm.com Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt 7114152Sgiacomo.travaglini@arm.com """ 7214152Sgiacomo.travaglini@arm.com assert self._state.interrupt_cells == 3 7314152Sgiacomo.travaglini@arm.com return [ int_type, int_num, int_flag ] 7414152Sgiacomo.travaglini@arm.com 7512739Sandreas.sandberg@arm.comclass ArmInterruptPin(SimObject): 7612739Sandreas.sandberg@arm.com type = 'ArmInterruptPin' 7712739Sandreas.sandberg@arm.com cxx_header = "dev/arm/base_gic.hh" 7812974Sgiacomo.travaglini@arm.com cxx_class = "ArmInterruptPinGen" 7912739Sandreas.sandberg@arm.com abstract = True 8012739Sandreas.sandberg@arm.com 8112739Sandreas.sandberg@arm.com platform = Param.Platform(Parent.any, "Platform with interrupt controller") 8212739Sandreas.sandberg@arm.com num = Param.UInt32("Interrupt number in GIC") 8312739Sandreas.sandberg@arm.com 8412739Sandreas.sandberg@arm.comclass ArmSPI(ArmInterruptPin): 8512739Sandreas.sandberg@arm.com type = 'ArmSPI' 8612739Sandreas.sandberg@arm.com cxx_header = "dev/arm/base_gic.hh" 8712974Sgiacomo.travaglini@arm.com cxx_class = "ArmSPIGen" 8812739Sandreas.sandberg@arm.com 8912739Sandreas.sandberg@arm.comclass ArmPPI(ArmInterruptPin): 9012739Sandreas.sandberg@arm.com type = 'ArmPPI' 9112739Sandreas.sandberg@arm.com cxx_header = "dev/arm/base_gic.hh" 9212974Sgiacomo.travaglini@arm.com cxx_class = "ArmPPIGen" 9312739Sandreas.sandberg@arm.com 9413014Sciro.santilli@arm.comclass GicV2(BaseGic): 9513014Sciro.santilli@arm.com type = 'GicV2' 9613014Sciro.santilli@arm.com cxx_header = "dev/arm/gic_v2.hh" 979525SAndreas.Sandberg@ARM.com 9813013Sciro.santilli@arm.com dist_addr = Param.Addr("Address for distributor") 9913013Sciro.santilli@arm.com cpu_addr = Param.Addr("Address for cpu") 10013013Sciro.santilli@arm.com cpu_size = Param.Addr(0x2000, "Size of cpu register bank") 1019525SAndreas.Sandberg@ARM.com dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor") 1029525SAndreas.Sandberg@ARM.com cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface") 1039525SAndreas.Sandberg@ARM.com int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU") 1049525SAndreas.Sandberg@ARM.com it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)") 10511652SCurtis.Dunham@arm.com gem5_extensions = Param.Bool(False, "Enable gem5 extensions") 10610749Smatt.evans@arm.com 10713505Sgiacomo.travaglini@arm.comclass Gic400(GicV2): 10813505Sgiacomo.travaglini@arm.com """ 10913505Sgiacomo.travaglini@arm.com As defined in: 11013505Sgiacomo.travaglini@arm.com "ARM Generic Interrupt Controller Architecture" version 2.0 11113505Sgiacomo.travaglini@arm.com "CoreLink GIC-400 Generic Interrupt Controller" revision r0p1 11213505Sgiacomo.travaglini@arm.com """ 11313505Sgiacomo.travaglini@arm.com gicd_pidr = 0x002bb490 11413505Sgiacomo.travaglini@arm.com gicd_iidr = 0x0200143B 11513505Sgiacomo.travaglini@arm.com gicc_iidr = 0x0202143B 11613505Sgiacomo.travaglini@arm.com 11713505Sgiacomo.travaglini@arm.com # gicv_iidr same as gicc_idr 11813505Sgiacomo.travaglini@arm.com gicv_iidr = gicc_iidr 11913505Sgiacomo.travaglini@arm.com 12010749Smatt.evans@arm.comclass Gicv2mFrame(SimObject): 12110749Smatt.evans@arm.com type = 'Gicv2mFrame' 12210749Smatt.evans@arm.com cxx_header = "dev/arm/gic_v2m.hh" 12310749Smatt.evans@arm.com spi_base = Param.UInt32(0x0, "Frame SPI base number"); 12410749Smatt.evans@arm.com spi_len = Param.UInt32(0x0, "Frame SPI total number"); 12510749Smatt.evans@arm.com addr = Param.Addr("Address for frame PIO") 12610749Smatt.evans@arm.com 12710749Smatt.evans@arm.comclass Gicv2m(PioDevice): 12810749Smatt.evans@arm.com type = 'Gicv2m' 12910749Smatt.evans@arm.com cxx_header = "dev/arm/gic_v2m.hh" 13010749Smatt.evans@arm.com 13110749Smatt.evans@arm.com pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 13210749Smatt.evans@arm.com gic = Param.BaseGic(Parent.any, "Gic on which to trigger interrupts") 13310749Smatt.evans@arm.com frames = VectorParam.Gicv2mFrame([], "Power of two number of frames") 13413504Sgiacomo.travaglini@arm.com 13513504Sgiacomo.travaglini@arm.comclass VGic(PioDevice): 13613504Sgiacomo.travaglini@arm.com type = 'VGic' 13713504Sgiacomo.travaglini@arm.com cxx_header = "dev/arm/vgic.hh" 13813504Sgiacomo.travaglini@arm.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 13913504Sgiacomo.travaglini@arm.com platform = Param.Platform(Parent.any, "Platform this device is part of.") 14013504Sgiacomo.travaglini@arm.com vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 14113504Sgiacomo.travaglini@arm.com hv_addr = Param.Addr(0, "Address for hv control") 14213504Sgiacomo.travaglini@arm.com pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 14313504Sgiacomo.travaglini@arm.com # The number of list registers is not currently configurable at runtime. 14413814Sgiacomo.travaglini@arm.com maint_int = Param.UInt32("HV maintenance interrupt number") 14513504Sgiacomo.travaglini@arm.com 14613505Sgiacomo.travaglini@arm.com # gicv_iidr same as gicc_idr 14713505Sgiacomo.travaglini@arm.com gicv_iidr = Param.UInt32(Self.gic.gicc_iidr, 14813505Sgiacomo.travaglini@arm.com "VM CPU Interface Identification Register") 14913505Sgiacomo.travaglini@arm.com 15013504Sgiacomo.travaglini@arm.com def generateDeviceTree(self, state): 15113504Sgiacomo.travaglini@arm.com gic = self.gic.unproxy(self) 15213504Sgiacomo.travaglini@arm.com 15313504Sgiacomo.travaglini@arm.com node = FdtNode("interrupt-controller") 15413504Sgiacomo.travaglini@arm.com node.appendCompatible(["gem5,gic", "arm,cortex-a15-gic", 15513504Sgiacomo.travaglini@arm.com "arm,cortex-a9-gic"]) 15614152Sgiacomo.travaglini@arm.com node.append(gic._state.interruptCellsProperty()) 15714152Sgiacomo.travaglini@arm.com node.append(gic._state.addrCellsProperty()) 15813504Sgiacomo.travaglini@arm.com node.append(FdtProperty("interrupt-controller")) 15913504Sgiacomo.travaglini@arm.com 16013504Sgiacomo.travaglini@arm.com regs = ( 16113504Sgiacomo.travaglini@arm.com state.addrCells(gic.dist_addr) + 16213504Sgiacomo.travaglini@arm.com state.sizeCells(0x1000) + 16313504Sgiacomo.travaglini@arm.com state.addrCells(gic.cpu_addr) + 16413504Sgiacomo.travaglini@arm.com state.sizeCells(0x1000) + 16513504Sgiacomo.travaglini@arm.com state.addrCells(self.hv_addr) + 16613504Sgiacomo.travaglini@arm.com state.sizeCells(0x2000) + 16713504Sgiacomo.travaglini@arm.com state.addrCells(self.vcpu_addr) + 16813504Sgiacomo.travaglini@arm.com state.sizeCells(0x2000) ) 16913504Sgiacomo.travaglini@arm.com 17013504Sgiacomo.travaglini@arm.com node.append(FdtPropertyWords("reg", regs)) 17113504Sgiacomo.travaglini@arm.com node.append(FdtPropertyWords("interrupts", 17213814Sgiacomo.travaglini@arm.com [1, int(self.maint_int)-16, 0xf04])) 17313504Sgiacomo.travaglini@arm.com 17413504Sgiacomo.travaglini@arm.com node.appendPhandle(gic) 17513504Sgiacomo.travaglini@arm.com 17613504Sgiacomo.travaglini@arm.com yield node 17713531Sjairo.balart@metempsy.com 17813996Sgiacomo.travaglini@arm.comclass Gicv3Its(BasicPioDevice): 17913996Sgiacomo.travaglini@arm.com type = 'Gicv3Its' 18013996Sgiacomo.travaglini@arm.com cxx_header = "dev/arm/gic_v3_its.hh" 18113996Sgiacomo.travaglini@arm.com 18213996Sgiacomo.travaglini@arm.com dma = MasterPort("DMA port") 18313996Sgiacomo.travaglini@arm.com pio_size = Param.Unsigned(0x20000, "Gicv3Its pio size") 18413996Sgiacomo.travaglini@arm.com 18513996Sgiacomo.travaglini@arm.com # CIL [36] = 0: ITS supports 16-bit CollectionID 18613996Sgiacomo.travaglini@arm.com # Devbits [17:13] = 0b100011: ITS supports 23 DeviceID bits 18713996Sgiacomo.travaglini@arm.com # ID_bits [12:8] = 0b11111: ITS supports 31 EventID bits 18813996Sgiacomo.travaglini@arm.com gits_typer = Param.UInt64(0x30023F01, "GITS_TYPER RO value") 18913996Sgiacomo.travaglini@arm.com 19014226Sadrian.herrera@arm.com def generateDeviceTree(self, state): 19114226Sadrian.herrera@arm.com node = self.generateBasicPioDeviceNode(state, "gic-its", self.pio_addr, 19214226Sadrian.herrera@arm.com self.pio_size) 19314226Sadrian.herrera@arm.com node.appendCompatible(["arm,gic-v3-its"]) 19414226Sadrian.herrera@arm.com node.append(FdtProperty("msi-controller")) 19514226Sadrian.herrera@arm.com node.append(FdtPropertyWords("#msi-cells", [1])) 19614226Sadrian.herrera@arm.com 19714226Sadrian.herrera@arm.com return node 19814226Sadrian.herrera@arm.com 19913531Sjairo.balart@metempsy.comclass Gicv3(BaseGic): 20013531Sjairo.balart@metempsy.com type = 'Gicv3' 20113531Sjairo.balart@metempsy.com cxx_header = "dev/arm/gic_v3.hh" 20213531Sjairo.balart@metempsy.com 20314152Sgiacomo.travaglini@arm.com # Used for DTB autogeneration 20414154Sgiacomo.travaglini@arm.com _state = FdtState(addr_cells=2, size_cells=2, interrupt_cells=3) 20514152Sgiacomo.travaglini@arm.com 20613996Sgiacomo.travaglini@arm.com its = Param.Gicv3Its(Gicv3Its(), "GICv3 Interrupt Translation Service") 20713996Sgiacomo.travaglini@arm.com 20813880Sgiacomo.travaglini@arm.com dist_addr = Param.Addr("Address for distributor") 20913531Sjairo.balart@metempsy.com dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor") 21013880Sgiacomo.travaglini@arm.com redist_addr = Param.Addr("Address for redistributors") 21113531Sjairo.balart@metempsy.com redist_pio_delay = Param.Latency('10ns', 21213531Sjairo.balart@metempsy.com "Delay for PIO r/w to redistributors") 21313531Sjairo.balart@metempsy.com it_lines = Param.UInt32(1020, 21413531Sjairo.balart@metempsy.com "Number of interrupt lines supported (max = 1020)") 21513826Sgiacomo.travaglini@arm.com 21613826Sgiacomo.travaglini@arm.com maint_int = Param.ArmInterruptPin( 21713826Sgiacomo.travaglini@arm.com "HV maintenance interrupt." 21813826Sgiacomo.travaglini@arm.com "ARM strongly recommends that maintenance interrupts " 21913826Sgiacomo.travaglini@arm.com "are configured to use INTID 25 (PPI Interrupt).") 22013877Sgiacomo.travaglini@arm.com 22113877Sgiacomo.travaglini@arm.com cpu_max = Param.Unsigned(256, 22213877Sgiacomo.travaglini@arm.com "Maximum number of PE. This is affecting the maximum number of " 22313877Sgiacomo.travaglini@arm.com "redistributors") 22413878Sgiacomo.travaglini@arm.com 22513878Sgiacomo.travaglini@arm.com gicv4 = Param.Bool(True, "GICv4 extension available") 22614154Sgiacomo.travaglini@arm.com 22714154Sgiacomo.travaglini@arm.com def interruptCells(self, int_type, int_num, int_flag): 22814154Sgiacomo.travaglini@arm.com """ 22914154Sgiacomo.travaglini@arm.com Interupt cells generation helper: 23014154Sgiacomo.travaglini@arm.com Following specifications described in 23114154Sgiacomo.travaglini@arm.com 23214154Sgiacomo.travaglini@arm.com Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt 23314154Sgiacomo.travaglini@arm.com """ 23414154Sgiacomo.travaglini@arm.com prop = self._state.interruptCells(0) 23514154Sgiacomo.travaglini@arm.com assert len(prop) >= 3 23614154Sgiacomo.travaglini@arm.com prop[0] = int_type 23714154Sgiacomo.travaglini@arm.com prop[1] = int_num 23814154Sgiacomo.travaglini@arm.com prop[2] = int_flag 23914154Sgiacomo.travaglini@arm.com return prop 24014154Sgiacomo.travaglini@arm.com 24114154Sgiacomo.travaglini@arm.com def generateDeviceTree(self, state): 24214154Sgiacomo.travaglini@arm.com node = FdtNode("interrupt-controller") 24314154Sgiacomo.travaglini@arm.com node.appendCompatible(["arm,gic-v3"]) 24414154Sgiacomo.travaglini@arm.com node.append(self._state.interruptCellsProperty()) 24514154Sgiacomo.travaglini@arm.com node.append(self._state.addrCellsProperty()) 24614154Sgiacomo.travaglini@arm.com node.append(self._state.sizeCellsProperty()) 24714179Sadrian.herrera@arm.com node.append(FdtProperty("ranges")) 24814154Sgiacomo.travaglini@arm.com node.append(FdtProperty("interrupt-controller")) 24914154Sgiacomo.travaglini@arm.com 25014173Sgiacomo.travaglini@arm.com redist_stride = 0x40000 if self.gicv4 else 0x20000 25114173Sgiacomo.travaglini@arm.com node.append(FdtPropertyWords("redistributor-stride", 25214173Sgiacomo.travaglini@arm.com state.sizeCells(redist_stride))) 25314173Sgiacomo.travaglini@arm.com 25414154Sgiacomo.travaglini@arm.com regs = ( 25514154Sgiacomo.travaglini@arm.com state.addrCells(self.dist_addr) + 25614154Sgiacomo.travaglini@arm.com state.sizeCells(0x10000) + 25714154Sgiacomo.travaglini@arm.com state.addrCells(self.redist_addr) + 25814154Sgiacomo.travaglini@arm.com state.sizeCells(0x2000000) ) 25914154Sgiacomo.travaglini@arm.com 26014154Sgiacomo.travaglini@arm.com node.append(FdtPropertyWords("reg", regs)) 26114154Sgiacomo.travaglini@arm.com node.append(FdtPropertyWords("interrupts", 26214154Sgiacomo.travaglini@arm.com self.interruptCells(1, int(self.maint_int.num)-16, 0xf04))) 26314154Sgiacomo.travaglini@arm.com 26414154Sgiacomo.travaglini@arm.com node.appendPhandle(self) 26514154Sgiacomo.travaglini@arm.com 26614226Sadrian.herrera@arm.com # Generate the ITS device tree 26714226Sadrian.herrera@arm.com node.append(self.its.generateDeviceTree(self._state)) 26814226Sadrian.herrera@arm.com 26914154Sgiacomo.travaglini@arm.com yield node 270