Searched refs:icache_port (Results 1 - 18 of 18) sorted by relevance

/gem5/configs/example/
H A Dhmc_hello.py64 system.cpu.icache_port = system.membus.slave
H A Dse.py264 system.cpu[i].icache_port = ruby_port.slave
H A Dapu_se.py459 system.cpu[i].icache_port = ruby_port.slave
504 system.cpu[cp_idx].icache_port = \
H A Dfs.py171 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
/gem5/tests/gem5/cpu_tests/
H A Drun.py63 self.cpu_side = cpu.icache_port
137 system.cpu.icache_port = system.membus.slave
/gem5/util/tlm/conf/
H A Dtlm_elastic_slave.py95 system.cpu.icache.cpu_side = system.cpu.icache_port
/gem5/util/tlm/examples/
H A Dtlm_elastic_slave_with_l2.py102 system.cpu.icache.cpu_side = system.cpu.icache_port
/gem5/configs/learning_gem5/part1/
H A Dcaches.py91 self.cpu_side = cpu.icache_port
H A Dsimple.py68 system.cpu.icache_port = system.membus.slave
/gem5/configs/learning_gem5/part2/
H A Dsimple_cache.py68 system.cpu.icache_port = system.cache.cpu_side
H A Dsimple_memobj.py63 system.cpu.icache_port = system.memobj.inst_port
/gem5/tests/configs/
H A Dpc-simple-timing-ruby.py83 cpu.icache_port = system.ruby._cpu_ports[i].slave
/gem5/src/cpu/checker/
H A Dcpu.cc122 CheckerCPU::setIcachePort(MasterPort *icache_port) argument
124 icachePort = icache_port;
H A Dcpu.hh104 void setIcachePort(MasterPort *icache_port);
/gem5/src/cpu/
H A DBaseCPU.py212 icache_port = MasterPort("Instruction Port") variable in class:BaseCPU
214 _cached_ports = ['icache_port', 'dcache_port']
248 self.icache_port = ic.cpu_side
/gem5/configs/learning_gem5/part3/
H A Dmsi_caches.py110 cpu.icache_port = self.sequencers[i].slave
H A Druby_caches_MI_example.py108 cpu.icache_port = self.sequencers[i].slave
/gem5/configs/splash2/
H A Dcluster.py236 cpu.icache_port = cluster.clusterbus.slave

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