Searched refs:dcache_port (Results 1 - 20 of 20) sorted by relevance

/gem5/configs/example/
H A Dhmc_hello.py65 system.cpu.dcache_port = system.membus.slave
H A Dse.py265 system.cpu[i].dcache_port = ruby_port.slave
H A Dapu_se.py460 system.cpu[i].dcache_port = ruby_port.slave
502 system.cpu[cp_idx].dcache_port = \
H A Dfs.py172 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
/gem5/tests/gem5/cpu_tests/
H A Drun.py73 self.cpu_side = cpu.dcache_port
138 system.cpu.dcache_port = system.membus.slave
/gem5/util/tlm/conf/
H A Dtlm_elastic_slave.py96 system.cpu.dcache.cpu_side = system.cpu.dcache_port
/gem5/util/tlm/examples/
H A Dtlm_elastic_slave_with_l2.py103 system.cpu.dcache.cpu_side = system.cpu.dcache_port
/gem5/configs/learning_gem5/part1/
H A Dcaches.py110 self.cpu_side = cpu.dcache_port
H A Dsimple.py69 system.cpu.dcache_port = system.membus.slave
/gem5/configs/learning_gem5/part2/
H A Dsimple_cache.py69 system.cpu.dcache_port = system.cache.cpu_side
H A Dsimple_memobj.py64 system.cpu.dcache_port = system.memobj.data_port
/gem5/tests/configs/
H A Dpc-simple-timing-ruby.py84 cpu.dcache_port = system.ruby._cpu_ports[i].slave
/gem5/src/cpu/checker/
H A Dcpu.cc128 CheckerCPU::setDcachePort(MasterPort *dcache_port) argument
130 dcachePort = dcache_port;
H A Dcpu.hh106 void setDcachePort(MasterPort *dcache_port);
/gem5/src/cpu/
H A DBaseCPU.py213 dcache_port = MasterPort("Data Port") variable in class:BaseCPU
214 _cached_ports = ['icache_port', 'dcache_port']
249 self.dcache_port = dc.cpu_side
/gem5/configs/learning_gem5/part3/
H A Dmsi_caches.py111 cpu.dcache_port = self.sequencers[i].slave
H A Druby_caches_MI_example.py109 cpu.dcache_port = self.sequencers[i].slave
/gem5/configs/splash2/
H A Dcluster.py237 cpu.dcache_port = cluster.clusterbus.slave
/gem5/src/cpu/o3/
H A Dlsq_unit_impl.hh251 LSQUnit<Impl>::setDcachePort(MasterPort *dcache_port) argument
253 dcachePort = dcache_port;
H A Dlsq_unit.hh237 void setDcachePort(MasterPort *dcache_port);

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