| /gem5/src/cpu/simple/ |
| H A D | timing.hh | 115 FetchTranslation(TimingSimpleCPU *_cpu) argument
116 : cpu(_cpu)
164 TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu) argument
165 : MasterPort(_name, _cpu), cpu(_cpu),
178 TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {} argument
190 IcachePort(TimingSimpleCPU *_cpu) argument
191 : TimingCPUPort(_cpu->name() + ".icache_port", _cpu),
204 ITickEvent(TimingSimpleCPU *_cpu) argument
218 DcachePort(TimingSimpleCPU *_cpu) argument
244 DTickEvent(TimingSimpleCPU *_cpu) argument
[all...] |
| H A D | atomic.hh | 119 AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu) argument
120 : MasterPort(_name, _cpu)
142 AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu) argument
143 : AtomicCPUPort(_name, _cpu), cpu(_cpu)
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| H A D | exec_context.hh | 171 SimpleExecContext(BaseSimpleCPU* _cpu, SimpleThread* _thread) argument
172 : cpu(_cpu), thread(_thread), fetchOffset(0), stayAtPC(false),
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| /gem5/src/arch/power/ |
| H A D | interrupts.hh | 61 setCPU(BaseCPU * _cpu) argument
63 cpu = _cpu;
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| /gem5/src/cpu/o3/ |
| H A D | thread_state.hh | 91 O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process) argument
92 : ThreadState(_cpu, _thread_num, _process),
93 cpu(_cpu), noSquashFromTC(false), trapPending(false),
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| H A D | fetch.hh | 101 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) argument
102 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
223 DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
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| H A D | decode.hh | 102 DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params);
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| H A D | rob.hh | 88 * @param _cpu The cpu object pointer.
91 ROB(O3CPU *_cpu, DerivO3CPUParams *params);
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| H A D | lsq.hh | 134 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) argument
135 : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq),
136 cpu(_cpu)
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| H A D | rob_impl.hh | 58 ROB<Impl>::ROB(O3CPU *_cpu, DerivO3CPUParams *params) argument
60 cpu(_cpu),
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| H A D | commit.hh | 144 DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params);
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| H A D | iew.hh | 136 DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params);
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| H A D | rename.hh | 133 DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params);
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| H A D | decode_impl.hh | 62 DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params) argument
63 : cpu(_cpu),
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| /gem5/src/arch/mips/ |
| H A D | interrupts.hh | 65 setCPU(BaseCPU *_cpu) argument
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| /gem5/src/cpu/ |
| H A D | simple_thread.cc | 76 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, argument
79 : ThreadState(_cpu, _thread_num, _process), isa(_isa),
87 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, argument
90 : ThreadState(_cpu, _thread_num, NULL), isa(_isa),
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| H A D | base.hh | 97 CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
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| H A D | simple_thread.hh | 138 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
142 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
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| /gem5/src/cpu/trace/ |
| H A D | trace_cpu.hh | 232 IcachePort(TraceCPU* _cpu) argument
233 : MasterPort(_cpu->name() + ".icache_port", _cpu),
234 owner(_cpu)
273 DcachePort(TraceCPU* _cpu) argument
274 : MasterPort(_cpu->name() + ".dcache_port", _cpu),
275 owner(_cpu)
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| /gem5/src/arch/riscv/ |
| H A D | interrupts.hh | 72 void setCPU(BaseCPU * _cpu) { cpu = _cpu; } argument
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| /gem5/src/arch/alpha/ |
| H A D | interrupts.hh | 78 setCPU(BaseCPU * _cpu) argument
80 cpu = _cpu;
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| /gem5/src/arch/sparc/ |
| H A D | interrupts.hh | 69 setCPU(BaseCPU * _cpu) argument
71 cpu = _cpu;
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| /gem5/src/cpu/kvm/ |
| H A D | base.hh | 583 KVMCpuPort(const std::string &_name, BaseKvmCPU *_cpu) argument
584 : MasterPort(_name, _cpu), cpu(_cpu), activeMMIOReqs(0)
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| /gem5/src/arch/arm/ |
| H A D | interrupts.hh | 70 setCPU(BaseCPU * _cpu) argument
72 cpu = _cpu;
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| /gem5/src/dev/arm/ |
| H A D | generic_timer.hh | 286 GenericTimerISA(GenericTimer &_parent, unsigned _cpu) argument
287 : parent(_parent), cpu(_cpu) {}
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