110037SARM gem5 Developers/* 212971Sandreas.sandberg@arm.com * Copyright (c) 2013, 2015, 2017-2018 ARM Limited 310037SARM gem5 Developers * All rights reserved. 410037SARM gem5 Developers * 510037SARM gem5 Developers * The license below extends only to copyright in the software and shall 610037SARM gem5 Developers * not be construed as granting a license to any other intellectual 710037SARM gem5 Developers * property including but not limited to intellectual property relating 810037SARM gem5 Developers * to a hardware implementation of the functionality of the software 910037SARM gem5 Developers * licensed hereunder. You may use the software subject to the license 1010037SARM gem5 Developers * terms below provided that you ensure that this notice is replicated 1110037SARM gem5 Developers * unmodified and in its entirety in all distributions of the software, 1210037SARM gem5 Developers * modified or unmodified, in source code or in binary form. 1310037SARM gem5 Developers * 1410037SARM gem5 Developers * Redistribution and use in source and binary forms, with or without 1510037SARM gem5 Developers * modification, are permitted provided that the following conditions are 1610037SARM gem5 Developers * met: redistributions of source code must retain the above copyright 1710037SARM gem5 Developers * notice, this list of conditions and the following disclaimer; 1810037SARM gem5 Developers * redistributions in binary form must reproduce the above copyright 1910037SARM gem5 Developers * notice, this list of conditions and the following disclaimer in the 2010037SARM gem5 Developers * documentation and/or other materials provided with the distribution; 2110037SARM gem5 Developers * neither the name of the copyright holders nor the names of its 2210037SARM gem5 Developers * contributors may be used to endorse or promote products derived from 2310037SARM gem5 Developers * this software without specific prior written permission. 2410037SARM gem5 Developers * 2510037SARM gem5 Developers * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610037SARM gem5 Developers * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710037SARM gem5 Developers * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810037SARM gem5 Developers * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910037SARM gem5 Developers * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010037SARM gem5 Developers * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110037SARM gem5 Developers * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210037SARM gem5 Developers * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310037SARM gem5 Developers * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410037SARM gem5 Developers * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510037SARM gem5 Developers * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610037SARM gem5 Developers * 3710037SARM gem5 Developers * Authors: Giacomo Gabrielli 3810844Sandreas.sandberg@arm.com * Andreas Sandberg 3910037SARM gem5 Developers */ 4010037SARM gem5 Developers 4110037SARM gem5 Developers#ifndef __DEV_ARM_GENERIC_TIMER_HH__ 4210037SARM gem5 Developers#define __DEV_ARM_GENERIC_TIMER_HH__ 4310037SARM gem5 Developers 4410844Sandreas.sandberg@arm.com#include "arch/arm/isa_device.hh" 4512102SCurtis.Dunham@arm.com#include "arch/arm/system.hh" 4610037SARM gem5 Developers#include "base/bitunion.hh" 4710844Sandreas.sandberg@arm.com#include "dev/arm/base_gic.hh" 4810037SARM gem5 Developers#include "sim/core.hh" 4910037SARM gem5 Developers#include "sim/sim_object.hh" 5010037SARM gem5 Developers 5110037SARM gem5 Developers/// @file 5210037SARM gem5 Developers/// This module implements the global system counter and the local per-CPU 5310037SARM gem5 Developers/// architected timers as specified by the ARM Generic Timer extension (ARM 5410037SARM gem5 Developers/// ARM, Issue C, Chapter 17). 5510037SARM gem5 Developers 5610037SARM gem5 Developersclass Checkpoint; 5710844Sandreas.sandberg@arm.comclass GenericTimerParams; 5810847Sandreas.sandberg@arm.comclass GenericTimerMemParams; 5910037SARM gem5 Developers 6010844Sandreas.sandberg@arm.com/// Global system counter. It is shared by the architected timers. 6110844Sandreas.sandberg@arm.com/// @todo: implement memory-mapped controls 6210905Sandreas.sandberg@arm.comclass SystemCounter : public Serializable 6310844Sandreas.sandberg@arm.com{ 6410844Sandreas.sandberg@arm.com protected: 6510844Sandreas.sandberg@arm.com /// Counter frequency (as specified by CNTFRQ). 6610844Sandreas.sandberg@arm.com uint64_t _freq; 6710844Sandreas.sandberg@arm.com /// Cached copy of the counter period (inverse of the frequency). 6810844Sandreas.sandberg@arm.com Tick _period; 6910844Sandreas.sandberg@arm.com /// Tick when the counter was reset. 7010844Sandreas.sandberg@arm.com Tick _resetTick; 7110844Sandreas.sandberg@arm.com 7212733Sandreas.sandberg@arm.com /// Kernel event stream control register 7310844Sandreas.sandberg@arm.com uint32_t _regCntkctl; 7412733Sandreas.sandberg@arm.com /// Hypervisor event stream control register 7512733Sandreas.sandberg@arm.com uint32_t _regCnthctl; 7610844Sandreas.sandberg@arm.com 7710844Sandreas.sandberg@arm.com public: 7810844Sandreas.sandberg@arm.com SystemCounter(); 7910844Sandreas.sandberg@arm.com 8010844Sandreas.sandberg@arm.com /// Returns the current value of the physical counter. 8110844Sandreas.sandberg@arm.com uint64_t value() const 8210844Sandreas.sandberg@arm.com { 8310844Sandreas.sandberg@arm.com if (_freq == 0) 8410844Sandreas.sandberg@arm.com return 0; // Counter is still off. 8510844Sandreas.sandberg@arm.com return (curTick() - _resetTick) / _period; 8610844Sandreas.sandberg@arm.com } 8710844Sandreas.sandberg@arm.com 8810844Sandreas.sandberg@arm.com /// Returns the counter frequency. 8910844Sandreas.sandberg@arm.com uint64_t freq() const { return _freq; } 9010844Sandreas.sandberg@arm.com /// Sets the counter frequency. 9110844Sandreas.sandberg@arm.com /// @param freq frequency in Hz. 9210844Sandreas.sandberg@arm.com void setFreq(uint32_t freq); 9310844Sandreas.sandberg@arm.com 9410844Sandreas.sandberg@arm.com /// Returns the counter period. 9510844Sandreas.sandberg@arm.com Tick period() const { return _period; } 9610844Sandreas.sandberg@arm.com 9710844Sandreas.sandberg@arm.com void setKernelControl(uint32_t val) { _regCntkctl = val; } 9810844Sandreas.sandberg@arm.com uint32_t getKernelControl() { return _regCntkctl; } 9910844Sandreas.sandberg@arm.com 10012733Sandreas.sandberg@arm.com void setHypControl(uint32_t val) { _regCnthctl = val; } 10112733Sandreas.sandberg@arm.com uint32_t getHypControl() { return _regCnthctl; } 10212733Sandreas.sandberg@arm.com 10311168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 10411168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 10510844Sandreas.sandberg@arm.com 10610844Sandreas.sandberg@arm.com private: 10710844Sandreas.sandberg@arm.com // Disable copying 10810844Sandreas.sandberg@arm.com SystemCounter(const SystemCounter &c); 10910844Sandreas.sandberg@arm.com}; 11010844Sandreas.sandberg@arm.com 11110844Sandreas.sandberg@arm.com/// Per-CPU architected timer. 11212101SCurtis.Dunham@arm.comclass ArchTimer : public Serializable, public Drainable 11310844Sandreas.sandberg@arm.com{ 11410844Sandreas.sandberg@arm.com protected: 11510844Sandreas.sandberg@arm.com /// Control register. 11610844Sandreas.sandberg@arm.com BitUnion32(ArchTimerCtrl) 11710844Sandreas.sandberg@arm.com Bitfield<0> enable; 11810844Sandreas.sandberg@arm.com Bitfield<1> imask; 11910844Sandreas.sandberg@arm.com Bitfield<2> istatus; 12010844Sandreas.sandberg@arm.com EndBitUnion(ArchTimerCtrl) 12110844Sandreas.sandberg@arm.com 12210844Sandreas.sandberg@arm.com /// Name of this timer. 12310844Sandreas.sandberg@arm.com const std::string _name; 12410844Sandreas.sandberg@arm.com 12510844Sandreas.sandberg@arm.com /// Pointer to parent class. 12610844Sandreas.sandberg@arm.com SimObject &_parent; 12710844Sandreas.sandberg@arm.com 12810844Sandreas.sandberg@arm.com SystemCounter &_systemCounter; 12910844Sandreas.sandberg@arm.com 13012975Sgiacomo.travaglini@arm.com ArmInterruptPin * const _interrupt; 13110844Sandreas.sandberg@arm.com 13210844Sandreas.sandberg@arm.com /// Value of the control register ({CNTP/CNTHP/CNTV}_CTL). 13310844Sandreas.sandberg@arm.com ArchTimerCtrl _control; 13410844Sandreas.sandberg@arm.com /// Programmed limit value for the upcounter ({CNTP/CNTHP/CNTV}_CVAL). 13510844Sandreas.sandberg@arm.com uint64_t _counterLimit; 13610845Sandreas.sandberg@arm.com /// Offset relative to the physical timer (CNTVOFF) 13710845Sandreas.sandberg@arm.com uint64_t _offset; 13810844Sandreas.sandberg@arm.com 13910844Sandreas.sandberg@arm.com /** 14010844Sandreas.sandberg@arm.com * Timer settings or the offset has changed, re-evaluate 14110844Sandreas.sandberg@arm.com * trigger condition and raise interrupt if necessary. 14210844Sandreas.sandberg@arm.com */ 14310844Sandreas.sandberg@arm.com void updateCounter(); 14410844Sandreas.sandberg@arm.com 14510844Sandreas.sandberg@arm.com /// Called when the upcounter reaches the programmed value. 14610844Sandreas.sandberg@arm.com void counterLimitReached(); 14712086Sspwilson2@wisc.edu EventFunctionWrapper _counterLimitReachedEvent; 14810844Sandreas.sandberg@arm.com 14912102SCurtis.Dunham@arm.com virtual bool scheduleEvents() { return true; } 15012102SCurtis.Dunham@arm.com 15110844Sandreas.sandberg@arm.com public: 15210844Sandreas.sandberg@arm.com ArchTimer(const std::string &name, 15310844Sandreas.sandberg@arm.com SimObject &parent, 15410844Sandreas.sandberg@arm.com SystemCounter &sysctr, 15512975Sgiacomo.travaglini@arm.com ArmInterruptPin *interrupt); 15610844Sandreas.sandberg@arm.com 15710844Sandreas.sandberg@arm.com /// Returns the timer name. 15810844Sandreas.sandberg@arm.com std::string name() const { return _name; } 15910844Sandreas.sandberg@arm.com 16010844Sandreas.sandberg@arm.com /// Returns the CompareValue view of the timer. 16110844Sandreas.sandberg@arm.com uint64_t compareValue() const { return _counterLimit; } 16210844Sandreas.sandberg@arm.com /// Sets the CompareValue view of the timer. 16310844Sandreas.sandberg@arm.com void setCompareValue(uint64_t val); 16410844Sandreas.sandberg@arm.com 16510844Sandreas.sandberg@arm.com /// Returns the TimerValue view of the timer. 16610844Sandreas.sandberg@arm.com uint32_t timerValue() const { return _counterLimit - value(); } 16710844Sandreas.sandberg@arm.com /// Sets the TimerValue view of the timer. 16810844Sandreas.sandberg@arm.com void setTimerValue(uint32_t val); 16910844Sandreas.sandberg@arm.com 17010844Sandreas.sandberg@arm.com /// Sets the control register. 17110844Sandreas.sandberg@arm.com uint32_t control() const { return _control; } 17210844Sandreas.sandberg@arm.com void setControl(uint32_t val); 17310844Sandreas.sandberg@arm.com 17410845Sandreas.sandberg@arm.com uint64_t offset() const { return _offset; } 17510845Sandreas.sandberg@arm.com void setOffset(uint64_t val); 17610845Sandreas.sandberg@arm.com 17710844Sandreas.sandberg@arm.com /// Returns the value of the counter which this timer relies on. 17810844Sandreas.sandberg@arm.com uint64_t value() const; 17910844Sandreas.sandberg@arm.com 18012101SCurtis.Dunham@arm.com // Serializable 18111168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 18211168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 18310844Sandreas.sandberg@arm.com 18412101SCurtis.Dunham@arm.com // Drainable 18512101SCurtis.Dunham@arm.com DrainState drain() override; 18612101SCurtis.Dunham@arm.com void drainResume() override; 18712101SCurtis.Dunham@arm.com 18810844Sandreas.sandberg@arm.com private: 18910844Sandreas.sandberg@arm.com // Disable copying 19010844Sandreas.sandberg@arm.com ArchTimer(const ArchTimer &t); 19110844Sandreas.sandberg@arm.com}; 19210844Sandreas.sandberg@arm.com 19312102SCurtis.Dunham@arm.comclass ArchTimerKvm : public ArchTimer 19412102SCurtis.Dunham@arm.com{ 19512102SCurtis.Dunham@arm.com private: 19612102SCurtis.Dunham@arm.com ArmSystem &system; 19712102SCurtis.Dunham@arm.com 19812102SCurtis.Dunham@arm.com public: 19912102SCurtis.Dunham@arm.com ArchTimerKvm(const std::string &name, 20012102SCurtis.Dunham@arm.com ArmSystem &system, 20112102SCurtis.Dunham@arm.com SimObject &parent, 20212102SCurtis.Dunham@arm.com SystemCounter &sysctr, 20312975Sgiacomo.travaglini@arm.com ArmInterruptPin *interrupt) 20412102SCurtis.Dunham@arm.com : ArchTimer(name, parent, sysctr, interrupt), system(system) {} 20512102SCurtis.Dunham@arm.com 20612102SCurtis.Dunham@arm.com protected: 20712102SCurtis.Dunham@arm.com // For ArchTimer's in a GenericTimerISA with Kvm execution about 20812102SCurtis.Dunham@arm.com // to begin, skip rescheduling the event. 20912102SCurtis.Dunham@arm.com // Otherwise, we should reschedule the event (if necessary). 21012102SCurtis.Dunham@arm.com bool scheduleEvents() override { 21112102SCurtis.Dunham@arm.com return !system.validKvmEnvironment(); 21212102SCurtis.Dunham@arm.com } 21312102SCurtis.Dunham@arm.com}; 21412102SCurtis.Dunham@arm.com 21512467SCurtis.Dunham@arm.comclass GenericTimer : public ClockedObject 21610037SARM gem5 Developers{ 21710037SARM gem5 Developers public: 21812975Sgiacomo.travaglini@arm.com const GenericTimerParams * params() const; 21912975Sgiacomo.travaglini@arm.com 22010844Sandreas.sandberg@arm.com GenericTimer(GenericTimerParams *p); 22110037SARM gem5 Developers 22211168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 22311168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 22410037SARM gem5 Developers 22510844Sandreas.sandberg@arm.com public: 22613557Sgabeblack@google.com void setMiscReg(int misc_reg, unsigned cpu, RegVal val); 22713557Sgabeblack@google.com RegVal readMiscReg(int misc_reg, unsigned cpu); 22810037SARM gem5 Developers 22910844Sandreas.sandberg@arm.com protected: 23010844Sandreas.sandberg@arm.com struct CoreTimers { 23112102SCurtis.Dunham@arm.com CoreTimers(GenericTimer &parent, ArmSystem &system, unsigned cpu, 23212975Sgiacomo.travaglini@arm.com ArmInterruptPin *_irqPhysS, ArmInterruptPin *_irqPhysNS, 23312975Sgiacomo.travaglini@arm.com ArmInterruptPin *_irqVirt, ArmInterruptPin *_irqHyp) 23412975Sgiacomo.travaglini@arm.com : irqPhysS(_irqPhysS), 23512975Sgiacomo.travaglini@arm.com irqPhysNS(_irqPhysNS), 23612975Sgiacomo.travaglini@arm.com irqVirt(_irqVirt), 23712975Sgiacomo.travaglini@arm.com irqHyp(_irqHyp), 23812733Sandreas.sandberg@arm.com physS(csprintf("%s.phys_s_timer%d", parent.name(), cpu), 23912733Sandreas.sandberg@arm.com system, parent, parent.systemCounter, 24012975Sgiacomo.travaglini@arm.com _irqPhysS), 24110844Sandreas.sandberg@arm.com // This should really be phys_timerN, but we are stuck with 24210844Sandreas.sandberg@arm.com // arch_timer for backwards compatibility. 24312733Sandreas.sandberg@arm.com physNS(csprintf("%s.arch_timer%d", parent.name(), cpu), 24412733Sandreas.sandberg@arm.com system, parent, parent.systemCounter, 24512975Sgiacomo.travaglini@arm.com _irqPhysNS), 24610845Sandreas.sandberg@arm.com virt(csprintf("%s.virt_timer%d", parent.name(), cpu), 24712102SCurtis.Dunham@arm.com system, parent, parent.systemCounter, 24812975Sgiacomo.travaglini@arm.com _irqVirt), 24912733Sandreas.sandberg@arm.com hyp(csprintf("%s.hyp_timer%d", parent.name(), cpu), 25012733Sandreas.sandberg@arm.com system, parent, parent.systemCounter, 25112975Sgiacomo.travaglini@arm.com _irqHyp) 25210844Sandreas.sandberg@arm.com {} 25310037SARM gem5 Developers 25412975Sgiacomo.travaglini@arm.com ArmInterruptPin const *irqPhysS; 25512975Sgiacomo.travaglini@arm.com ArmInterruptPin const *irqPhysNS; 25612975Sgiacomo.travaglini@arm.com ArmInterruptPin const *irqVirt; 25712975Sgiacomo.travaglini@arm.com ArmInterruptPin const *irqHyp; 25810845Sandreas.sandberg@arm.com 25912733Sandreas.sandberg@arm.com ArchTimerKvm physS; 26012733Sandreas.sandberg@arm.com ArchTimerKvm physNS; 26112102SCurtis.Dunham@arm.com ArchTimerKvm virt; 26212733Sandreas.sandberg@arm.com ArchTimerKvm hyp; 26310037SARM gem5 Developers 26410844Sandreas.sandberg@arm.com private: 26510844Sandreas.sandberg@arm.com // Disable copying 26610844Sandreas.sandberg@arm.com CoreTimers(const CoreTimers &c); 26710037SARM gem5 Developers }; 26810037SARM gem5 Developers 26910844Sandreas.sandberg@arm.com CoreTimers &getTimers(int cpu_id); 27010844Sandreas.sandberg@arm.com void createTimers(unsigned cpus); 27110037SARM gem5 Developers 27210844Sandreas.sandberg@arm.com /// System counter. 27310844Sandreas.sandberg@arm.com SystemCounter systemCounter; 27410037SARM gem5 Developers 27510844Sandreas.sandberg@arm.com /// Per-CPU physical architected timers. 27610844Sandreas.sandberg@arm.com std::vector<std::unique_ptr<CoreTimers>> timers; 27710037SARM gem5 Developers 27810844Sandreas.sandberg@arm.com protected: // Configuration 27912102SCurtis.Dunham@arm.com /// ARM system containing this timer 28012102SCurtis.Dunham@arm.com ArmSystem &system; 28110844Sandreas.sandberg@arm.com}; 28210037SARM gem5 Developers 28310844Sandreas.sandberg@arm.comclass GenericTimerISA : public ArmISA::BaseISADevice 28410844Sandreas.sandberg@arm.com{ 28510844Sandreas.sandberg@arm.com public: 28610844Sandreas.sandberg@arm.com GenericTimerISA(GenericTimer &_parent, unsigned _cpu) 28710844Sandreas.sandberg@arm.com : parent(_parent), cpu(_cpu) {} 28810037SARM gem5 Developers 28913557Sgabeblack@google.com void setMiscReg(int misc_reg, RegVal val) override; 29013557Sgabeblack@google.com RegVal readMiscReg(int misc_reg) override; 29110037SARM gem5 Developers 29210037SARM gem5 Developers protected: 29310844Sandreas.sandberg@arm.com GenericTimer &parent; 29410844Sandreas.sandberg@arm.com unsigned cpu; 29510037SARM gem5 Developers}; 29610037SARM gem5 Developers 29710847Sandreas.sandberg@arm.comclass GenericTimerMem : public PioDevice 29810847Sandreas.sandberg@arm.com{ 29910847Sandreas.sandberg@arm.com public: 30010847Sandreas.sandberg@arm.com GenericTimerMem(GenericTimerMemParams *p); 30110847Sandreas.sandberg@arm.com 30211168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 30311168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 30410847Sandreas.sandberg@arm.com 30510847Sandreas.sandberg@arm.com public: // PioDevice 30611168Sandreas.hansson@arm.com AddrRangeList getAddrRanges() const override { return addrRanges; } 30711168Sandreas.hansson@arm.com Tick read(PacketPtr pkt) override; 30811168Sandreas.hansson@arm.com Tick write(PacketPtr pkt) override; 30910847Sandreas.sandberg@arm.com 31010847Sandreas.sandberg@arm.com protected: 31110847Sandreas.sandberg@arm.com uint64_t ctrlRead(Addr addr, size_t size) const; 31210847Sandreas.sandberg@arm.com void ctrlWrite(Addr addr, size_t size, uint64_t value); 31310847Sandreas.sandberg@arm.com 31410847Sandreas.sandberg@arm.com uint64_t timerRead(Addr addr, size_t size) const; 31510847Sandreas.sandberg@arm.com void timerWrite(Addr addr, size_t size, uint64_t value); 31610847Sandreas.sandberg@arm.com 31710847Sandreas.sandberg@arm.com protected: // Registers 31810847Sandreas.sandberg@arm.com static const Addr CTRL_CNTFRQ = 0x000; 31910847Sandreas.sandberg@arm.com static const Addr CTRL_CNTNSAR = 0x004; 32010847Sandreas.sandberg@arm.com static const Addr CTRL_CNTTIDR = 0x008; 32110847Sandreas.sandberg@arm.com static const Addr CTRL_CNTACR_BASE = 0x040; 32210847Sandreas.sandberg@arm.com static const Addr CTRL_CNTVOFF_LO_BASE = 0x080; 32310847Sandreas.sandberg@arm.com static const Addr CTRL_CNTVOFF_HI_BASE = 0x084; 32410847Sandreas.sandberg@arm.com 32510847Sandreas.sandberg@arm.com static const Addr TIMER_CNTPCT_LO = 0x000; 32610847Sandreas.sandberg@arm.com static const Addr TIMER_CNTPCT_HI = 0x004; 32710847Sandreas.sandberg@arm.com static const Addr TIMER_CNTVCT_LO = 0x008; 32810847Sandreas.sandberg@arm.com static const Addr TIMER_CNTVCT_HI = 0x00C; 32910847Sandreas.sandberg@arm.com static const Addr TIMER_CNTFRQ = 0x010; 33010847Sandreas.sandberg@arm.com static const Addr TIMER_CNTEL0ACR = 0x014; 33110847Sandreas.sandberg@arm.com static const Addr TIMER_CNTVOFF_LO = 0x018; 33210847Sandreas.sandberg@arm.com static const Addr TIMER_CNTVOFF_HI = 0x01C; 33310847Sandreas.sandberg@arm.com static const Addr TIMER_CNTP_CVAL_LO = 0x020; 33410847Sandreas.sandberg@arm.com static const Addr TIMER_CNTP_CVAL_HI = 0x024; 33510847Sandreas.sandberg@arm.com static const Addr TIMER_CNTP_TVAL = 0x028; 33610847Sandreas.sandberg@arm.com static const Addr TIMER_CNTP_CTL = 0x02C; 33710847Sandreas.sandberg@arm.com static const Addr TIMER_CNTV_CVAL_LO = 0x030; 33810847Sandreas.sandberg@arm.com static const Addr TIMER_CNTV_CVAL_HI = 0x034; 33910847Sandreas.sandberg@arm.com static const Addr TIMER_CNTV_TVAL = 0x038; 34010847Sandreas.sandberg@arm.com static const Addr TIMER_CNTV_CTL = 0x03C; 34110847Sandreas.sandberg@arm.com 34210847Sandreas.sandberg@arm.com protected: // Params 34310847Sandreas.sandberg@arm.com const AddrRange ctrlRange; 34410847Sandreas.sandberg@arm.com const AddrRange timerRange; 34510847Sandreas.sandberg@arm.com const AddrRangeList addrRanges; 34610847Sandreas.sandberg@arm.com 34710847Sandreas.sandberg@arm.com protected: 34810847Sandreas.sandberg@arm.com /// System counter. 34910847Sandreas.sandberg@arm.com SystemCounter systemCounter; 35010847Sandreas.sandberg@arm.com ArchTimer physTimer; 35110847Sandreas.sandberg@arm.com ArchTimer virtTimer; 35210847Sandreas.sandberg@arm.com}; 35310847Sandreas.sandberg@arm.com 35410037SARM gem5 Developers#endif // __DEV_ARM_GENERIC_TIMER_HH__ 355