12623SN/A/* 213012Sandreas.sandberg@arm.com * Copyright (c) 2012-2013, 2015, 2018 ARM Limited 38926Sandreas.hansson@arm.com * All rights reserved. 48926Sandreas.hansson@arm.com * 58926Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68926Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78926Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88926Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98926Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108926Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118926Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128926Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138926Sandreas.hansson@arm.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 432623SN/A#ifndef __CPU_SIMPLE_ATOMIC_HH__ 442623SN/A#define __CPU_SIMPLE_ATOMIC_HH__ 452623SN/A 462623SN/A#include "cpu/simple/base.hh" 4711147Smitch.hayenga@arm.com#include "cpu/simple/exec_context.hh" 4811608Snikos.nikoleris@arm.com#include "mem/request.hh" 495529Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 5010381Sdam.sunwoo@arm.com#include "sim/probe/probe.hh" 519647Sdam.sunwoo@arm.com 522623SN/Aclass AtomicSimpleCPU : public BaseSimpleCPU 532623SN/A{ 542623SN/A public: 552623SN/A 565529Snate@binkert.org AtomicSimpleCPU(AtomicSimpleCPUParams *params); 572623SN/A virtual ~AtomicSimpleCPU(); 582623SN/A 5911169Sandreas.hansson@arm.com void init() override; 602623SN/A 6113012Sandreas.sandberg@arm.com protected: 622623SN/A 6312127Sspwilson2@wisc.edu EventFunctionWrapper tickEvent; 642623SN/A 652623SN/A const int width; 666078Sgblack@eecs.umich.edu bool locked; 675487Snate@binkert.org const bool simulate_data_stalls; 685487Snate@binkert.org const bool simulate_inst_stalls; 692623SN/A 702623SN/A // main simulation loop (one cycle) 712623SN/A void tick(); 722623SN/A 738707Sandreas.hansson@arm.com /** 749443SAndreas.Sandberg@ARM.com * Check if a system is in a drained state. 759443SAndreas.Sandberg@ARM.com * 769443SAndreas.Sandberg@ARM.com * We need to drain if: 779443SAndreas.Sandberg@ARM.com * <ul> 789443SAndreas.Sandberg@ARM.com * <li>We are in the middle of a microcode sequence as some CPUs 799443SAndreas.Sandberg@ARM.com * (e.g., HW accelerated CPUs) can't be started in the middle 809443SAndreas.Sandberg@ARM.com * of a gem5 microcode sequence. 819443SAndreas.Sandberg@ARM.com * 829443SAndreas.Sandberg@ARM.com * <li>The CPU is in a LLSC region. This shouldn't normally happen 839443SAndreas.Sandberg@ARM.com * as these are executed atomically within a single tick() 849443SAndreas.Sandberg@ARM.com * call. The only way this can happen at the moment is if 859443SAndreas.Sandberg@ARM.com * there is an event in the PC event queue that affects the 869443SAndreas.Sandberg@ARM.com * CPU state while it is in an LLSC region. 879443SAndreas.Sandberg@ARM.com * 889443SAndreas.Sandberg@ARM.com * <li>Stay at PC is true. 899443SAndreas.Sandberg@ARM.com * </ul> 909443SAndreas.Sandberg@ARM.com */ 9114085Sgiacomo.travaglini@arm.com bool isCpuDrained() const { 9211147Smitch.hayenga@arm.com SimpleExecContext &t_info = *threadInfo[curThread]; 9311147Smitch.hayenga@arm.com 9411147Smitch.hayenga@arm.com return t_info.thread->microPC() == 0 && 959443SAndreas.Sandberg@ARM.com !locked && 9611147Smitch.hayenga@arm.com !t_info.stayAtPC; 979443SAndreas.Sandberg@ARM.com } 989443SAndreas.Sandberg@ARM.com 999443SAndreas.Sandberg@ARM.com /** 1009443SAndreas.Sandberg@ARM.com * Try to complete a drain request. 1019443SAndreas.Sandberg@ARM.com * 1029443SAndreas.Sandberg@ARM.com * @returns true if the CPU is drained, false otherwise. 1039443SAndreas.Sandberg@ARM.com */ 1049443SAndreas.Sandberg@ARM.com bool tryCompleteDrain(); 1059443SAndreas.Sandberg@ARM.com 10613012Sandreas.sandberg@arm.com virtual Tick sendPacket(MasterPort &port, const PacketPtr &pkt); 10713012Sandreas.sandberg@arm.com 1089443SAndreas.Sandberg@ARM.com /** 1098707Sandreas.hansson@arm.com * An AtomicCPUPort overrides the default behaviour of the 1109608Sandreas.hansson@arm.com * recvAtomicSnoop and ignores the packet instead of panicking. It 1119608Sandreas.hansson@arm.com * also provides an implementation for the purely virtual timing 1129608Sandreas.hansson@arm.com * functions and panics on either of these. 1138707Sandreas.hansson@arm.com */ 1149608Sandreas.hansson@arm.com class AtomicCPUPort : public MasterPort 1152623SN/A { 1168707Sandreas.hansson@arm.com 1172623SN/A public: 1182623SN/A 11910030SAli.Saidi@ARM.com AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu) 1209608Sandreas.hansson@arm.com : MasterPort(_name, _cpu) 1212623SN/A { } 1222623SN/A 1232623SN/A protected: 1243192Srdreslin@umich.edu 1259608Sandreas.hansson@arm.com bool recvTimingResp(PacketPtr pkt) 1269608Sandreas.hansson@arm.com { 1279608Sandreas.hansson@arm.com panic("Atomic CPU doesn't expect recvTimingResp!\n"); 1289608Sandreas.hansson@arm.com return true; 1299608Sandreas.hansson@arm.com } 1309608Sandreas.hansson@arm.com 13110713Sandreas.hansson@arm.com void recvReqRetry() 1329608Sandreas.hansson@arm.com { 1339608Sandreas.hansson@arm.com panic("Atomic CPU doesn't expect recvRetry!\n"); 1349608Sandreas.hansson@arm.com } 1359608Sandreas.hansson@arm.com 1362623SN/A }; 1374192Sktlim@umich.edu 13810030SAli.Saidi@ARM.com class AtomicCPUDPort : public AtomicCPUPort 13910030SAli.Saidi@ARM.com { 14010030SAli.Saidi@ARM.com 14110030SAli.Saidi@ARM.com public: 14210030SAli.Saidi@ARM.com AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu) 14310030SAli.Saidi@ARM.com : AtomicCPUPort(_name, _cpu), cpu(_cpu) 14410030SAli.Saidi@ARM.com { 14510030SAli.Saidi@ARM.com cacheBlockMask = ~(cpu->cacheLineSize() - 1); 14610030SAli.Saidi@ARM.com } 14710030SAli.Saidi@ARM.com 14810030SAli.Saidi@ARM.com bool isSnooping() const { return true; } 14910030SAli.Saidi@ARM.com 15010030SAli.Saidi@ARM.com Addr cacheBlockMask; 15110030SAli.Saidi@ARM.com protected: 15210030SAli.Saidi@ARM.com BaseSimpleCPU *cpu; 15310030SAli.Saidi@ARM.com 15410030SAli.Saidi@ARM.com virtual Tick recvAtomicSnoop(PacketPtr pkt); 15510030SAli.Saidi@ARM.com virtual void recvFunctionalSnoop(PacketPtr pkt); 15610030SAli.Saidi@ARM.com }; 15710030SAli.Saidi@ARM.com 15810030SAli.Saidi@ARM.com 1598707Sandreas.hansson@arm.com AtomicCPUPort icachePort; 16010030SAli.Saidi@ARM.com AtomicCPUDPort dcachePort; 1612623SN/A 16213012Sandreas.sandberg@arm.com 16312749Sgiacomo.travaglini@arm.com RequestPtr ifetch_req; 16412749Sgiacomo.travaglini@arm.com RequestPtr data_read_req; 16512749Sgiacomo.travaglini@arm.com RequestPtr data_write_req; 16613652Sqtt2@cornell.edu RequestPtr data_amo_req; 1672623SN/A 1682623SN/A bool dcache_access; 1692662Sstever@eecs.umich.edu Tick dcache_latency; 1702623SN/A 17110381Sdam.sunwoo@arm.com /** Probe Points. */ 17210381Sdam.sunwoo@arm.com ProbePointArg<std::pair<SimpleThread*, const StaticInstPtr>> *ppCommit; 1739647Sdam.sunwoo@arm.com 1748850Sandreas.hansson@arm.com protected: 1758850Sandreas.hansson@arm.com 1768850Sandreas.hansson@arm.com /** Return a reference to the data port. */ 17714198Sgabeblack@google.com Port &getDataPort() override { return dcachePort; } 1788850Sandreas.hansson@arm.com 1798850Sandreas.hansson@arm.com /** Return a reference to the instruction port. */ 18014198Sgabeblack@google.com Port &getInstPort() override { return icachePort; } 1818850Sandreas.hansson@arm.com 18211148Smitch.hayenga@arm.com /** Perform snoop for other cpu-local thread contexts. */ 18311148Smitch.hayenga@arm.com void threadSnoop(PacketPtr pkt, ThreadID sender); 18411148Smitch.hayenga@arm.com 1852623SN/A public: 1862623SN/A 18711168Sandreas.hansson@arm.com DrainState drain() override; 18811168Sandreas.hansson@arm.com void drainResume() override; 1892623SN/A 19011169Sandreas.hansson@arm.com void switchOut() override; 19111169Sandreas.hansson@arm.com void takeOverFrom(BaseCPU *oldCPU) override; 1922623SN/A 19311169Sandreas.hansson@arm.com void verifyMemoryMode() const override; 1949523SAndreas.Sandberg@ARM.com 19511169Sandreas.hansson@arm.com void activateContext(ThreadID thread_num) override; 19611169Sandreas.hansson@arm.com void suspendContext(ThreadID thread_num) override; 1972623SN/A 19813954Sgiacomo.gabrielli@arm.com /** 19913954Sgiacomo.gabrielli@arm.com * Helper function used to set up the request for a single fragment of a 20013954Sgiacomo.gabrielli@arm.com * memory access. 20113954Sgiacomo.gabrielli@arm.com * 20213954Sgiacomo.gabrielli@arm.com * Takes care of setting up the appropriate byte-enable mask for the 20313954Sgiacomo.gabrielli@arm.com * fragment, given the mask for the entire memory access. 20413954Sgiacomo.gabrielli@arm.com * 20513954Sgiacomo.gabrielli@arm.com * @param req Pointer to the Request object to populate. 20613954Sgiacomo.gabrielli@arm.com * @param frag_addr Start address of the fragment. 20713954Sgiacomo.gabrielli@arm.com * @param size Total size of the memory access in bytes. 20813954Sgiacomo.gabrielli@arm.com * @param flags Request flags. 20913954Sgiacomo.gabrielli@arm.com * @param byte_enable Byte-enable mask for the entire memory access. 21013954Sgiacomo.gabrielli@arm.com * @param[out] frag_size Fragment size. 21113954Sgiacomo.gabrielli@arm.com * @param[in,out] size_left Size left to be processed in the memory access. 21213954Sgiacomo.gabrielli@arm.com * @return True if the byte-enable mask for the fragment is not all-false. 21313954Sgiacomo.gabrielli@arm.com */ 21413954Sgiacomo.gabrielli@arm.com bool genMemFragmentRequest(const RequestPtr& req, Addr frag_addr, 21513954Sgiacomo.gabrielli@arm.com int size, Request::Flags flags, 21613954Sgiacomo.gabrielli@arm.com const std::vector<bool>& byte_enable, 21713954Sgiacomo.gabrielli@arm.com int& frag_size, int& size_left) const; 21813954Sgiacomo.gabrielli@arm.com 21911169Sandreas.hansson@arm.com Fault readMem(Addr addr, uint8_t *data, unsigned size, 22013954Sgiacomo.gabrielli@arm.com Request::Flags flags, 22113954Sgiacomo.gabrielli@arm.com const std::vector<bool>& byteEnable = std::vector<bool>()) 22213954Sgiacomo.gabrielli@arm.com override; 2237520Sgblack@eecs.umich.edu 2248444Sgblack@eecs.umich.edu Fault writeMem(uint8_t *data, unsigned size, 22513954Sgiacomo.gabrielli@arm.com Addr addr, Request::Flags flags, uint64_t *res, 22613954Sgiacomo.gabrielli@arm.com const std::vector<bool>& byteEnable = std::vector<bool>()) 22713954Sgiacomo.gabrielli@arm.com override; 2287520Sgblack@eecs.umich.edu 22913652Sqtt2@cornell.edu Fault amoMem(Addr addr, uint8_t* data, unsigned size, 23014297Sjordi.vaquero@metempsy.com Request::Flags flags, AtomicOpFunctorPtr amo_op) override; 23113652Sqtt2@cornell.edu 23211169Sandreas.hansson@arm.com void regProbePoints() override; 23310381Sdam.sunwoo@arm.com 2345315Sstever@gmail.com /** 2355315Sstever@gmail.com * Print state of address in memory system via PrintReq (for 2365315Sstever@gmail.com * debugging). 2375315Sstever@gmail.com */ 2385315Sstever@gmail.com void printAddr(Addr a); 2392623SN/A}; 2402623SN/A 2412623SN/A#endif // __CPU_SIMPLE_ATOMIC_HH__ 242