1/*
2 * Copyright (c) 2012-2013, 2015, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#ifndef __CPU_SIMPLE_ATOMIC_HH__
44#define __CPU_SIMPLE_ATOMIC_HH__
45
46#include "cpu/simple/base.hh"
47#include "cpu/simple/exec_context.hh"
48#include "mem/request.hh"
49#include "params/AtomicSimpleCPU.hh"
50#include "sim/probe/probe.hh"
51
52class AtomicSimpleCPU : public BaseSimpleCPU
53{
54  public:
55
56    AtomicSimpleCPU(AtomicSimpleCPUParams *params);
57    virtual ~AtomicSimpleCPU();
58
59    void init() override;
60
61  protected:
62
63    EventFunctionWrapper tickEvent;
64
65    const int width;
66    bool locked;
67    const bool simulate_data_stalls;
68    const bool simulate_inst_stalls;
69
70    // main simulation loop (one cycle)
71    void tick();
72
73    /**
74     * Check if a system is in a drained state.
75     *
76     * We need to drain if:
77     * <ul>
78     * <li>We are in the middle of a microcode sequence as some CPUs
79     *     (e.g., HW accelerated CPUs) can't be started in the middle
80     *     of a gem5 microcode sequence.
81     *
82     * <li>The CPU is in a LLSC region. This shouldn't normally happen
83     *     as these are executed atomically within a single tick()
84     *     call. The only way this can happen at the moment is if
85     *     there is an event in the PC event queue that affects the
86     *     CPU state while it is in an LLSC region.
87     *
88     * <li>Stay at PC is true.
89     * </ul>
90     */
91    bool isCpuDrained() const {
92        SimpleExecContext &t_info = *threadInfo[curThread];
93
94        return t_info.thread->microPC() == 0 &&
95            !locked &&
96            !t_info.stayAtPC;
97    }
98
99    /**
100     * Try to complete a drain request.
101     *
102     * @returns true if the CPU is drained, false otherwise.
103     */
104    bool tryCompleteDrain();
105
106    virtual Tick sendPacket(MasterPort &port, const PacketPtr &pkt);
107
108    /**
109     * An AtomicCPUPort overrides the default behaviour of the
110     * recvAtomicSnoop and ignores the packet instead of panicking. It
111     * also provides an implementation for the purely virtual timing
112     * functions and panics on either of these.
113     */
114    class AtomicCPUPort : public MasterPort
115    {
116
117      public:
118
119        AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu)
120            : MasterPort(_name, _cpu)
121        { }
122
123      protected:
124
125        bool recvTimingResp(PacketPtr pkt)
126        {
127            panic("Atomic CPU doesn't expect recvTimingResp!\n");
128            return true;
129        }
130
131        void recvReqRetry()
132        {
133            panic("Atomic CPU doesn't expect recvRetry!\n");
134        }
135
136    };
137
138    class AtomicCPUDPort : public AtomicCPUPort
139    {
140
141      public:
142        AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu)
143            : AtomicCPUPort(_name, _cpu), cpu(_cpu)
144        {
145            cacheBlockMask = ~(cpu->cacheLineSize() - 1);
146        }
147
148        bool isSnooping() const { return true; }
149
150        Addr cacheBlockMask;
151      protected:
152        BaseSimpleCPU *cpu;
153
154        virtual Tick recvAtomicSnoop(PacketPtr pkt);
155        virtual void recvFunctionalSnoop(PacketPtr pkt);
156    };
157
158
159    AtomicCPUPort icachePort;
160    AtomicCPUDPort dcachePort;
161
162
163    RequestPtr ifetch_req;
164    RequestPtr data_read_req;
165    RequestPtr data_write_req;
166    RequestPtr data_amo_req;
167
168    bool dcache_access;
169    Tick dcache_latency;
170
171    /** Probe Points. */
172    ProbePointArg<std::pair<SimpleThread*, const StaticInstPtr>> *ppCommit;
173
174  protected:
175
176    /** Return a reference to the data port. */
177    Port &getDataPort() override { return dcachePort; }
178
179    /** Return a reference to the instruction port. */
180    Port &getInstPort() override { return icachePort; }
181
182    /** Perform snoop for other cpu-local thread contexts. */
183    void threadSnoop(PacketPtr pkt, ThreadID sender);
184
185  public:
186
187    DrainState drain() override;
188    void drainResume() override;
189
190    void switchOut() override;
191    void takeOverFrom(BaseCPU *oldCPU) override;
192
193    void verifyMemoryMode() const override;
194
195    void activateContext(ThreadID thread_num) override;
196    void suspendContext(ThreadID thread_num) override;
197
198    /**
199     * Helper function used to set up the request for a single fragment of a
200     * memory access.
201     *
202     * Takes care of setting up the appropriate byte-enable mask for the
203     * fragment, given the mask for the entire memory access.
204     *
205     * @param req Pointer to the Request object to populate.
206     * @param frag_addr Start address of the fragment.
207     * @param size Total size of the memory access in bytes.
208     * @param flags Request flags.
209     * @param byte_enable Byte-enable mask for the entire memory access.
210     * @param[out] frag_size Fragment size.
211     * @param[in,out] size_left Size left to be processed in the memory access.
212     * @return True if the byte-enable mask for the fragment is not all-false.
213     */
214    bool genMemFragmentRequest(const RequestPtr& req, Addr frag_addr,
215                               int size, Request::Flags flags,
216                               const std::vector<bool>& byte_enable,
217                               int& frag_size, int& size_left) const;
218
219    Fault readMem(Addr addr, uint8_t *data, unsigned size,
220                  Request::Flags flags,
221                  const std::vector<bool>& byteEnable = std::vector<bool>())
222        override;
223
224    Fault writeMem(uint8_t *data, unsigned size,
225                   Addr addr, Request::Flags flags, uint64_t *res,
226                   const std::vector<bool>& byteEnable = std::vector<bool>())
227        override;
228
229    Fault amoMem(Addr addr, uint8_t* data, unsigned size,
230                 Request::Flags flags, AtomicOpFunctorPtr amo_op) override;
231
232    void regProbePoints() override;
233
234    /**
235     * Print state of address in memory system via PrintReq (for
236     * debugging).
237     */
238    void printAddr(Addr a);
239};
240
241#endif // __CPU_SIMPLE_ATOMIC_HH__
242