11689SN/A/* 210329Smitch.hayenga@arm.com * Copyright (c) 2010-2012, 2014 ARM Limited 37849SAli.Saidi@ARM.com * All rights reserved 47849SAli.Saidi@ARM.com * 57849SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67849SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77849SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87849SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97849SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107849SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117849SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127849SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137849SAli.Saidi@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412756Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 442292SN/A#ifndef __CPU_O3_FETCH_HH__ 452292SN/A#define __CPU_O3_FETCH_HH__ 461060SN/A 479020Sgblack@eecs.umich.edu#include "arch/decoder.hh" 482669Sktlim@umich.edu#include "arch/utility.hh" 491461SN/A#include "base/statistics.hh" 506658Snate@binkert.org#include "config/the_isa.hh" 511060SN/A#include "cpu/pc_event.hh" 529480Snilay@cs.wisc.edu#include "cpu/pred/bpred_unit.hh" 538229Snate@binkert.org#include "cpu/timebuf.hh" 547849SAli.Saidi@ARM.com#include "cpu/translation.hh" 5513559Snikos.nikoleris@arm.com#include "enums/FetchPolicy.hh" 563348Sbinkertn@umich.edu#include "mem/packet.hh" 572669Sktlim@umich.edu#include "mem/port.hh" 581461SN/A#include "sim/eventq.hh" 5910023Smatt.horsnell@ARM.com#include "sim/probe/probe.hh" 601060SN/A 618737Skoansin.tan@gmail.comstruct DerivO3CPUParams; 6214195Sgabeblack@google.comtemplate <class Impl> 6314195Sgabeblack@google.comclass FullO3CPU; 645529Snate@binkert.org 651060SN/A/** 662329SN/A * DefaultFetch class handles both single threaded and SMT fetch. Its 672329SN/A * width is specified by the parameters; each cycle it tries to fetch 682329SN/A * that many instructions. It supports using a branch predictor to 692329SN/A * predict direction and targets. 702348SN/A * It supports the idling functionality of the CPU by indicating to 712329SN/A * the CPU when it is active and inactive. 721060SN/A */ 731060SN/Atemplate <class Impl> 742292SN/Aclass DefaultFetch 751060SN/A{ 761060SN/A public: 771060SN/A /** Typedefs from Impl. */ 781061SN/A typedef typename Impl::CPUPol CPUPol; 791060SN/A typedef typename Impl::DynInst DynInst; 801061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 812733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 821060SN/A 832292SN/A /** Typedefs from the CPU policy. */ 841061SN/A typedef typename CPUPol::FetchStruct FetchStruct; 851061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 861060SN/A 871060SN/A /** Typedefs from ISA. */ 882107SN/A typedef TheISA::MachInst MachInst; 892632Sstever@eecs.umich.edu 9014195Sgabeblack@google.com /** 9114195Sgabeblack@google.com * IcachePort class for instruction fetch. 9214195Sgabeblack@google.com */ 9314195Sgabeblack@google.com class IcachePort : public MasterPort 9414195Sgabeblack@google.com { 9514195Sgabeblack@google.com protected: 9614195Sgabeblack@google.com /** Pointer to fetch. */ 9714195Sgabeblack@google.com DefaultFetch<Impl> *fetch; 9814195Sgabeblack@google.com 9914195Sgabeblack@google.com public: 10014195Sgabeblack@google.com /** Default constructor. */ 10114195Sgabeblack@google.com IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) 10214195Sgabeblack@google.com : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) 10314195Sgabeblack@google.com { } 10414195Sgabeblack@google.com 10514195Sgabeblack@google.com protected: 10614195Sgabeblack@google.com 10714195Sgabeblack@google.com /** Timing version of receive. Handles setting fetch to the 10814195Sgabeblack@google.com * proper status to start fetching. */ 10914195Sgabeblack@google.com virtual bool recvTimingResp(PacketPtr pkt); 11014195Sgabeblack@google.com 11114195Sgabeblack@google.com /** Handles doing a retry of a failed fetch. */ 11214195Sgabeblack@google.com virtual void recvReqRetry(); 11314195Sgabeblack@google.com }; 11414195Sgabeblack@google.com 1157849SAli.Saidi@ARM.com class FetchTranslation : public BaseTLB::Translation 1167849SAli.Saidi@ARM.com { 1177849SAli.Saidi@ARM.com protected: 1187849SAli.Saidi@ARM.com DefaultFetch<Impl> *fetch; 1197849SAli.Saidi@ARM.com 1207849SAli.Saidi@ARM.com public: 1217849SAli.Saidi@ARM.com FetchTranslation(DefaultFetch<Impl> *_fetch) 1227849SAli.Saidi@ARM.com : fetch(_fetch) 1237849SAli.Saidi@ARM.com {} 1247849SAli.Saidi@ARM.com 1257849SAli.Saidi@ARM.com void 1267944SGiacomo.Gabrielli@arm.com markDelayed() 1277944SGiacomo.Gabrielli@arm.com {} 1287944SGiacomo.Gabrielli@arm.com 1297944SGiacomo.Gabrielli@arm.com void 13012749Sgiacomo.travaglini@arm.com finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, 1317849SAli.Saidi@ARM.com BaseTLB::Mode mode) 1327849SAli.Saidi@ARM.com { 1337849SAli.Saidi@ARM.com assert(mode == BaseTLB::Execute); 1347849SAli.Saidi@ARM.com fetch->finishTranslation(fault, req); 1357849SAli.Saidi@ARM.com delete this; 1367849SAli.Saidi@ARM.com } 1377849SAli.Saidi@ARM.com }; 1382935Sksewell@umich.edu 1398462Sgeoffrey.blake@arm.com private: 1408462Sgeoffrey.blake@arm.com /* Event to delay delivery of a fetch translation result in case of 1418462Sgeoffrey.blake@arm.com * a fault and the nop to carry the fault cannot be generated 1428462Sgeoffrey.blake@arm.com * immediately */ 1438462Sgeoffrey.blake@arm.com class FinishTranslationEvent : public Event 1448462Sgeoffrey.blake@arm.com { 1458462Sgeoffrey.blake@arm.com private: 1468462Sgeoffrey.blake@arm.com DefaultFetch<Impl> *fetch; 1478462Sgeoffrey.blake@arm.com Fault fault; 1488462Sgeoffrey.blake@arm.com RequestPtr req; 1498462Sgeoffrey.blake@arm.com 1508462Sgeoffrey.blake@arm.com public: 1518462Sgeoffrey.blake@arm.com FinishTranslationEvent(DefaultFetch<Impl> *_fetch) 15213453Srekai.gonzalezalberquilla@arm.com : fetch(_fetch), req(nullptr) 1538462Sgeoffrey.blake@arm.com {} 1548462Sgeoffrey.blake@arm.com 1558462Sgeoffrey.blake@arm.com void setFault(Fault _fault) 1568462Sgeoffrey.blake@arm.com { 1578462Sgeoffrey.blake@arm.com fault = _fault; 1588462Sgeoffrey.blake@arm.com } 1598462Sgeoffrey.blake@arm.com 16012749Sgiacomo.travaglini@arm.com void setReq(const RequestPtr &_req) 1618462Sgeoffrey.blake@arm.com { 1628462Sgeoffrey.blake@arm.com req = _req; 1638462Sgeoffrey.blake@arm.com } 1648462Sgeoffrey.blake@arm.com 1658462Sgeoffrey.blake@arm.com /** Process the delayed finish translation */ 1668462Sgeoffrey.blake@arm.com void process() 1678462Sgeoffrey.blake@arm.com { 1688462Sgeoffrey.blake@arm.com assert(fetch->numInst < fetch->fetchWidth); 1698462Sgeoffrey.blake@arm.com fetch->finishTranslation(fault, req); 1708462Sgeoffrey.blake@arm.com } 1718462Sgeoffrey.blake@arm.com 1728462Sgeoffrey.blake@arm.com const char *description() const 1738462Sgeoffrey.blake@arm.com { 1748462Sgeoffrey.blake@arm.com return "FullO3CPU FetchFinishTranslation"; 1758462Sgeoffrey.blake@arm.com } 1768462Sgeoffrey.blake@arm.com }; 1778462Sgeoffrey.blake@arm.com 1781060SN/A public: 1792329SN/A /** Overall fetch status. Used to determine if the CPU can 1802329SN/A * deschedule itsef due to a lack of activity. 1812292SN/A */ 1822292SN/A enum FetchStatus { 1832292SN/A Active, 1842292SN/A Inactive 1852292SN/A }; 1862292SN/A 1872292SN/A /** Individual thread status. */ 1882292SN/A enum ThreadStatus { 1891060SN/A Running, 1901060SN/A Idle, 1911060SN/A Squashing, 1921060SN/A Blocked, 1932292SN/A Fetching, 1942292SN/A TrapPending, 1952292SN/A QuiescePending, 1967849SAli.Saidi@ARM.com ItlbWait, 1972669Sktlim@umich.edu IcacheWaitResponse, 1982696Sktlim@umich.edu IcacheWaitRetry, 1998460SAli.Saidi@ARM.com IcacheAccessComplete, 2008460SAli.Saidi@ARM.com NoGoodAddr 2011060SN/A }; 2021060SN/A 2032292SN/A private: 2042292SN/A /** Fetch status. */ 2052292SN/A FetchStatus _status; 2062292SN/A 2072292SN/A /** Per-thread status. */ 2082292SN/A ThreadStatus fetchStatus[Impl::MaxThreads]; 2092292SN/A 2102292SN/A /** Fetch policy. */ 21113559Snikos.nikoleris@arm.com FetchPolicy fetchPolicy; 2122292SN/A 2132292SN/A /** List that has the threads organized by priority. */ 2146221Snate@binkert.org std::list<ThreadID> priorityList; 2151060SN/A 21610023Smatt.horsnell@ARM.com /** Probe points. */ 21710023Smatt.horsnell@ARM.com ProbePointArg<DynInstPtr> *ppFetch; 21811246Sradhika.jagtap@ARM.com /** To probe when a fetch request is successfully sent. */ 21911246Sradhika.jagtap@ARM.com ProbePointArg<RequestPtr> *ppFetchRequestSent; 22010023Smatt.horsnell@ARM.com 2211060SN/A public: 2222292SN/A /** DefaultFetch constructor. */ 2235529Snate@binkert.org DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params); 2241684SN/A 2252292SN/A /** Returns the name of fetch. */ 2262292SN/A std::string name() const; 2271684SN/A 2282292SN/A /** Registers statistics. */ 2291062SN/A void regStats(); 2301062SN/A 23110023Smatt.horsnell@ARM.com /** Registers probes. */ 23210023Smatt.horsnell@ARM.com void regProbePoints(); 23310023Smatt.horsnell@ARM.com 2342292SN/A /** Sets the main backwards communication time buffer pointer. */ 2351060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); 2361060SN/A 2372292SN/A /** Sets pointer to list of active threads. */ 2386221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 2392292SN/A 2402292SN/A /** Sets pointer to time buffer used to communicate to the next stage. */ 2411060SN/A void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 2421060SN/A 2432292SN/A /** Initialize stage. */ 2449427SAndreas.Sandberg@ARM.com void startupStage(); 2452292SN/A 24613641Sqtt2@cornell.edu /** Clear all thread-specific states*/ 24713641Sqtt2@cornell.edu void clearStates(ThreadID tid); 24813641Sqtt2@cornell.edu 2498707Sandreas.hansson@arm.com /** Handles retrying the fetch access. */ 25010713Sandreas.hansson@arm.com void recvReqRetry(); 2518707Sandreas.hansson@arm.com 2522292SN/A /** Processes cache completion event. */ 2532669Sktlim@umich.edu void processCacheCompletion(PacketPtr pkt); 2542292SN/A 2559444SAndreas.Sandberg@ARM.com /** Resume after a drain. */ 2569444SAndreas.Sandberg@ARM.com void drainResume(); 2572843Sktlim@umich.edu 2589444SAndreas.Sandberg@ARM.com /** Perform sanity checks after a drain. */ 2599444SAndreas.Sandberg@ARM.com void drainSanityCheck() const; 2602843Sktlim@umich.edu 2619444SAndreas.Sandberg@ARM.com /** Has the stage drained? */ 2629444SAndreas.Sandberg@ARM.com bool isDrained() const; 2632307SN/A 2642348SN/A /** Takes over from another CPU's thread. */ 2652307SN/A void takeOverFrom(); 2662307SN/A 2679444SAndreas.Sandberg@ARM.com /** 2689444SAndreas.Sandberg@ARM.com * Stall the fetch stage after reaching a safe drain point. 2699444SAndreas.Sandberg@ARM.com * 2709444SAndreas.Sandberg@ARM.com * The CPU uses this method to stop fetching instructions from a 2719444SAndreas.Sandberg@ARM.com * thread that has been drained. The drain stall is different from 2729444SAndreas.Sandberg@ARM.com * all other stalls in that it is signaled instantly from the 2739444SAndreas.Sandberg@ARM.com * commit stage (without the normal communication delay) when it 2749444SAndreas.Sandberg@ARM.com * has reached a safe point to drain from. 2759444SAndreas.Sandberg@ARM.com */ 2769444SAndreas.Sandberg@ARM.com void drainStall(ThreadID tid); 2772307SN/A 2782348SN/A /** Tells fetch to wake up from a quiesce instruction. */ 2792292SN/A void wakeFromQuiesce(); 2801060SN/A 28110331Smitch.hayenga@arm.com /** For priority-based fetch policies, need to keep update priorityList */ 28210331Smitch.hayenga@arm.com void deactivateThread(ThreadID tid); 2831061SN/A private: 2849444SAndreas.Sandberg@ARM.com /** Reset this pipeline stage */ 2859444SAndreas.Sandberg@ARM.com void resetStage(); 2869444SAndreas.Sandberg@ARM.com 2872329SN/A /** Changes the status of this stage to active, and indicates this 2882329SN/A * to the CPU. 2892292SN/A */ 2902292SN/A inline void switchToActive(); 2912292SN/A 2922329SN/A /** Changes the status of this stage to inactive, and indicates 2932329SN/A * this to the CPU. 2942292SN/A */ 2952292SN/A inline void switchToInactive(); 2962292SN/A 2971061SN/A /** 2981061SN/A * Looks up in the branch predictor to see if the next PC should be 2991061SN/A * either next PC+=MachInst or a branch target. 3001763SN/A * @param next_PC Next PC variable passed in by reference. It is 3011061SN/A * expected to be set to the current PC; it will be updated with what 3021061SN/A * the next PC will be. 3032935Sksewell@umich.edu * @param next_NPC Used for ISAs which use delay slots. 3041061SN/A * @return Whether or not a branch was predicted as taken. 3051061SN/A */ 30613429Srekai.gonzalezalberquilla@arm.com bool lookupAndUpdateNextPC(const DynInstPtr &inst, TheISA::PCState &pc); 3071062SN/A 3081062SN/A /** 3099982Satgutier@umich.edu * Fetches the cache line that contains the fetch PC. Returns any 3101062SN/A * fault that happened. Puts the data into the class variable 3119982Satgutier@umich.edu * fetchBuffer, which may not hold the entire fetched cache line. 3127764Sgblack@eecs.umich.edu * @param vaddr The memory address that is being fetched from. 3132292SN/A * @param ret_fault The fault reference that will be set to the result of 3142292SN/A * the icache access. 3152292SN/A * @param tid Thread id. 3167764Sgblack@eecs.umich.edu * @param pc The actual PC of the current instruction. 3171062SN/A * @return Any fault that occured. 3181062SN/A */ 3197849SAli.Saidi@ARM.com bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc); 32012749Sgiacomo.travaglini@arm.com void finishTranslation(const Fault &fault, const RequestPtr &mem_req); 3211062SN/A 3227847Sminkyu.jeong@arm.com 3237847Sminkyu.jeong@arm.com /** Check if an interrupt is pending and that we need to handle 3247847Sminkyu.jeong@arm.com */ 3257847Sminkyu.jeong@arm.com bool 3267847Sminkyu.jeong@arm.com checkInterrupt(Addr pc) 3277847Sminkyu.jeong@arm.com { 3287847Sminkyu.jeong@arm.com return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3))); 3297847Sminkyu.jeong@arm.com } 3307847Sminkyu.jeong@arm.com 3312292SN/A /** Squashes a specific thread and resets the PC. */ 3328503Sgblack@eecs.umich.edu inline void doSquash(const TheISA::PCState &newPC, 3338503Sgblack@eecs.umich.edu const DynInstPtr squashInst, ThreadID tid); 3341684SN/A 3352292SN/A /** Squashes a specific thread and resets the PC. Also tells the CPU to 3362292SN/A * remove any instructions between fetch and decode that should be sqaushed. 3372292SN/A */ 3387720Sgblack@eecs.umich.edu void squashFromDecode(const TheISA::PCState &newPC, 3398503Sgblack@eecs.umich.edu const DynInstPtr squashInst, 3408503Sgblack@eecs.umich.edu const InstSeqNum seq_num, ThreadID tid); 3412292SN/A 3422292SN/A /** Checks if a thread is stalled. */ 3436221Snate@binkert.org bool checkStall(ThreadID tid) const; 3442292SN/A 3452292SN/A /** Updates overall fetch stage status; to be called at the end of each 3462292SN/A * cycle. */ 3472292SN/A FetchStatus updateFetchStatus(); 3481684SN/A 3491684SN/A public: 3502292SN/A /** Squashes a specific thread and resets the PC. Also tells the CPU to 3512292SN/A * remove any instructions that are not in the ROB. The source of this 3522292SN/A * squash should be the commit stage. 3532292SN/A */ 3548503Sgblack@eecs.umich.edu void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num, 3558503Sgblack@eecs.umich.edu DynInstPtr squashInst, ThreadID tid); 3561684SN/A 3572292SN/A /** Ticks the fetch stage, processing all inputs signals and fetching 3582292SN/A * as many instructions as possible. 3592292SN/A */ 3601684SN/A void tick(); 3611684SN/A 3622292SN/A /** Checks all input signals and updates the status as necessary. 3632292SN/A * @return: Returns if the status has changed due to input signals. 3642292SN/A */ 3656221Snate@binkert.org bool checkSignalsAndUpdate(ThreadID tid); 3661684SN/A 3672292SN/A /** Does the actual fetching of instructions and passing them on to the 3682292SN/A * next stage. 3692292SN/A * @param status_change fetch() sets this variable if there was a status 3702292SN/A * change (ie switching to IcacheMissStall). 3712292SN/A */ 3722292SN/A void fetch(bool &status_change); 3732292SN/A 3749982Satgutier@umich.edu /** Align a PC to the start of a fetch buffer block. */ 3759982Satgutier@umich.edu Addr fetchBufferAlignPC(Addr addr) 3761062SN/A { 3779982Satgutier@umich.edu return (addr & ~(fetchBufferMask)); 3781062SN/A } 3791061SN/A 3808541Sgblack@eecs.umich.edu /** The decoder. */ 3819023Sgblack@eecs.umich.edu TheISA::Decoder *decoder[Impl::MaxThreads]; 3828541Sgblack@eecs.umich.edu 38314195Sgabeblack@google.com MasterPort &getInstPort() { return icachePort; } 38414195Sgabeblack@google.com 3851060SN/A private: 3867764Sgblack@eecs.umich.edu DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst, 3877764Sgblack@eecs.umich.edu StaticInstPtr curMacroop, TheISA::PCState thisPC, 3887764Sgblack@eecs.umich.edu TheISA::PCState nextPC, bool trace); 3897764Sgblack@eecs.umich.edu 3902292SN/A /** Returns the appropriate thread to fetch, given the fetch policy. */ 39113559Snikos.nikoleris@arm.com ThreadID getFetchingThread(); 3922292SN/A 3932292SN/A /** Returns the appropriate thread to fetch using a round robin policy. */ 3946221Snate@binkert.org ThreadID roundRobin(); 3952292SN/A 3962292SN/A /** Returns the appropriate thread to fetch using the IQ count policy. */ 3976221Snate@binkert.org ThreadID iqCount(); 3982292SN/A 3992292SN/A /** Returns the appropriate thread to fetch using the LSQ count policy. */ 4006221Snate@binkert.org ThreadID lsqCount(); 4012292SN/A 4026221Snate@binkert.org /** Returns the appropriate thread to fetch using the branch count 4036221Snate@binkert.org * policy. */ 4046221Snate@binkert.org ThreadID branchCount(); 4052292SN/A 4068462Sgeoffrey.blake@arm.com /** Pipeline the next I-cache access to the current one. */ 4078462Sgeoffrey.blake@arm.com void pipelineIcacheAccesses(ThreadID tid); 4088462Sgeoffrey.blake@arm.com 4098462Sgeoffrey.blake@arm.com /** Profile the reasons of fetch stall. */ 4108462Sgeoffrey.blake@arm.com void profileStall(ThreadID tid); 4118462Sgeoffrey.blake@arm.com 4122292SN/A private: 4132733Sktlim@umich.edu /** Pointer to the O3CPU. */ 4142733Sktlim@umich.edu O3CPU *cpu; 4151060SN/A 4161060SN/A /** Time buffer interface. */ 4171060SN/A TimeBuffer<TimeStruct> *timeBuffer; 4181060SN/A 4191060SN/A /** Wire to get decode's information from backwards time buffer. */ 4201060SN/A typename TimeBuffer<TimeStruct>::wire fromDecode; 4211060SN/A 4221060SN/A /** Wire to get rename's information from backwards time buffer. */ 4231060SN/A typename TimeBuffer<TimeStruct>::wire fromRename; 4241060SN/A 4251060SN/A /** Wire to get iew's information from backwards time buffer. */ 4261060SN/A typename TimeBuffer<TimeStruct>::wire fromIEW; 4271060SN/A 4281060SN/A /** Wire to get commit's information from backwards time buffer. */ 4291060SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 4301060SN/A 4311060SN/A //Might be annoying how this name is different than the queue. 4321060SN/A /** Wire used to write any information heading to decode. */ 4331060SN/A typename TimeBuffer<FetchStruct>::wire toDecode; 4341060SN/A 4351061SN/A /** BPredUnit. */ 4369480Snilay@cs.wisc.edu BPredUnit *branchPred; 4371061SN/A 4387720Sgblack@eecs.umich.edu TheISA::PCState pc[Impl::MaxThreads]; 4392292SN/A 4407764Sgblack@eecs.umich.edu Addr fetchOffset[Impl::MaxThreads]; 4417764Sgblack@eecs.umich.edu 4427764Sgblack@eecs.umich.edu StaticInstPtr macroop[Impl::MaxThreads]; 4437764Sgblack@eecs.umich.edu 4448314Sgeoffrey.blake@arm.com /** Can the fetch stage redirect from an interrupt on this instruction? */ 4458314Sgeoffrey.blake@arm.com bool delayedCommit[Impl::MaxThreads]; 4468314Sgeoffrey.blake@arm.com 4472678Sktlim@umich.edu /** Memory request used to access cache. */ 4482678Sktlim@umich.edu RequestPtr memReq[Impl::MaxThreads]; 4492292SN/A 4502292SN/A /** Variable that tracks if fetch has written to the time buffer this 4512292SN/A * cycle. Used to tell CPU if there is activity this cycle. 4522292SN/A */ 4532292SN/A bool wroteToTimeBuffer; 4542292SN/A 4552292SN/A /** Tracks how many instructions has been fetched this cycle. */ 4562292SN/A int numInst; 4572292SN/A 4582292SN/A /** Source of possible stalls. */ 4592292SN/A struct Stalls { 4602292SN/A bool decode; 4619444SAndreas.Sandberg@ARM.com bool drain; 4622292SN/A }; 4632292SN/A 4642292SN/A /** Tracks which stages are telling fetch to stall. */ 4652292SN/A Stalls stalls[Impl::MaxThreads]; 4661060SN/A 4679184Sandreas.hansson@arm.com /** Decode to fetch delay. */ 4689184Sandreas.hansson@arm.com Cycles decodeToFetchDelay; 4691060SN/A 4709184Sandreas.hansson@arm.com /** Rename to fetch delay. */ 4719184Sandreas.hansson@arm.com Cycles renameToFetchDelay; 4721060SN/A 4739184Sandreas.hansson@arm.com /** IEW to fetch delay. */ 4749184Sandreas.hansson@arm.com Cycles iewToFetchDelay; 4751060SN/A 4769184Sandreas.hansson@arm.com /** Commit to fetch delay. */ 4779184Sandreas.hansson@arm.com Cycles commitToFetchDelay; 4781060SN/A 4791060SN/A /** The width of fetch in instructions. */ 4801060SN/A unsigned fetchWidth; 4811060SN/A 48210329Smitch.hayenga@arm.com /** The width of decode in instructions. */ 48310329Smitch.hayenga@arm.com unsigned decodeWidth; 48410329Smitch.hayenga@arm.com 4852696Sktlim@umich.edu /** Is the cache blocked? If so no threads can access it. */ 4862696Sktlim@umich.edu bool cacheBlocked; 4872696Sktlim@umich.edu 4882696Sktlim@umich.edu /** The packet that is waiting to be retried. */ 4892696Sktlim@umich.edu PacketPtr retryPkt; 4902696Sktlim@umich.edu 4912696Sktlim@umich.edu /** The thread that is waiting on the cache to tell fetch to retry. */ 4926221Snate@binkert.org ThreadID retryTid; 4932696Sktlim@umich.edu 4941060SN/A /** Cache block size. */ 4959814Sandreas.hansson@arm.com unsigned int cacheBlkSize; 4961060SN/A 4979982Satgutier@umich.edu /** The size of the fetch buffer in bytes. The fetch buffer 4989982Satgutier@umich.edu * itself may be smaller than a cache line. 4999982Satgutier@umich.edu */ 5009982Satgutier@umich.edu unsigned fetchBufferSize; 5011060SN/A 5029982Satgutier@umich.edu /** Mask to align a fetch address to a fetch buffer boundary. */ 5039982Satgutier@umich.edu Addr fetchBufferMask; 5041060SN/A 5059982Satgutier@umich.edu /** The fetch data that is being fetched and buffered. */ 5069982Satgutier@umich.edu uint8_t *fetchBuffer[Impl::MaxThreads]; 5072893Sktlim@umich.edu 5089982Satgutier@umich.edu /** The PC of the first instruction loaded into the fetch buffer. */ 5099982Satgutier@umich.edu Addr fetchBufferPC[Impl::MaxThreads]; 5109982Satgutier@umich.edu 51110329Smitch.hayenga@arm.com /** The size of the fetch queue in micro-ops */ 51210329Smitch.hayenga@arm.com unsigned fetchQueueSize; 51310329Smitch.hayenga@arm.com 51410331Smitch.hayenga@arm.com /** Queue of fetched instructions. Per-thread to prevent HoL blocking. */ 51510331Smitch.hayenga@arm.com std::deque<DynInstPtr> fetchQueue[Impl::MaxThreads]; 51610329Smitch.hayenga@arm.com 5179982Satgutier@umich.edu /** Whether or not the fetch buffer data is valid. */ 5189982Satgutier@umich.edu bool fetchBufferValid[Impl::MaxThreads]; 5192906Sktlim@umich.edu 5201060SN/A /** Size of instructions. */ 5211060SN/A int instSize; 5221060SN/A 5231060SN/A /** Icache stall statistics. */ 5242292SN/A Counter lastIcacheStall[Impl::MaxThreads]; 5251062SN/A 5262292SN/A /** List of Active Threads */ 5276221Snate@binkert.org std::list<ThreadID> *activeThreads; 5282292SN/A 5292292SN/A /** Number of threads. */ 5306221Snate@binkert.org ThreadID numThreads; 5312292SN/A 5322292SN/A /** Number of threads that are actively fetching. */ 5336221Snate@binkert.org ThreadID numFetchingThreads; 5342292SN/A 5352292SN/A /** Thread ID being fetched. */ 5366221Snate@binkert.org ThreadID threadFetched; 5372292SN/A 5382348SN/A /** Checks if there is an interrupt pending. If there is, fetch 5392348SN/A * must stop once it is not fetching PAL instructions. 5402348SN/A */ 5412292SN/A bool interruptPending; 5422292SN/A 54314195Sgabeblack@google.com /** Instruction port. Note that it has to appear after the fetch stage. */ 54414195Sgabeblack@google.com IcachePort icachePort; 54514195Sgabeblack@google.com 5468462Sgeoffrey.blake@arm.com /** Set to true if a pipelined I-cache request should be issued. */ 5478462Sgeoffrey.blake@arm.com bool issuePipelinedIfetch[Impl::MaxThreads]; 5488462Sgeoffrey.blake@arm.com 5498462Sgeoffrey.blake@arm.com /** Event used to delay fault generation of translation faults */ 5508462Sgeoffrey.blake@arm.com FinishTranslationEvent finishTranslationEvent; 5518462Sgeoffrey.blake@arm.com 5522292SN/A // @todo: Consider making these vectors and tracking on a per thread basis. 5532292SN/A /** Stat for total number of cycles stalled due to an icache miss. */ 5545999Snate@binkert.org Stats::Scalar icacheStallCycles; 5552292SN/A /** Stat for total number of fetched instructions. */ 5565999Snate@binkert.org Stats::Scalar fetchedInsts; 5572727Sktlim@umich.edu /** Total number of fetched branches. */ 5585999Snate@binkert.org Stats::Scalar fetchedBranches; 5592292SN/A /** Stat for total number of predicted branches. */ 5605999Snate@binkert.org Stats::Scalar predictedBranches; 5612292SN/A /** Stat for total number of cycles spent fetching. */ 5625999Snate@binkert.org Stats::Scalar fetchCycles; 5632292SN/A /** Stat for total number of cycles spent squashing. */ 5645999Snate@binkert.org Stats::Scalar fetchSquashCycles; 5657849SAli.Saidi@ARM.com /** Stat for total number of cycles spent waiting for translation */ 5667849SAli.Saidi@ARM.com Stats::Scalar fetchTlbCycles; 5672292SN/A /** Stat for total number of cycles spent blocked due to other stages in 5682292SN/A * the pipeline. 5692292SN/A */ 5705999Snate@binkert.org Stats::Scalar fetchIdleCycles; 5712348SN/A /** Total number of cycles spent blocked. */ 5725999Snate@binkert.org Stats::Scalar fetchBlockedCycles; 5732348SN/A /** Total number of cycles spent in any other state. */ 5745999Snate@binkert.org Stats::Scalar fetchMiscStallCycles; 5758462Sgeoffrey.blake@arm.com /** Total number of cycles spent in waiting for drains. */ 5768462Sgeoffrey.blake@arm.com Stats::Scalar fetchPendingDrainCycles; 5778462Sgeoffrey.blake@arm.com /** Total number of stall cycles caused by no active threads to run. */ 5788462Sgeoffrey.blake@arm.com Stats::Scalar fetchNoActiveThreadStallCycles; 5798462Sgeoffrey.blake@arm.com /** Total number of stall cycles caused by pending traps. */ 5808462Sgeoffrey.blake@arm.com Stats::Scalar fetchPendingTrapStallCycles; 5818462Sgeoffrey.blake@arm.com /** Total number of stall cycles caused by pending quiesce instructions. */ 5828462Sgeoffrey.blake@arm.com Stats::Scalar fetchPendingQuiesceStallCycles; 5838462Sgeoffrey.blake@arm.com /** Total number of stall cycles caused by I-cache wait retrys. */ 5848462Sgeoffrey.blake@arm.com Stats::Scalar fetchIcacheWaitRetryStallCycles; 5852292SN/A /** Stat for total number of fetched cache lines. */ 5865999Snate@binkert.org Stats::Scalar fetchedCacheLines; 5872348SN/A /** Total number of outstanding icache accesses that were dropped 5882348SN/A * due to a squash. 5892348SN/A */ 5905999Snate@binkert.org Stats::Scalar fetchIcacheSquashes; 5918064SAli.Saidi@ARM.com /** Total number of outstanding tlb accesses that were dropped 5928064SAli.Saidi@ARM.com * due to a squash. 5938064SAli.Saidi@ARM.com */ 5948064SAli.Saidi@ARM.com Stats::Scalar fetchTlbSquashes; 5952292SN/A /** Distribution of number of instructions fetched each cycle. */ 5965999Snate@binkert.org Stats::Distribution fetchNisnDist; 5972348SN/A /** Rate of how often fetch was idle. */ 5982292SN/A Stats::Formula idleRate; 5992348SN/A /** Number of branch fetches per cycle. */ 6002292SN/A Stats::Formula branchRate; 6012348SN/A /** Number of instruction fetched per cycle. */ 6022292SN/A Stats::Formula fetchRate; 6031060SN/A}; 6041060SN/A 6052292SN/A#endif //__CPU_O3_FETCH_HH__ 606