| /gem5/src/cpu/ |
| H A D | inst_seq.hh | 40 typedef uint64_t InstSeqNum; typedef
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| H A D | base_dyn_inst_impl.hh | 65 InstSeqNum seq_num, ImplCPU *cpu)
173 std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
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| /gem5/src/cpu/o3/ |
| H A D | store_set.hh | 43 bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
87 void insertLoad(Addr load_PC, InstSeqNum load_seq_num);
91 void insertStore(Addr store_PC, InstSeqNum store_seq_num, ThreadID tid);
97 InstSeqNum checkInst(Addr PC);
100 void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store);
103 void squash(InstSeqNum squashed_num, ThreadID tid);
127 std::vector<InstSeqNum> LFST;
135 std::map<InstSeqNum, int, ltseqnum> storeList;
137 typedef std::map<InstSeqNum, in
[all...] |
| H A D | mem_dep_unit.hh | 56 size_t operator() (const InstSeqNum &seq_num) const {
155 void squash(const InstSeqNum &squashed_num, ThreadID tid);
242 typedef std::unordered_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash;
265 InstSeqNum loadBarrierSN;
269 InstSeqNum storeBarrierSN;
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| H A D | comm.hh | 64 InstSeqNum fetchFaultSN;
98 InstSeqNum squashedSeqNum[Impl::MaxThreads];
124 InstSeqNum doneSeqNum;
190 InstSeqNum nonSpecSeqNum; // *I
195 InstSeqNum doneSeqNum; // *F, I
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| H A D | rob.hh | 128 DynInstPtr findInst(ThreadID tid, InstSeqNum squash_inst);
201 void squash(InstSeqNum squash_num, ThreadID tid);
222 // InstSeqNum readHeadSeqNum();
226 // InstSeqNum readHeadSeqNum(ThreadID tid);
235 // InstSeqNum readTailSeqNum();
238 // InstSeqNum readTailSeqNum(ThreadID tid);
321 InstSeqNum squashedSeqNum[Impl::MaxThreads];
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| H A D | inst_queue.hh | 222 void scheduleNonSpec(const InstSeqNum &inst);
228 void commit(const InstSeqNum &inst, ThreadID tid = 0);
363 std::map<InstSeqNum, DynInstPtr> nonSpecInsts;
365 typedef typename std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt;
370 InstSeqNum oldestInst;
443 InstSeqNum squashedSeqNum[Impl::MaxThreads];
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| H A D | rename.hh | 122 typedef typename std::pair<InstSeqNum, PhysRegIdPtr> SeqNumRegPair;
197 void squash(const InstSeqNum &squash_seq_num, ThreadID tid);
252 void doSquash(const InstSeqNum &squash_seq_num, ThreadID tid);
255 void removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid);
304 RenameHistory(InstSeqNum _instSeqNum, const RegId& _archReg,
313 InstSeqNum instSeqNum;
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| H A D | store_set.cc | 201 StoreSet::insertLoad(Addr load_PC, InstSeqNum load_seq_num)
209 StoreSet::insertStore(Addr store_PC, InstSeqNum store_seq_num, ThreadID tid)
238 InstSeqNum
274 StoreSet::issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store)
311 StoreSet::squash(InstSeqNum squashed_num, ThreadID tid)
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| H A D | mem_dep_unit_impl.hh | 182 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
193 InstSeqNum producing_store;
279 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
309 InstSeqNum barr_sn = barr_inst->seqNum;
330 std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
436 InstSeqNum barr_sn = inst->seqNum;
486 MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
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| H A D | lsq_unit.hh | 277 void commitLoads(InstSeqNum &youngest_inst);
280 void commitStores(InstSeqNum &youngest_inst);
290 void squash(const InstSeqNum &squashed_num);
512 InstSeqNum stallingStoreIsn;
583 InstSeqNum
594 InstSeqNum
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| /gem5/src/cpu/minor/ |
| H A D | dyn_inst.hh | 75 static const InstSeqNum firstStreamSeqNum = 1;
76 static const InstSeqNum firstPredictionSeqNum = 1;
77 static const InstSeqNum firstLineSeqNum = 1;
78 static const InstSeqNum firstFetchSeqNum = 1;
79 static const InstSeqNum firstExecSeqNum = 1;
88 InstSeqNum streamSeqNum;
92 InstSeqNum predictionSeqNum;
96 InstSeqNum lineSeqNum;
100 InstSeqNum fetchSeqNum;
105 InstSeqNum execSeqNu
[all...] |
| H A D | pipe_data.hh | 117 InstSeqNum newStreamSeqNum;
118 InstSeqNum newPredictionSeqNum;
136 InstSeqNum new_stream_seq_num,
137 InstSeqNum new_prediction_seq_num,
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| H A D | fetch2.hh | 144 InstSeqNum lastStreamSeqNum;
148 InstSeqNum fetchSeqNum;
154 InstSeqNum expectedStreamSeqNum;
159 InstSeqNum predictionSeqNum;
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| H A D | scoreboard.hh | 91 std::vector<InstSeqNum> writingInst;
128 InstSeqNum execSeqNumToWaitFor(MinorDynInstPtr inst,
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| H A D | dyn_inst.cc | 56 const InstSeqNum InstId::firstStreamSeqNum;
57 const InstSeqNum InstId::firstPredictionSeqNum;
58 const InstSeqNum InstId::firstLineSeqNum;
59 const InstSeqNum InstId::firstFetchSeqNum;
60 const InstSeqNum InstId::firstExecSeqNum;
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| H A D | fetch1.hh | 268 InstSeqNum streamSeqNum;
274 InstSeqNum predictionSeqNum;
308 InstSeqNum lineSeqNum;
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| H A D | decode.hh | 121 InstSeqNum execSeqNum;
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| H A D | execute.hh | 188 InstSeqNum streamSeqNum;
194 InstSeqNum lastPredictionSeqNum;
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| /gem5/src/cpu/pred/ |
| H A D | indirect.hh | 54 InstSeqNum seq_num, ThreadID tid) = 0;
55 virtual void commit(InstSeqNum seq_num, ThreadID tid,
57 virtual void squash(InstSeqNum seq_num, ThreadID tid) = 0;
58 virtual void recordTarget(InstSeqNum seq_num, void * indirect_history,
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| H A D | simple_indirect.hh | 48 void recordIndirect(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num,
50 void commit(InstSeqNum seq_num, ThreadID tid, void * indirect_history);
51 void squash(InstSeqNum seq_num, ThreadID tid);
52 void recordTarget(InstSeqNum seq_num, void * indirect_history,
85 HistoryEntry(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num)
89 InstSeqNum seqNum;
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| H A D | bpred_unit.hh | 94 bool predict(const StaticInstPtr &inst, const InstSeqNum &seqNum,
106 void update(const InstSeqNum &done_sn, ThreadID tid);
114 void squash(const InstSeqNum &squashed_sn, ThreadID tid);
125 void squash(const InstSeqNum &squashed_sn,
204 PredictorHistory(const InstSeqNum &seq_num, Addr instPC,
220 InstSeqNum seqNum;
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| H A D | simple_indirect.cc | 115 InstSeqNum seq_num, ThreadID tid)
123 SimpleIndirectPredictor::commit(InstSeqNum seq_num, ThreadID tid,
146 SimpleIndirectPredictor::squash(InstSeqNum seq_num, ThreadID tid)
176 InstSeqNum seq_num, void * indirect_history, const TheISA::PCState& target,
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| /gem5/src/cpu/o3/probe/ |
| H A D | elastic_trace.hh | 94 typedef typename std::pair<InstSeqNum, PhysRegIndex> SeqNumRegPair;
217 std::set<InstSeqNum> physRegDepSet;
234 std::unordered_map<InstSeqNum, InstExecInfo*> tempStore;
240 InstSeqNum lastClearedSeqNum;
247 std::unordered_map<PhysRegIndex, InstSeqNum> physRegDepMap;
266 InstSeqNum instNum;
278 std::list<InstSeqNum> robDepList;
280 std::list<InstSeqNum> physRegDepList;
340 std::unordered_map<InstSeqNum, TraceInfo*> traceInfoMap;
363 const InstSeqNum startTraceIns
[all...] |
| /gem5/src/sim/ |
| H A D | insttracer.hh | 109 InstSeqNum fetch_seq;
115 InstSeqNum cp_seq;
216 void setFetchSeq(InstSeqNum seq)
219 void setCPSeq(InstSeqNum seq)
242 InstSeqNum getFetchSeq() const { return fetch_seq; }
245 InstSeqNum getCpSeq() const { return cp_seq; }
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