1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_STORE_SET_HH__
32#define __CPU_O3_STORE_SET_HH__
33
34#include <list>
35#include <map>
36#include <utility>
37#include <vector>
38
39#include "base/types.hh"
40#include "cpu/inst_seq.hh"
41
42struct ltseqnum {
43    bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
44    {
45        return lhs > rhs;
46    }
47};
48
49/**
50 * Implements a store set predictor for determining if memory
51 * instructions are dependent upon each other.  See paper "Memory
52 * Dependence Prediction using Store Sets" by Chrysos and Emer.  SSID
53 * stands for Store Set ID, SSIT stands for Store Set ID Table, and
54 * LFST is Last Fetched Store Table.
55 */
56class StoreSet
57{
58  public:
59    typedef unsigned SSID;
60
61  public:
62    /** Default constructor.  init() must be called prior to use. */
63    StoreSet() { };
64
65    /** Creates store set predictor with given table sizes. */
66    StoreSet(uint64_t clear_period, int SSIT_size, int LFST_size);
67
68    /** Default destructor. */
69    ~StoreSet();
70
71    /** Initializes the store set predictor with the given table sizes. */
72    void init(uint64_t clear_period, int SSIT_size, int LFST_size);
73
74    /** Records a memory ordering violation between the younger load
75     * and the older store. */
76    void violation(Addr store_PC, Addr load_PC);
77
78    /** Clears the store set predictor every so often so that all the
79     * entries aren't used and stores are constantly predicted as
80     * conflicting.
81     */
82    void checkClear();
83
84    /** Inserts a load into the store set predictor.  This does nothing but
85     * is included in case other predictors require a similar function.
86     */
87    void insertLoad(Addr load_PC, InstSeqNum load_seq_num);
88
89    /** Inserts a store into the store set predictor.  Updates the
90     * LFST if the store has a valid SSID. */
91    void insertStore(Addr store_PC, InstSeqNum store_seq_num, ThreadID tid);
92
93    /** Checks if the instruction with the given PC is dependent upon
94     * any store.  @return Returns the sequence number of the store
95     * instruction this PC is dependent upon.  Returns 0 if none.
96     */
97    InstSeqNum checkInst(Addr PC);
98
99    /** Records this PC/sequence number as issued. */
100    void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store);
101
102    /** Squashes for a specific thread until the given sequence number. */
103    void squash(InstSeqNum squashed_num, ThreadID tid);
104
105    /** Resets all tables. */
106    void clear();
107
108    /** Debug function to dump the contents of the store list. */
109    void dump();
110
111  private:
112    /** Calculates the index into the SSIT based on the PC. */
113    inline int calcIndex(Addr PC)
114    { return (PC >> offsetBits) & indexMask; }
115
116    /** Calculates a Store Set ID based on the PC. */
117    inline SSID calcSSID(Addr PC)
118    { return ((PC ^ (PC >> 10)) % LFSTSize); }
119
120    /** The Store Set ID Table. */
121    std::vector<SSID> SSIT;
122
123    /** Bit vector to tell if the SSIT has a valid entry. */
124    std::vector<bool> validSSIT;
125
126    /** Last Fetched Store Table. */
127    std::vector<InstSeqNum> LFST;
128
129    /** Bit vector to tell if the LFST has a valid entry. */
130    std::vector<bool> validLFST;
131
132    /** Map of stores that have been inserted into the store set, but
133     * not yet issued or squashed.
134     */
135    std::map<InstSeqNum, int, ltseqnum> storeList;
136
137    typedef std::map<InstSeqNum, int, ltseqnum>::iterator SeqNumMapIt;
138
139    /** Number of loads/stores to process before wiping predictor so all
140     * entries don't get saturated
141     */
142    uint64_t clearPeriod;
143
144    /** Store Set ID Table size, in entries. */
145    int SSITSize;
146
147    /** Last Fetched Store Table size, in entries. */
148    int LFSTSize;
149
150    /** Mask to obtain the index. */
151    int indexMask;
152
153    // HACK: Hardcoded for now.
154    int offsetBits;
155
156    /** Number of memory operations predicted since last clear of predictor */
157    int memOpsPred;
158};
159
160#endif // __CPU_O3_STORE_SET_HH__
161