1/*
2 * Copyright (c) 2014 ARM Limited
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Mitch Hayenga
29 */
30
31#ifndef __CPU_PRED_INDIRECT_BASE_HH__
32#define __CPU_PRED_INDIRECT_BASE_HH__
33
34#include "arch/isa_traits.hh"
35#include "config/the_isa.hh"
36#include "cpu/inst_seq.hh"
37#include "params/IndirectPredictor.hh"
38#include "sim/sim_object.hh"
39
40class IndirectPredictor : public SimObject
41{
42  public:
43
44    typedef IndirectPredictorParams Params;
45
46    IndirectPredictor(const Params *params)
47        : SimObject(params)
48    {
49    }
50
51    virtual bool lookup(Addr br_addr, TheISA::PCState& br_target,
52                        ThreadID tid) = 0;
53    virtual void recordIndirect(Addr br_addr, Addr tgt_addr,
54                                InstSeqNum seq_num, ThreadID tid) = 0;
55    virtual void commit(InstSeqNum seq_num, ThreadID tid,
56                        void * indirect_history) = 0;
57    virtual void squash(InstSeqNum seq_num, ThreadID tid) = 0;
58    virtual void recordTarget(InstSeqNum seq_num, void * indirect_history,
59                              const TheISA::PCState& target, ThreadID tid) = 0;
60    virtual void genIndirectInfo(ThreadID tid, void* & indirect_history) = 0;
61    virtual void updateDirectionInfo(ThreadID tid, bool actually_taken) = 0;
62    virtual void deleteIndirectInfo(ThreadID tid, void * indirect_history) = 0;
63    virtual void changeDirectionPrediction(ThreadID tid,
64                                           void * indirect_history,
65                                           bool actually_taken) = 0;
66};
67
68#endif // __CPU_PRED_INDIRECT_BASE_HH__
69