14776Sgblack@eecs.umich.edu/* 213610Sgiacomo.gabrielli@arm.com * Copyright (c) 2014, 2017 ARM Limited 310665SAli.Saidi@ARM.com * All rights reserved 410665SAli.Saidi@ARM.com * 510665SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 610665SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 710665SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 810665SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 910665SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 1010665SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 1110665SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 1210665SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 1310665SAli.Saidi@ARM.com * 144776Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 154776Sgblack@eecs.umich.edu * All rights reserved. 164776Sgblack@eecs.umich.edu * 174776Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 184776Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 194776Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 204776Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 214776Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 224776Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 234776Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 244776Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 254776Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 264776Sgblack@eecs.umich.edu * this software without specific prior written permission. 274776Sgblack@eecs.umich.edu * 284776Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294776Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304776Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314776Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324776Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334776Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344776Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354776Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364776Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374776Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384776Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394776Sgblack@eecs.umich.edu * 404776Sgblack@eecs.umich.edu * Authors: Steve Reinhardt 414776Sgblack@eecs.umich.edu * Nathan Binkert 424776Sgblack@eecs.umich.edu */ 434776Sgblack@eecs.umich.edu 444776Sgblack@eecs.umich.edu#ifndef __INSTRECORD_HH__ 454776Sgblack@eecs.umich.edu#define __INSTRECORD_HH__ 464776Sgblack@eecs.umich.edu 4713610Sgiacomo.gabrielli@arm.com#include "arch/generic/vec_pred_reg.hh" 4813610Sgiacomo.gabrielli@arm.com#include "arch/generic/vec_reg.hh" 496216Snate@binkert.org#include "base/types.hh" 5011800Sbrandon.potter@amd.com#include "cpu/inst_seq.hh" 514776Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 524776Sgblack@eecs.umich.edu#include "sim/sim_object.hh" 534776Sgblack@eecs.umich.edu 544776Sgblack@eecs.umich.educlass ThreadContext; 554776Sgblack@eecs.umich.edu 564776Sgblack@eecs.umich.edunamespace Trace { 574776Sgblack@eecs.umich.edu 584776Sgblack@eecs.umich.educlass InstRecord 594776Sgblack@eecs.umich.edu{ 604776Sgblack@eecs.umich.edu protected: 614776Sgblack@eecs.umich.edu Tick when; 624776Sgblack@eecs.umich.edu 634776Sgblack@eecs.umich.edu // The following fields are initialized by the constructor and 644776Sgblack@eecs.umich.edu // thus guaranteed to be valid. 654776Sgblack@eecs.umich.edu ThreadContext *thread; 664776Sgblack@eecs.umich.edu // need to make this ref-counted so it doesn't go away before we 674776Sgblack@eecs.umich.edu // dump the record 684776Sgblack@eecs.umich.edu StaticInstPtr staticInst; 697720Sgblack@eecs.umich.edu TheISA::PCState pc; 705784Sgblack@eecs.umich.edu StaticInstPtr macroStaticInst; 714776Sgblack@eecs.umich.edu 724776Sgblack@eecs.umich.edu // The remaining fields are only valid for particular instruction 734776Sgblack@eecs.umich.edu // types (e.g, addresses for memory ops) or when particular 744776Sgblack@eecs.umich.edu // options are enabled (e.g., tracing full register contents). 754776Sgblack@eecs.umich.edu // Each data field has an associated valid flag to indicate 764776Sgblack@eecs.umich.edu // whether the data field is valid. 774776Sgblack@eecs.umich.edu 7810665SAli.Saidi@ARM.com /*** @defgroup mem 7910665SAli.Saidi@ARM.com * @{ 8010665SAli.Saidi@ARM.com * Memory request information in the instruction accessed memory. 8110665SAli.Saidi@ARM.com * @see mem_valid 8210665SAli.Saidi@ARM.com */ 8310665SAli.Saidi@ARM.com Addr addr; ///< The address that was accessed 8410665SAli.Saidi@ARM.com Addr size; ///< The size of the memory request 8510665SAli.Saidi@ARM.com unsigned flags; ///< The flags that were assigned to the request. 8610665SAli.Saidi@ARM.com 8710665SAli.Saidi@ARM.com /** @} */ 8810665SAli.Saidi@ARM.com 8910665SAli.Saidi@ARM.com /** @defgroup data 9010665SAli.Saidi@ARM.com * If this instruction wrote any data values they're recorded here 9110665SAli.Saidi@ARM.com * WARNING: Instructions are quite loose with with what they write 9210665SAli.Saidi@ARM.com * since many instructions write multiple values (e.g. destintation 9310665SAli.Saidi@ARM.com * register, flags, status, ...) This only captures the last write. 9410665SAli.Saidi@ARM.com * @TODO fix this and record all destintations that an instruction writes 9510665SAli.Saidi@ARM.com * @see data_status 9610665SAli.Saidi@ARM.com */ 974776Sgblack@eecs.umich.edu union { 984776Sgblack@eecs.umich.edu uint64_t as_int; 994776Sgblack@eecs.umich.edu double as_double; 10013610Sgiacomo.gabrielli@arm.com ::VecRegContainer<TheISA::VecRegSizeBytes>* as_vec; 10113610Sgiacomo.gabrielli@arm.com ::VecPredRegContainer<TheISA::VecPredRegSizeBits, 10213610Sgiacomo.gabrielli@arm.com TheISA::VecPredRegHasPackedRepr>* as_pred; 1034776Sgblack@eecs.umich.edu } data; 10410665SAli.Saidi@ARM.com 10510665SAli.Saidi@ARM.com /** @defgroup fetch_seq 10610665SAli.Saidi@ARM.com * This records the serial number that the instruction was fetched in. 10710665SAli.Saidi@ARM.com * @see fetch_seq_valid 10810665SAli.Saidi@ARM.com */ 10910665SAli.Saidi@ARM.com InstSeqNum fetch_seq; 11010665SAli.Saidi@ARM.com 11110665SAli.Saidi@ARM.com /** @defgroup commit_seq 11210665SAli.Saidi@ARM.com * This records the instruction number that was committed in the pipeline 11310665SAli.Saidi@ARM.com * @see cp_seq_valid 11410665SAli.Saidi@ARM.com */ 11510665SAli.Saidi@ARM.com InstSeqNum cp_seq; 11610665SAli.Saidi@ARM.com 11710665SAli.Saidi@ARM.com /** @ingroup data 11810665SAli.Saidi@ARM.com * What size of data was written? 11910665SAli.Saidi@ARM.com */ 12012386Sgabeblack@google.com enum DataStatus { 1214776Sgblack@eecs.umich.edu DataInvalid = 0, 1225543Ssaidi@eecs.umich.edu DataInt8 = 1, // set to equal number of bytes 1234776Sgblack@eecs.umich.edu DataInt16 = 2, 1244776Sgblack@eecs.umich.edu DataInt32 = 4, 1254776Sgblack@eecs.umich.edu DataInt64 = 8, 12613610Sgiacomo.gabrielli@arm.com DataDouble = 3, 12713610Sgiacomo.gabrielli@arm.com DataVec = 5, 12813610Sgiacomo.gabrielli@arm.com DataVecPred = 6 1294776Sgblack@eecs.umich.edu } data_status; 1304776Sgblack@eecs.umich.edu 13110665SAli.Saidi@ARM.com /** @ingroup memory 13210665SAli.Saidi@ARM.com * Are the memory fields in the record valid? 13310665SAli.Saidi@ARM.com */ 13410665SAli.Saidi@ARM.com bool mem_valid; 13510665SAli.Saidi@ARM.com 13610665SAli.Saidi@ARM.com /** @ingroup fetch_seq 13710665SAli.Saidi@ARM.com * Are the fetch sequence number fields valid? 13810665SAli.Saidi@ARM.com */ 1394776Sgblack@eecs.umich.edu bool fetch_seq_valid; 14010665SAli.Saidi@ARM.com /** @ingroup commit_seq 14110665SAli.Saidi@ARM.com * Are the commit sequence number fields valid? 14210665SAli.Saidi@ARM.com */ 14310665SAli.Saidi@ARM.com bool cp_seq_valid; 1444776Sgblack@eecs.umich.edu 14510665SAli.Saidi@ARM.com /** is the predicate for execution this inst true or false (not execed)? 14610665SAli.Saidi@ARM.com */ 14710665SAli.Saidi@ARM.com bool predicate; 1484776Sgblack@eecs.umich.edu 1494776Sgblack@eecs.umich.edu public: 1504776Sgblack@eecs.umich.edu InstRecord(Tick _when, ThreadContext *_thread, 1515784Sgblack@eecs.umich.edu const StaticInstPtr _staticInst, 15210664SAli.Saidi@ARM.com TheISA::PCState _pc, 1537720Sgblack@eecs.umich.edu const StaticInstPtr _macroStaticInst = NULL) 15410665SAli.Saidi@ARM.com : when(_when), thread(_thread), staticInst(_staticInst), pc(_pc), 15510665SAli.Saidi@ARM.com macroStaticInst(_macroStaticInst), addr(0), size(0), flags(0), 15610665SAli.Saidi@ARM.com fetch_seq(0), cp_seq(0), data_status(DataInvalid), mem_valid(false), 15710665SAli.Saidi@ARM.com fetch_seq_valid(false), cp_seq_valid(false), predicate(true) 15810665SAli.Saidi@ARM.com { } 1594776Sgblack@eecs.umich.edu 16013610Sgiacomo.gabrielli@arm.com virtual ~InstRecord() 16113610Sgiacomo.gabrielli@arm.com { 16213610Sgiacomo.gabrielli@arm.com if (data_status == DataVec) { 16313610Sgiacomo.gabrielli@arm.com assert(data.as_vec); 16413610Sgiacomo.gabrielli@arm.com delete data.as_vec; 16513610Sgiacomo.gabrielli@arm.com } else if (data_status == DataVecPred) { 16613610Sgiacomo.gabrielli@arm.com assert(data.as_pred); 16713610Sgiacomo.gabrielli@arm.com delete data.as_pred; 16813610Sgiacomo.gabrielli@arm.com } 16913610Sgiacomo.gabrielli@arm.com } 1704776Sgblack@eecs.umich.edu 17110198SAndrew.Bardsley@arm.com void setWhen(Tick new_when) { when = new_when; } 17210665SAli.Saidi@ARM.com void setMem(Addr a, Addr s, unsigned f) 17310665SAli.Saidi@ARM.com { 17410665SAli.Saidi@ARM.com addr = a; size = s; flags = f; mem_valid = true; 17510665SAli.Saidi@ARM.com } 1764776Sgblack@eecs.umich.edu 17712386Sgabeblack@google.com template <typename T, size_t N> 17812386Sgabeblack@google.com void 17912386Sgabeblack@google.com setData(std::array<T, N> d) 18012386Sgabeblack@google.com { 18112386Sgabeblack@google.com data.as_int = d[0]; 18212386Sgabeblack@google.com data_status = (DataStatus)sizeof(T); 18312386Sgabeblack@google.com static_assert(sizeof(T) == DataInt8 || sizeof(T) == DataInt16 || 18412386Sgabeblack@google.com sizeof(T) == DataInt32 || sizeof(T) == DataInt64, 18512386Sgabeblack@google.com "Type T has an unrecognized size."); 18612386Sgabeblack@google.com } 18712386Sgabeblack@google.com 1884776Sgblack@eecs.umich.edu void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; } 1894776Sgblack@eecs.umich.edu void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; } 1904776Sgblack@eecs.umich.edu void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; } 1914776Sgblack@eecs.umich.edu void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; } 1924776Sgblack@eecs.umich.edu 1934776Sgblack@eecs.umich.edu void setData(int64_t d) { setData((uint64_t)d); } 1944776Sgblack@eecs.umich.edu void setData(int32_t d) { setData((uint32_t)d); } 1954776Sgblack@eecs.umich.edu void setData(int16_t d) { setData((uint16_t)d); } 1964776Sgblack@eecs.umich.edu void setData(int8_t d) { setData((uint8_t)d); } 1974776Sgblack@eecs.umich.edu 1984776Sgblack@eecs.umich.edu void setData(double d) { data.as_double = d; data_status = DataDouble; } 1994776Sgblack@eecs.umich.edu 20013610Sgiacomo.gabrielli@arm.com void 20113610Sgiacomo.gabrielli@arm.com setData(::VecRegContainer<TheISA::VecRegSizeBytes>& d) 20213610Sgiacomo.gabrielli@arm.com { 20313610Sgiacomo.gabrielli@arm.com data.as_vec = new ::VecRegContainer<TheISA::VecRegSizeBytes>(d); 20413610Sgiacomo.gabrielli@arm.com data_status = DataVec; 20513610Sgiacomo.gabrielli@arm.com } 20613610Sgiacomo.gabrielli@arm.com 20713610Sgiacomo.gabrielli@arm.com void 20813610Sgiacomo.gabrielli@arm.com setData(::VecPredRegContainer<TheISA::VecPredRegSizeBits, 20913610Sgiacomo.gabrielli@arm.com TheISA::VecPredRegHasPackedRepr>& d) 21013610Sgiacomo.gabrielli@arm.com { 21113610Sgiacomo.gabrielli@arm.com data.as_pred = new ::VecPredRegContainer< 21213610Sgiacomo.gabrielli@arm.com TheISA::VecPredRegSizeBits, TheISA::VecPredRegHasPackedRepr>(d); 21313610Sgiacomo.gabrielli@arm.com data_status = DataVecPred; 21413610Sgiacomo.gabrielli@arm.com } 21513610Sgiacomo.gabrielli@arm.com 2164776Sgblack@eecs.umich.edu void setFetchSeq(InstSeqNum seq) 2174776Sgblack@eecs.umich.edu { fetch_seq = seq; fetch_seq_valid = true; } 2184776Sgblack@eecs.umich.edu 2194776Sgblack@eecs.umich.edu void setCPSeq(InstSeqNum seq) 2204776Sgblack@eecs.umich.edu { cp_seq = seq; cp_seq_valid = true; } 2214776Sgblack@eecs.umich.edu 2227600Sminkyu.jeong@arm.com void setPredicate(bool val) { predicate = val; } 2237600Sminkyu.jeong@arm.com 2244776Sgblack@eecs.umich.edu virtual void dump() = 0; 22511320Ssteve.reinhardt@amd.com 2266364Sgblack@eecs.umich.edu public: 22710665SAli.Saidi@ARM.com Tick getWhen() const { return when; } 22810665SAli.Saidi@ARM.com ThreadContext *getThread() const { return thread; } 22910665SAli.Saidi@ARM.com StaticInstPtr getStaticInst() const { return staticInst; } 23010665SAli.Saidi@ARM.com TheISA::PCState getPCState() const { return pc; } 23110665SAli.Saidi@ARM.com StaticInstPtr getMacroStaticInst() const { return macroStaticInst; } 2326364Sgblack@eecs.umich.edu 23310665SAli.Saidi@ARM.com Addr getAddr() const { return addr; } 23410665SAli.Saidi@ARM.com Addr getSize() const { return size; } 23510665SAli.Saidi@ARM.com unsigned getFlags() const { return flags; } 23610665SAli.Saidi@ARM.com bool getMemValid() const { return mem_valid; } 2376364Sgblack@eecs.umich.edu 23810665SAli.Saidi@ARM.com uint64_t getIntData() const { return data.as_int; } 23910665SAli.Saidi@ARM.com double getFloatData() const { return data.as_double; } 24010665SAli.Saidi@ARM.com int getDataStatus() const { return data_status; } 2416364Sgblack@eecs.umich.edu 24210665SAli.Saidi@ARM.com InstSeqNum getFetchSeq() const { return fetch_seq; } 24310665SAli.Saidi@ARM.com bool getFetchSeqValid() const { return fetch_seq_valid; } 2446364Sgblack@eecs.umich.edu 24510665SAli.Saidi@ARM.com InstSeqNum getCpSeq() const { return cp_seq; } 24610665SAli.Saidi@ARM.com bool getCpSeqValid() const { return cp_seq_valid; } 2474776Sgblack@eecs.umich.edu}; 2484776Sgblack@eecs.umich.edu 2494776Sgblack@eecs.umich.educlass InstTracer : public SimObject 2504776Sgblack@eecs.umich.edu{ 2514776Sgblack@eecs.umich.edu public: 2525034Smilesck@eecs.umich.edu InstTracer(const Params *p) : SimObject(p) 2534776Sgblack@eecs.umich.edu {} 2544776Sgblack@eecs.umich.edu 2554776Sgblack@eecs.umich.edu virtual ~InstTracer() 2564776Sgblack@eecs.umich.edu {}; 2574776Sgblack@eecs.umich.edu 2584776Sgblack@eecs.umich.edu virtual InstRecord * 2594776Sgblack@eecs.umich.edu getInstRecord(Tick when, ThreadContext *tc, 2607720Sgblack@eecs.umich.edu const StaticInstPtr staticInst, TheISA::PCState pc, 2617720Sgblack@eecs.umich.edu const StaticInstPtr macroStaticInst = NULL) = 0; 2624776Sgblack@eecs.umich.edu}; 2634776Sgblack@eecs.umich.edu 2644776Sgblack@eecs.umich.edu 2654776Sgblack@eecs.umich.edu 2667811Ssteve.reinhardt@amd.com} // namespace Trace 2674776Sgblack@eecs.umich.edu 2684776Sgblack@eecs.umich.edu#endif // __INSTRECORD_HH__ 269