1/*
2 * Copyright (c) 2014, 2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 *          Nathan Binkert
42 */
43
44#ifndef __INSTRECORD_HH__
45#define __INSTRECORD_HH__
46
47#include "arch/generic/vec_pred_reg.hh"
48#include "arch/generic/vec_reg.hh"
49#include "base/types.hh"
50#include "cpu/inst_seq.hh"
51#include "cpu/static_inst.hh"
52#include "sim/sim_object.hh"
53
54class ThreadContext;
55
56namespace Trace {
57
58class InstRecord
59{
60  protected:
61    Tick when;
62
63    // The following fields are initialized by the constructor and
64    // thus guaranteed to be valid.
65    ThreadContext *thread;
66    // need to make this ref-counted so it doesn't go away before we
67    // dump the record
68    StaticInstPtr staticInst;
69    TheISA::PCState pc;
70    StaticInstPtr macroStaticInst;
71
72    // The remaining fields are only valid for particular instruction
73    // types (e.g, addresses for memory ops) or when particular
74    // options are enabled (e.g., tracing full register contents).
75    // Each data field has an associated valid flag to indicate
76    // whether the data field is valid.
77
78    /*** @defgroup mem
79     * @{
80     * Memory request information in the instruction accessed memory.
81     * @see mem_valid
82     */
83    Addr addr; ///< The address that was accessed
84    Addr size; ///< The size of the memory request
85    unsigned flags; ///< The flags that were assigned to the request.
86
87    /** @} */
88
89    /** @defgroup data
90     * If this instruction wrote any data values they're recorded here
91     * WARNING: Instructions are quite loose with with what they write
92     * since many instructions write multiple values (e.g. destintation
93     * register, flags, status, ...) This only captures the last write.
94     * @TODO fix this and record all destintations that an instruction writes
95     * @see data_status
96     */
97    union {
98        uint64_t as_int;
99        double as_double;
100        ::VecRegContainer<TheISA::VecRegSizeBytes>* as_vec;
101        ::VecPredRegContainer<TheISA::VecPredRegSizeBits,
102                              TheISA::VecPredRegHasPackedRepr>* as_pred;
103    } data;
104
105    /** @defgroup fetch_seq
106     * This records the serial number that the instruction was fetched in.
107     * @see fetch_seq_valid
108     */
109    InstSeqNum fetch_seq;
110
111    /** @defgroup commit_seq
112     * This records the instruction number that was committed in the pipeline
113     * @see cp_seq_valid
114     */
115    InstSeqNum cp_seq;
116
117    /** @ingroup data
118     * What size of data was written?
119     */
120    enum DataStatus {
121        DataInvalid = 0,
122        DataInt8 = 1,   // set to equal number of bytes
123        DataInt16 = 2,
124        DataInt32 = 4,
125        DataInt64 = 8,
126        DataDouble = 3,
127        DataVec = 5,
128        DataVecPred = 6
129    } data_status;
130
131    /** @ingroup memory
132     * Are the memory fields in the record valid?
133     */
134    bool mem_valid;
135
136    /** @ingroup fetch_seq
137     * Are the fetch sequence number fields valid?
138     */
139    bool fetch_seq_valid;
140    /** @ingroup commit_seq
141     * Are the commit sequence number fields valid?
142     */
143    bool cp_seq_valid;
144
145    /** is the predicate for execution this inst true or false (not execed)?
146     */
147    bool predicate;
148
149  public:
150    InstRecord(Tick _when, ThreadContext *_thread,
151               const StaticInstPtr _staticInst,
152               TheISA::PCState _pc,
153               const StaticInstPtr _macroStaticInst = NULL)
154        : when(_when), thread(_thread), staticInst(_staticInst), pc(_pc),
155        macroStaticInst(_macroStaticInst), addr(0), size(0), flags(0),
156        fetch_seq(0), cp_seq(0), data_status(DataInvalid), mem_valid(false),
157        fetch_seq_valid(false), cp_seq_valid(false), predicate(true)
158    { }
159
160    virtual ~InstRecord()
161    {
162        if (data_status == DataVec) {
163            assert(data.as_vec);
164            delete data.as_vec;
165        } else if (data_status == DataVecPred) {
166            assert(data.as_pred);
167            delete data.as_pred;
168        }
169    }
170
171    void setWhen(Tick new_when) { when = new_when; }
172    void setMem(Addr a, Addr s, unsigned f)
173    {
174        addr = a; size = s; flags = f; mem_valid = true;
175    }
176
177    template <typename T, size_t N>
178    void
179    setData(std::array<T, N> d)
180    {
181        data.as_int = d[0];
182        data_status = (DataStatus)sizeof(T);
183        static_assert(sizeof(T) == DataInt8 || sizeof(T) == DataInt16 ||
184                      sizeof(T) == DataInt32 || sizeof(T) == DataInt64,
185                      "Type T has an unrecognized size.");
186    }
187
188    void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
189    void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
190    void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
191    void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
192
193    void setData(int64_t d) { setData((uint64_t)d); }
194    void setData(int32_t d) { setData((uint32_t)d); }
195    void setData(int16_t d) { setData((uint16_t)d); }
196    void setData(int8_t d)  { setData((uint8_t)d); }
197
198    void setData(double d) { data.as_double = d; data_status = DataDouble; }
199
200    void
201    setData(::VecRegContainer<TheISA::VecRegSizeBytes>& d)
202    {
203        data.as_vec = new ::VecRegContainer<TheISA::VecRegSizeBytes>(d);
204        data_status = DataVec;
205    }
206
207    void
208    setData(::VecPredRegContainer<TheISA::VecPredRegSizeBits,
209                                  TheISA::VecPredRegHasPackedRepr>& d)
210    {
211        data.as_pred = new ::VecPredRegContainer<
212            TheISA::VecPredRegSizeBits, TheISA::VecPredRegHasPackedRepr>(d);
213        data_status = DataVecPred;
214    }
215
216    void setFetchSeq(InstSeqNum seq)
217    { fetch_seq = seq; fetch_seq_valid = true; }
218
219    void setCPSeq(InstSeqNum seq)
220    { cp_seq = seq; cp_seq_valid = true; }
221
222    void setPredicate(bool val) { predicate = val; }
223
224    virtual void dump() = 0;
225
226  public:
227    Tick getWhen() const { return when; }
228    ThreadContext *getThread() const { return thread; }
229    StaticInstPtr getStaticInst() const { return staticInst; }
230    TheISA::PCState getPCState() const { return pc; }
231    StaticInstPtr getMacroStaticInst() const { return macroStaticInst; }
232
233    Addr getAddr() const { return addr; }
234    Addr getSize() const { return size; }
235    unsigned getFlags() const { return flags; }
236    bool getMemValid() const { return mem_valid; }
237
238    uint64_t getIntData() const { return data.as_int; }
239    double getFloatData() const { return data.as_double; }
240    int getDataStatus() const { return data_status; }
241
242    InstSeqNum getFetchSeq() const { return fetch_seq; }
243    bool getFetchSeqValid() const { return fetch_seq_valid; }
244
245    InstSeqNum getCpSeq() const { return cp_seq; }
246    bool getCpSeqValid() const { return cp_seq_valid; }
247};
248
249class InstTracer : public SimObject
250{
251  public:
252    InstTracer(const Params *p) : SimObject(p)
253    {}
254
255    virtual ~InstTracer()
256    {};
257
258    virtual InstRecord *
259        getInstRecord(Tick when, ThreadContext *tc,
260                const StaticInstPtr staticInst, TheISA::PCState pc,
261                const StaticInstPtr macroStaticInst = NULL) = 0;
262};
263
264
265
266} // namespace Trace
267
268#endif // __INSTRECORD_HH__
269