11689SN/A/* 210333Smitch.hayenga@arm.com * Copyright (c) 2012, 2014 ARM Limited 39444SAndreas.Sandberg@ARM.com * All rights reserved 49444SAndreas.Sandberg@ARM.com * 59444SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 69444SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 79444SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 89444SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 99444SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 109444SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 119444SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 129444SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 139444SAndreas.Sandberg@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 411689SN/A */ 421061SN/A 432292SN/A#ifndef __CPU_O3_MEM_DEP_UNIT_HH__ 442292SN/A#define __CPU_O3_MEM_DEP_UNIT_HH__ 451061SN/A 462292SN/A#include <list> 4710473Sandreas.hansson@arm.com#include <memory> 481061SN/A#include <set> 4911168Sandreas.hansson@arm.com#include <unordered_map> 501061SN/A 511684SN/A#include "base/statistics.hh" 521061SN/A#include "cpu/inst_seq.hh" 538232Snate@binkert.org#include "debug/MemDepUnit.hh" 541061SN/A 552292SN/Astruct SNHash { 562292SN/A size_t operator() (const InstSeqNum &seq_num) const { 572292SN/A unsigned a = (unsigned)seq_num; 582292SN/A unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF; 592292SN/A 602292SN/A return hash; 612292SN/A } 622292SN/A}; 632292SN/A 648737Skoansin.tan@gmail.comstruct DerivO3CPUParams; 655529Snate@binkert.org 662292SN/Atemplate <class Impl> 672292SN/Aclass InstructionQueue; 682292SN/A 691061SN/A/** 701061SN/A * Memory dependency unit class. This holds the memory dependence predictor. 711061SN/A * As memory operations are issued to the IQ, they are also issued to this 721061SN/A * unit, which then looks up the prediction as to what they are dependent 731061SN/A * upon. This unit must be checked prior to a memory operation being able 741061SN/A * to issue. Although this is templated, it's somewhat hard to make a generic 751061SN/A * memory dependence unit. This one is mostly for store sets; it will be 761061SN/A * quite limited in what other memory dependence predictions it can also 771061SN/A * utilize. Thus this class should be most likely be rewritten for other 781061SN/A * dependence prediction schemes. 791061SN/A */ 801061SN/Atemplate <class MemDepPred, class Impl> 816005Snate@binkert.orgclass MemDepUnit 826005Snate@binkert.org{ 836005Snate@binkert.org protected: 846005Snate@binkert.org std::string _name; 856005Snate@binkert.org 861061SN/A public: 871061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 8813429Srekai.gonzalezalberquilla@arm.com typedef typename Impl::DynInstConstPtr DynInstConstPtr; 891061SN/A 902292SN/A /** Empty constructor. Must call init() prior to using in this case. */ 913500Sktlim@umich.edu MemDepUnit(); 921061SN/A 932292SN/A /** Constructs a MemDepUnit with given parameters. */ 945529Snate@binkert.org MemDepUnit(DerivO3CPUParams *params); 952292SN/A 962292SN/A /** Frees up any memory allocated. */ 972292SN/A ~MemDepUnit(); 982292SN/A 992292SN/A /** Returns the name of the memory dependence unit. */ 1006005Snate@binkert.org std::string name() const { return _name; } 1012292SN/A 1022292SN/A /** Initializes the unit with parameters and a thread id. */ 1036221Snate@binkert.org void init(DerivO3CPUParams *params, ThreadID tid); 1042292SN/A 1052292SN/A /** Registers statistics. */ 1061062SN/A void regStats(); 1071061SN/A 10810510Smitch.hayenga@arm.com /** Determine if we are drained. */ 10910510Smitch.hayenga@arm.com bool isDrained() const; 11010510Smitch.hayenga@arm.com 1119444SAndreas.Sandberg@ARM.com /** Perform sanity checks after a drain. */ 1129444SAndreas.Sandberg@ARM.com void drainSanityCheck() const; 1132307SN/A 1142348SN/A /** Takes over from another CPU's thread. */ 1152307SN/A void takeOverFrom(); 1162307SN/A 1172292SN/A /** Sets the pointer to the IQ. */ 1182292SN/A void setIQ(InstructionQueue<Impl> *iq_ptr); 1192292SN/A 1202292SN/A /** Inserts a memory instruction. */ 12113429Srekai.gonzalezalberquilla@arm.com void insert(const DynInstPtr &inst); 1221061SN/A 1232292SN/A /** Inserts a non-speculative memory instruction. */ 12413429Srekai.gonzalezalberquilla@arm.com void insertNonSpec(const DynInstPtr &inst); 1251062SN/A 1262292SN/A /** Inserts a barrier instruction. */ 12713429Srekai.gonzalezalberquilla@arm.com void insertBarrier(const DynInstPtr &barr_inst); 1281684SN/A 1292292SN/A /** Indicate that an instruction has its registers ready. */ 13013429Srekai.gonzalezalberquilla@arm.com void regsReady(const DynInstPtr &inst); 1311062SN/A 1322292SN/A /** Indicate that a non-speculative instruction is ready. */ 13313429Srekai.gonzalezalberquilla@arm.com void nonSpecInstReady(const DynInstPtr &inst); 1341061SN/A 1352292SN/A /** Reschedules an instruction to be re-executed. */ 13613429Srekai.gonzalezalberquilla@arm.com void reschedule(const DynInstPtr &inst); 1372292SN/A 1382292SN/A /** Replays all instructions that have been rescheduled by moving them to 1392292SN/A * the ready list. 1402292SN/A */ 14110333Smitch.hayenga@arm.com void replay(); 1422292SN/A 1432292SN/A /** Completes a memory instruction. */ 14413429Srekai.gonzalezalberquilla@arm.com void completed(const DynInstPtr &inst); 1452292SN/A 1462292SN/A /** Completes a barrier instruction. */ 14713429Srekai.gonzalezalberquilla@arm.com void completeBarrier(const DynInstPtr &inst); 1482292SN/A 1492292SN/A /** Wakes any dependents of a memory instruction. */ 15013429Srekai.gonzalezalberquilla@arm.com void wakeDependents(const DynInstPtr &inst); 1512292SN/A 1522292SN/A /** Squashes all instructions up until a given sequence number for a 1532292SN/A * specific thread. 1542292SN/A */ 1556221Snate@binkert.org void squash(const InstSeqNum &squashed_num, ThreadID tid); 1562292SN/A 1572292SN/A /** Indicates an ordering violation between a store and a younger load. */ 15813429Srekai.gonzalezalberquilla@arm.com void violation(const DynInstPtr &store_inst, 15913429Srekai.gonzalezalberquilla@arm.com const DynInstPtr &violating_load); 1602292SN/A 1612292SN/A /** Issues the given instruction */ 16213429Srekai.gonzalezalberquilla@arm.com void issue(const DynInstPtr &inst); 1631061SN/A 1642292SN/A /** Debugging function to dump the lists of instructions. */ 1652292SN/A void dumpLists(); 1661062SN/A 1671062SN/A private: 1682292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 1691062SN/A 1702292SN/A class MemDepEntry; 1711062SN/A 17210473Sandreas.hansson@arm.com typedef std::shared_ptr<MemDepEntry> MemDepEntryPtr; 1731062SN/A 1742292SN/A /** Memory dependence entries that track memory operations, marking 1752292SN/A * when the instruction is ready to execute and what instructions depend 1762292SN/A * upon it. 1772292SN/A */ 17810473Sandreas.hansson@arm.com class MemDepEntry { 1792292SN/A public: 1802292SN/A /** Constructs a memory dependence entry. */ 18113429Srekai.gonzalezalberquilla@arm.com MemDepEntry(const DynInstPtr &new_inst) 1822292SN/A : inst(new_inst), regsReady(false), memDepReady(false), 1832292SN/A completed(false), squashed(false) 1842292SN/A { 1852348SN/A#ifdef DEBUG 1862292SN/A ++memdep_count; 1871062SN/A 1882292SN/A DPRINTF(MemDepUnit, "Memory dependency entry created. " 1898516SMrinmoy.Ghosh@arm.com "memdep_count=%i %s\n", memdep_count, inst->pcState()); 1902348SN/A#endif 1912292SN/A } 1921062SN/A 1932292SN/A /** Frees any pointers. */ 1942292SN/A ~MemDepEntry() 1952292SN/A { 1962292SN/A for (int i = 0; i < dependInsts.size(); ++i) { 1972292SN/A dependInsts[i] = NULL; 1982292SN/A } 1992348SN/A#ifdef DEBUG 2002292SN/A --memdep_count; 2012292SN/A 2022292SN/A DPRINTF(MemDepUnit, "Memory dependency entry deleted. " 2038516SMrinmoy.Ghosh@arm.com "memdep_count=%i %s\n", memdep_count, inst->pcState()); 2042348SN/A#endif 2052292SN/A } 2062292SN/A 2072292SN/A /** Returns the name of the memory dependence entry. */ 2082292SN/A std::string name() const { return "memdepentry"; } 2092292SN/A 2102292SN/A /** The instruction being tracked. */ 2112292SN/A DynInstPtr inst; 2122292SN/A 2132292SN/A /** The iterator to the instruction's location inside the list. */ 2142292SN/A ListIt listIt; 2152292SN/A 2162292SN/A /** A vector of any dependent instructions. */ 2172292SN/A std::vector<MemDepEntryPtr> dependInsts; 2182292SN/A 2192292SN/A /** If the registers are ready or not. */ 2202292SN/A bool regsReady; 2212292SN/A /** If all memory dependencies have been satisfied. */ 2222292SN/A bool memDepReady; 2232292SN/A /** If the instruction is completed. */ 2242292SN/A bool completed; 2252292SN/A /** If the instruction is squashed. */ 2262292SN/A bool squashed; 2272292SN/A 2282292SN/A /** For debugging. */ 2292348SN/A#ifdef DEBUG 2302292SN/A static int memdep_count; 2312292SN/A static int memdep_insert; 2322292SN/A static int memdep_erase; 2332348SN/A#endif 2341062SN/A }; 2351062SN/A 2362292SN/A /** Finds the memory dependence entry in the hash map. */ 23713429Srekai.gonzalezalberquilla@arm.com inline MemDepEntryPtr &findInHash(const DynInstConstPtr& inst); 2381062SN/A 2392292SN/A /** Moves an entry to the ready list. */ 2402292SN/A inline void moveToReady(MemDepEntryPtr &ready_inst_entry); 2411062SN/A 24211168Sandreas.hansson@arm.com typedef std::unordered_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash; 2431061SN/A 2442292SN/A typedef typename MemDepHash::iterator MemDepHashIt; 2451061SN/A 2462292SN/A /** A hash map of all memory dependence entries. */ 2472292SN/A MemDepHash memDepHash; 2481062SN/A 2492292SN/A /** A list of all instructions in the memory dependence unit. */ 2502292SN/A std::list<DynInstPtr> instList[Impl::MaxThreads]; 2511062SN/A 2522292SN/A /** A list of all instructions that are going to be replayed. */ 2532292SN/A std::list<DynInstPtr> instsToReplay; 2541061SN/A 2551061SN/A /** The memory dependence predictor. It is accessed upon new 2561061SN/A * instructions being added to the IQ, and responds by telling 2571061SN/A * this unit what instruction the newly added instruction is dependent 2581061SN/A * upon. 2591061SN/A */ 2601061SN/A MemDepPred depPred; 2611061SN/A 2622348SN/A /** Is there an outstanding load barrier that loads must wait on. */ 2632292SN/A bool loadBarrier; 2642348SN/A /** The sequence number of the load barrier. */ 2652292SN/A InstSeqNum loadBarrierSN; 2662348SN/A /** Is there an outstanding store barrier that loads must wait on. */ 2672292SN/A bool storeBarrier; 2682348SN/A /** The sequence number of the store barrier. */ 2692292SN/A InstSeqNum storeBarrierSN; 2702292SN/A 2712292SN/A /** Pointer to the IQ. */ 2722292SN/A InstructionQueue<Impl> *iqPtr; 2732292SN/A 2742292SN/A /** The thread id of this memory dependence unit. */ 2752292SN/A int id; 2762292SN/A 2772292SN/A /** Stat for number of inserted loads. */ 2785999Snate@binkert.org Stats::Scalar insertedLoads; 2792292SN/A /** Stat for number of inserted stores. */ 2805999Snate@binkert.org Stats::Scalar insertedStores; 2812292SN/A /** Stat for number of conflicting loads that had to wait for a store. */ 2825999Snate@binkert.org Stats::Scalar conflictingLoads; 2832292SN/A /** Stat for number of conflicting stores that had to wait for a store. */ 2845999Snate@binkert.org Stats::Scalar conflictingStores; 2851061SN/A}; 2861061SN/A 2872292SN/A#endif // __CPU_O3_MEM_DEP_UNIT_HH__ 288