1/*
2 * Copyright (c) 2013-2014, 2016,2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andrew Bardsley
38 */
39
40#include "cpu/minor/dyn_inst.hh"
41
42#include <iomanip>
43#include <sstream>
44
45#include "arch/isa.hh"
46#include "arch/registers.hh"
47#include "cpu/base.hh"
48#include "cpu/minor/trace.hh"
49#include "cpu/reg_class.hh"
50#include "debug/MinorExecute.hh"
51#include "enums/OpClass.hh"
52
53namespace Minor
54{
55
56const InstSeqNum InstId::firstStreamSeqNum;
57const InstSeqNum InstId::firstPredictionSeqNum;
58const InstSeqNum InstId::firstLineSeqNum;
59const InstSeqNum InstId::firstFetchSeqNum;
60const InstSeqNum InstId::firstExecSeqNum;
61
62std::ostream &
63operator <<(std::ostream &os, const InstId &id)
64{
65    os << id.threadId << '/' << id.streamSeqNum << '.'
66        << id.predictionSeqNum << '/' << id.lineSeqNum;
67
68    /* Not all structures have fetch and exec sequence numbers */
69    if (id.fetchSeqNum != 0) {
70        os << '/' << id.fetchSeqNum;
71        if (id.execSeqNum != 0)
72            os << '.' << id.execSeqNum;
73    }
74
75    return os;
76}
77
78MinorDynInstPtr MinorDynInst::bubbleInst = NULL;
79
80void
81MinorDynInst::init()
82{
83    if (!bubbleInst) {
84        bubbleInst = new MinorDynInst();
85        assert(bubbleInst->isBubble());
86        /* Make bubbleInst immortal */
87        bubbleInst->incref();
88    }
89}
90
91bool
92MinorDynInst::isLastOpInInst() const
93{
94    assert(staticInst);
95    return !(staticInst->isMicroop() && !staticInst->isLastMicroop());
96}
97
98bool
99MinorDynInst::isNoCostInst() const
100{
101    return isInst() && staticInst->opClass() == No_OpClass;
102}
103
104void
105MinorDynInst::reportData(std::ostream &os) const
106{
107    if (isBubble())
108        os << "-";
109    else if (isFault())
110        os << "F;" << id;
111    else if (translationFault != NoFault)
112        os << "TF;" << id;
113    else
114        os << id;
115}
116
117std::ostream &
118operator <<(std::ostream &os, const MinorDynInst &inst)
119{
120    os << inst.id << " pc: 0x"
121        << std::hex << inst.pc.instAddr() << std::dec << " (";
122
123    if (inst.isFault())
124        os << "fault: \"" << inst.fault->name() << '"';
125    else if (inst.translationFault != NoFault)
126        os << "translation fault: \"" << inst.translationFault->name() << '"';
127    else if (inst.staticInst)
128        os << inst.staticInst->getName();
129    else
130        os << "bubble";
131
132    os << ')';
133
134    return os;
135}
136
137/** Print a register in the form r<n>, f<n>, m<n>(<name>), z for integer,
138 *  float, misc and zero registers given an 'architectural register number' */
139static void
140printRegName(std::ostream &os, const RegId& reg)
141{
142    switch (reg.classValue())
143    {
144      case MiscRegClass:
145        {
146            RegIndex misc_reg = reg.index();
147
148        /* This is an ugly test because not all archs. have miscRegName */
149#if THE_ISA == ARM_ISA
150            os << 'm' << misc_reg << '(' << TheISA::miscRegName[misc_reg] <<
151                ')';
152#else
153            os << 'n' << misc_reg;
154#endif
155        }
156        break;
157      case FloatRegClass:
158        os << 'f' << static_cast<unsigned int>(reg.index());
159        break;
160      case VecRegClass:
161        os << 'v' << static_cast<unsigned int>(reg.index());
162        break;
163      case VecElemClass:
164        os << 'v' << static_cast<unsigned int>(reg.index()) << '[' <<
165              static_cast<unsigned int>(reg.elemIndex()) << ']';
166        break;
167      case IntRegClass:
168        if (reg.isZeroReg()) {
169            os << 'z';
170        } else {
171            os << 'r' << static_cast<unsigned int>(reg.index());
172        }
173        break;
174      case CCRegClass:
175        os << 'c' << static_cast<unsigned int>(reg.index());
176        break;
177      default:
178        panic("Unknown register class: %d", (int)reg.classValue());
179    }
180}
181
182void
183MinorDynInst::minorTraceInst(const Named &named_object) const
184{
185    if (isFault()) {
186        MINORINST(&named_object, "id=F;%s addr=0x%x fault=\"%s\"\n",
187            id, pc.instAddr(), fault->name());
188    } else {
189        unsigned int num_src_regs = staticInst->numSrcRegs();
190        unsigned int num_dest_regs = staticInst->numDestRegs();
191
192        std::ostringstream regs_str;
193
194        /* Format lists of src and dest registers for microops and
195         *  'full' instructions */
196        if (!staticInst->isMacroop()) {
197            regs_str << " srcRegs=";
198
199            unsigned int src_reg = 0;
200            while (src_reg < num_src_regs) {
201                printRegName(regs_str, staticInst->srcRegIdx(src_reg));
202
203                src_reg++;
204                if (src_reg != num_src_regs)
205                    regs_str << ',';
206            }
207
208            regs_str << " destRegs=";
209
210            unsigned int dest_reg = 0;
211            while (dest_reg < num_dest_regs) {
212                printRegName(regs_str, staticInst->destRegIdx(dest_reg));
213
214                dest_reg++;
215                if (dest_reg != num_dest_regs)
216                    regs_str << ',';
217            }
218
219#if THE_ISA == ARM_ISA
220            regs_str << " extMachInst=" << std::hex << std::setw(16)
221                << std::setfill('0') << staticInst->machInst << std::dec;
222#endif
223        }
224
225        std::ostringstream flags;
226        staticInst->printFlags(flags, " ");
227
228        MINORINST(&named_object, "id=%s addr=0x%x inst=\"%s\" class=%s"
229            " flags=\"%s\"%s%s\n",
230            id, pc.instAddr(),
231            (staticInst->opClass() == No_OpClass ?
232                "(invalid)" : staticInst->disassemble(0,NULL)),
233            Enums::OpClassStrings[staticInst->opClass()],
234            flags.str(),
235            regs_str.str(),
236            (predictedTaken ? " predictedTaken" : ""));
237    }
238}
239
240MinorDynInst::~MinorDynInst()
241{
242    if (traceData)
243        delete traceData;
244}
245
246}
247