/gem5/src/arch/riscv/ |
H A D | tlb.hh | 60 PageTable lookupTable; // Quick lookup into page table 67 RiscvISA::PTE *lookup(Addr vpn, uint8_t asn) const;
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/gem5/src/arch/mips/ |
H A D | remote_gdb.cc | 168 return context()->getProcessPtr()->pTable->lookup(va) != nullptr;
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H A D | tlb.cc | 79 TLB::lookup(Addr vpn, uint8_t asn) const function in class:TLB 103 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 179 // Update fast lookup table
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/gem5/src/arch/power/ |
H A D | remote_gdb.cc | 171 return context()->getProcessPtr()->pTable->lookup(va) != nullptr;
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H A D | tlb.hh | 103 PageTable lookupTable; // Quick lookup into page table 117 PowerISA::PTE *lookup(Addr vpn, uint8_t asn) const;
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/gem5/src/arch/x86/ |
H A D | tlb.hh | 74 TlbEntry *lookup(Addr va, bool update_lru = true);
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/gem5/src/cpu/pred/ |
H A D | simple_indirect.hh | 47 bool lookup(Addr br_addr, TheISA::PCState& br_target, ThreadID tid);
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H A D | tage.cc | 105 TAGE::lookup(ThreadID tid, Addr branch_pc, void* &bp_history) function in class:TAGE
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H A D | bpred_unit.cc | 198 pred_taken = lookup(tid, pc.instAddr(), bp_history); 217 // Now lookup in the BTB or RAS. 259 target = BTB.lookup(pc.instAddr(), tid); 287 if (iPred->lookup(pc.instAddr(), target, tid)) { 327 // Note that this happens after indirect lookup, so it does not use
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H A D | bi_mode.cc | 94 * Here we lookup the actual branch prediction. We use the PC to 103 BiModeBP::lookup(ThreadID tid, Addr branchAddr, void * &bpHistory) function in class:BiModeBP
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/gem5/src/mem/ |
H A D | page_table.hh | 135 const Entry *lookup(Addr vaddr);
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/gem5/src/arch/alpha/ |
H A D | faults.cc | 199 const EmulationPageTable::Entry *pte = p->pTable->lookup(pc); 218 const EmulationPageTable::Entry *pte = p->pTable->lookup(vaddr); 220 pte = p->pTable->lookup(vaddr);
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H A D | tlb.hh | 75 PageTable lookupTable; // Quick lookup into page table 81 TlbEntry *lookup(Addr vpn, uint8_t asn);
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H A D | tlb.cc | 164 TLB::lookup(Addr vpn, uint8_t asn) function in class:AlphaISA::TLB 200 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 418 TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), 520 TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), asn);
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/gem5/src/systemc/tests/systemc/examples/trie/ |
H A D | trie.cpp | 21 sc_uint<10> lookup(sc_uint<32>); 76 // do the ip lookup to next hop 77 hop = lookup(data_in); 109 lc::lookup(sc_uint<32> ip) function in class:lc
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/gem5/src/cpu/o3/ |
H A D | cpu.cc | 1319 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 1330 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 1341 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 1351 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 1361 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 1371 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 1381 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 1391 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 1402 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 1413 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( [all...] |
H A D | rename_map.cc | 210 PhysRegIdPtr s_prid = vecElemMap.lookup(s_rid);
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H A D | cpu.hh | 437 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 448 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
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/gem5/src/gpu-compute/ |
H A D | gpu_tlb.cc | 213 GpuTLB::lookup(Addr va, bool update_lru) function in class:X86ISA::GpuTLB 645 * TLB_lookup will only perform a TLB lookup returning true on a TLB hit 675 TlbEntry *entry = lookup(vaddr, true); 783 TlbEntry *entry = lookup(vaddr); 800 p->pTable->lookup(vaddr); 808 pte = p->pTable->lookup(vaddr); 1028 * Do the TLB lookup for this coalesced request and schedule 1068 TlbEntry *entry = lookup(tmp_req->getVaddr(), false); 1088 * We now know the TLB lookup outcome (if it's a hit or a miss), as well 1241 * TLB lookup [all...] |
/gem5/src/dev/arm/ |
H A D | smmu_v3_caches.cc | 179 SMMUTLB::lookup(uint32_t sid, uint32_t ssid, function in class:SMMUTLB 248 lookup(incoming.sid, incoming.ssid, incoming.va, false); 459 ARMArchTLB::lookup(Addr va, uint16_t asid, uint16_t vmid, bool updStats) function in class:ARMArchTLB 500 lookup(incoming.va, incoming.asid, incoming.vmid, false); 658 IPACache::lookup(Addr ipa, uint16_t vmid, bool updStats) function in class:IPACache 698 const Entry *existing = lookup(incoming.ipa, incoming.vmid, false); 838 ConfigCache::lookup(uint32_t sid, uint32_t ssid, bool updStats) function in class:ConfigCache 877 const Entry *existing = lookup(incoming.sid, incoming.ssid, false); 1014 WalkCache::lookup(Addr va, Addr vaMask, function in class:WalkCache 1067 const Entry *existing = lookup(incomin [all...] |
/gem5/src/arch/sparc/ |
H A D | remote_gdb.cc | 170 return context()->getProcessPtr()->pTable->lookup(va) != nullptr;
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H A D | tlb.hh | 108 /** lookup an entry in the TLB based on the partition id, and real bit if 119 TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0,
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/gem5/src/python/m5/util/ |
H A D | code_formatter.py | 39 class lookup(object): class in inherits:object 219 l = lookup(self, frame, *args, **kwargs)
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/gem5/ext/systemc/src/sysc/utils/ |
H A D | sc_hash.cpp | 481 sc_phash_base::lookup( const void* k, void** c_ptr ) const function in class:sc_core::sc_phash_base 499 lookup( key, &contents );
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/gem5/src/base/ |
H A D | trie.hh | 274 lookup(Key key) function in class:Trie 328 * Method to lookup a value from the trie and then delete it.
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