11689SN/A/* 213601Sgiacomo.travaglini@arm.com * Copyright (c) 2011-2012, 2014, 2016, 2017, 2019 ARM Limited 39916Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48707Sandreas.hansson@arm.com * All rights reserved 58707Sandreas.hansson@arm.com * 68707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148707Sandreas.hansson@arm.com * 152325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 167897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 171689SN/A * All rights reserved. 181689SN/A * 191689SN/A * Redistribution and use in source and binary forms, with or without 201689SN/A * modification, are permitted provided that the following conditions are 211689SN/A * met: redistributions of source code must retain the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer; 231689SN/A * redistributions in binary form must reproduce the above copyright 241689SN/A * notice, this list of conditions and the following disclaimer in the 251689SN/A * documentation and/or other materials provided with the distribution; 261689SN/A * neither the name of the copyright holders nor the names of its 271689SN/A * contributors may be used to endorse or promote products derived from 281689SN/A * this software without specific prior written permission. 291689SN/A * 301689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 432756Sksewell@umich.edu * Korey Sewell 447897Shestness@cs.utexas.edu * Rick Strong 451689SN/A */ 461689SN/A 4711793Sbrandon.potter@amd.com#include "cpu/o3/cpu.hh" 4811793Sbrandon.potter@amd.com 4912109SRekai.GonzalezAlberquilla@arm.com#include "arch/generic/traits.hh" 508779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 516658Snate@binkert.org#include "config/the_isa.hh" 5211793Sbrandon.potter@amd.com#include "cpu/activity.hh" 538887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 548887Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 558229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 568229Snate@binkert.org#include "cpu/o3/thread_context.hh" 578779Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 584762Snate@binkert.org#include "cpu/simple_thread.hh" 594762Snate@binkert.org#include "cpu/thread_context.hh" 608232Snate@binkert.org#include "debug/Activity.hh" 619152Satgutier@umich.edu#include "debug/Drain.hh" 628232Snate@binkert.org#include "debug/O3CPU.hh" 638232Snate@binkert.org#include "debug/Quiesce.hh" 644762Snate@binkert.org#include "enums/MemoryMode.hh" 654762Snate@binkert.org#include "sim/core.hh" 668793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 678779Sgblack@eecs.umich.edu#include "sim/process.hh" 684762Snate@binkert.org#include "sim/stat_control.hh" 698460SAli.Saidi@ARM.com#include "sim/system.hh" 704762Snate@binkert.org 715702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 725702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 738232Snate@binkert.org#include "debug/Activity.hh" 7411793Sbrandon.potter@amd.com 755702Ssaidi@eecs.umich.edu#endif 765702Ssaidi@eecs.umich.edu 778737Skoansin.tan@gmail.comstruct BaseCPUParams; 785529Snate@binkert.org 792669Sktlim@umich.eduusing namespace TheISA; 806221Snate@binkert.orgusing namespace std; 811060SN/A 825529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 835712Shsul@eecs.umich.edu : BaseCPU(params) 841060SN/A{ 851060SN/A} 861060SN/A 872292SN/Avoid 882733Sktlim@umich.eduBaseO3CPU::regStats() 892292SN/A{ 902292SN/A BaseCPU::regStats(); 912292SN/A} 922292SN/A 938707Sandreas.hansson@arm.comtemplate <class Impl> 945595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 952733Sktlim@umich.edu : BaseO3CPU(params), 963781Sgblack@eecs.umich.edu itb(params->itb), 973781Sgblack@eecs.umich.edu dtb(params->dtb), 9812127Sspwilson2@wisc.edu tickEvent([this]{ tick(); }, "FullO3CPU tick", 9912127Sspwilson2@wisc.edu false, Event::CPU_Tick_Pri), 10013641Sqtt2@cornell.edu threadExitEvent([this]{ exitThreads(); }, "FullO3CPU exit threads", 10113641Sqtt2@cornell.edu false, Event::CPU_Exit_Pri), 1025737Scws3k@cs.virginia.edu#ifndef NDEBUG 1035737Scws3k@cs.virginia.edu instcount(0), 1045737Scws3k@cs.virginia.edu#endif 1052292SN/A removeInstsThisCycle(false), 1065595Sgblack@eecs.umich.edu fetch(this, params), 1075595Sgblack@eecs.umich.edu decode(this, params), 1085595Sgblack@eecs.umich.edu rename(this, params), 1095595Sgblack@eecs.umich.edu iew(this, params), 1105595Sgblack@eecs.umich.edu commit(this, params), 1111060SN/A 11212109SRekai.GonzalezAlberquilla@arm.com /* It is mandatory that all SMT threads use the same renaming mode as 11312109SRekai.GonzalezAlberquilla@arm.com * they are sharing registers and rename */ 11413601Sgiacomo.travaglini@arm.com vecMode(RenameMode<TheISA::ISA>::init(params->isa[0])), 1159915Ssteve.reinhardt@amd.com regFile(params->numPhysIntRegs, 1169920Syasuko.eckert@amd.com params->numPhysFloatRegs, 11712109SRekai.GonzalezAlberquilla@arm.com params->numPhysVecRegs, 11813610Sgiacomo.gabrielli@arm.com params->numPhysVecPredRegs, 11912109SRekai.GonzalezAlberquilla@arm.com params->numPhysCCRegs, 12012109SRekai.GonzalezAlberquilla@arm.com vecMode), 1211060SN/A 1229919Ssteve.reinhardt@amd.com freeList(name() + ".freelist", ®File), 1231060SN/A 1249954SFaissal.Sleiman@arm.com rob(this, params), 1251060SN/A 1269916Ssteve.reinhardt@amd.com scoreboard(name() + ".scoreboard", 12712105Snathanael.premillieu@arm.com regFile.totalNumPhysRegs()), 1281060SN/A 1299384SAndreas.Sandberg@arm.com isa(numThreads, NULL), 1309384SAndreas.Sandberg@arm.com 1312873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1322873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1332873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1342873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1352873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1365804Snate@binkert.org activityRec(name(), NumStages, 1372873Sktlim@umich.edu params->backComSize + params->forwardComSize, 1382873Sktlim@umich.edu params->activity), 1391060SN/A 1401060SN/A globalSeqNum(1), 1412292SN/A system(params->system), 1429180Sandreas.hansson@arm.com lastRunningCycle(curCycle()) 1431060SN/A{ 1449433SAndreas.Sandberg@ARM.com if (!params->switched_out) { 1453221Sktlim@umich.edu _status = Running; 1463221Sktlim@umich.edu } else { 1479152Satgutier@umich.edu _status = SwitchedOut; 1483221Sktlim@umich.edu } 1491681SN/A 1502794Sktlim@umich.edu if (params->checker) { 1512316SN/A BaseCPU *temp_checker = params->checker; 1528733Sgeoffrey.blake@arm.com checker = dynamic_cast<Checker<Impl> *>(temp_checker); 15314195Sgabeblack@google.com checker->setIcachePort(&this->fetch.getInstPort()); 1542316SN/A checker->setSystem(params->system); 1554598Sbinkertn@umich.edu } else { 1564598Sbinkertn@umich.edu checker = NULL; 1574598Sbinkertn@umich.edu } 1582316SN/A 1598793Sgblack@eecs.umich.edu if (!FullSystem) { 1608793Sgblack@eecs.umich.edu thread.resize(numThreads); 1618793Sgblack@eecs.umich.edu tids.resize(numThreads); 1628793Sgblack@eecs.umich.edu } 1631681SN/A 1642325SN/A // The stages also need their CPU pointer setup. However this 1652325SN/A // must be done at the upper level CPU because they have pointers 1662325SN/A // to the upper level CPU, and not this FullO3CPU. 1671060SN/A 1682292SN/A // Set up Pointers to the activeThreads list for each stage 1692292SN/A fetch.setActiveThreads(&activeThreads); 1702292SN/A decode.setActiveThreads(&activeThreads); 1712292SN/A rename.setActiveThreads(&activeThreads); 1722292SN/A iew.setActiveThreads(&activeThreads); 1732292SN/A commit.setActiveThreads(&activeThreads); 1741060SN/A 1751060SN/A // Give each of the stages the time buffer they will use. 1761060SN/A fetch.setTimeBuffer(&timeBuffer); 1771060SN/A decode.setTimeBuffer(&timeBuffer); 1781060SN/A rename.setTimeBuffer(&timeBuffer); 1791060SN/A iew.setTimeBuffer(&timeBuffer); 1801060SN/A commit.setTimeBuffer(&timeBuffer); 1811060SN/A 1821060SN/A // Also setup each of the stages' queues. 1831060SN/A fetch.setFetchQueue(&fetchQueue); 1841060SN/A decode.setFetchQueue(&fetchQueue); 1852292SN/A commit.setFetchQueue(&fetchQueue); 1861060SN/A decode.setDecodeQueue(&decodeQueue); 1871060SN/A rename.setDecodeQueue(&decodeQueue); 1881060SN/A rename.setRenameQueue(&renameQueue); 1891060SN/A iew.setRenameQueue(&renameQueue); 1901060SN/A iew.setIEWQueue(&iewQueue); 1911060SN/A commit.setIEWQueue(&iewQueue); 1921060SN/A commit.setRenameQueue(&renameQueue); 1931060SN/A 1942292SN/A commit.setIEWStage(&iew); 1952292SN/A rename.setIEWStage(&iew); 1962292SN/A rename.setCommitStage(&commit); 1972292SN/A 1988793Sgblack@eecs.umich.edu ThreadID active_threads; 1998793Sgblack@eecs.umich.edu if (FullSystem) { 2008793Sgblack@eecs.umich.edu active_threads = 1; 2018793Sgblack@eecs.umich.edu } else { 2028793Sgblack@eecs.umich.edu active_threads = params->workload.size(); 2032831Sksewell@umich.edu 2048793Sgblack@eecs.umich.edu if (active_threads > Impl::MaxThreads) { 2058793Sgblack@eecs.umich.edu panic("Workload Size too large. Increase the 'MaxThreads' " 2068793Sgblack@eecs.umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 2078793Sgblack@eecs.umich.edu "or edit your workload size."); 2088793Sgblack@eecs.umich.edu } 2092831Sksewell@umich.edu } 2102292SN/A 2112316SN/A //Make Sure That this a Valid Architeture 2122292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2132292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 21412109SRekai.GonzalezAlberquilla@arm.com assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs); 21513610Sgiacomo.gabrielli@arm.com assert(params->numPhysVecPredRegs >= numThreads * TheISA::NumVecPredRegs); 2169920Syasuko.eckert@amd.com assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs); 2172292SN/A 2182292SN/A rename.setScoreboard(&scoreboard); 2192292SN/A iew.setScoreboard(&scoreboard); 2202292SN/A 2211060SN/A // Setup the rename map for whichever stages need it. 2226221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2239384SAndreas.Sandberg@arm.com isa[tid] = params->isa[tid]; 22413601Sgiacomo.travaglini@arm.com assert(RenameMode<TheISA::ISA>::equalsInit(isa[tid], isa[0])); 2259384SAndreas.Sandberg@arm.com 2269919Ssteve.reinhardt@amd.com // Only Alpha has an FP zero register, so for other ISAs we 2279919Ssteve.reinhardt@amd.com // use an invalid FP register index to avoid special treatment 2289919Ssteve.reinhardt@amd.com // of any valid FP reg. 2299919Ssteve.reinhardt@amd.com RegIndex invalidFPReg = TheISA::NumFloatRegs + 1; 2309919Ssteve.reinhardt@amd.com RegIndex fpZeroReg = 2319919Ssteve.reinhardt@amd.com (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg; 2322292SN/A 2339919Ssteve.reinhardt@amd.com commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 23412109SRekai.GonzalezAlberquilla@arm.com &freeList, 23512109SRekai.GonzalezAlberquilla@arm.com vecMode); 2362292SN/A 2379919Ssteve.reinhardt@amd.com renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 23812109SRekai.GonzalezAlberquilla@arm.com &freeList, vecMode); 2392292SN/A } 2402292SN/A 2419919Ssteve.reinhardt@amd.com // Initialize rename map to assign physical registers to the 2429919Ssteve.reinhardt@amd.com // architectural registers for active threads only. 2439919Ssteve.reinhardt@amd.com for (ThreadID tid = 0; tid < active_threads; tid++) { 2449919Ssteve.reinhardt@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) { 2459919Ssteve.reinhardt@amd.com // Note that we can't use the rename() method because we don't 2469919Ssteve.reinhardt@amd.com // want special treatment for the zero register at this point 24712105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getIntReg(); 24812106SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg); 24912106SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg); 2509919Ssteve.reinhardt@amd.com } 2519919Ssteve.reinhardt@amd.com 2529919Ssteve.reinhardt@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) { 25312105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getFloatReg(); 25412106SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(RegId(FloatRegClass, ridx), phys_reg); 25512106SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry( 25612106SRekai.GonzalezAlberquilla@arm.com RegId(FloatRegClass, ridx), phys_reg); 2579919Ssteve.reinhardt@amd.com } 2589920Syasuko.eckert@amd.com 25912109SRekai.GonzalezAlberquilla@arm.com /* Here we need two 'interfaces' the 'whole register' and the 26012109SRekai.GonzalezAlberquilla@arm.com * 'register element'. At any point only one of them will be 26112109SRekai.GonzalezAlberquilla@arm.com * active. */ 26212109SRekai.GonzalezAlberquilla@arm.com if (vecMode == Enums::Full) { 26312109SRekai.GonzalezAlberquilla@arm.com /* Initialize the full-vector interface */ 26412109SRekai.GonzalezAlberquilla@arm.com for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) { 26512109SRekai.GonzalezAlberquilla@arm.com RegId rid = RegId(VecRegClass, ridx); 26612109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = freeList.getVecReg(); 26712109SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(rid, phys_reg); 26812109SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry(rid, phys_reg); 26912109SRekai.GonzalezAlberquilla@arm.com } 27012109SRekai.GonzalezAlberquilla@arm.com } else { 27112109SRekai.GonzalezAlberquilla@arm.com /* Initialize the vector-element interface */ 27212109SRekai.GonzalezAlberquilla@arm.com for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) { 27312109SRekai.GonzalezAlberquilla@arm.com for (ElemIndex ldx = 0; ldx < TheISA::NumVecElemPerVecReg; 27412109SRekai.GonzalezAlberquilla@arm.com ++ldx) { 27512109SRekai.GonzalezAlberquilla@arm.com RegId lrid = RegId(VecElemClass, ridx, ldx); 27612109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_elem = freeList.getVecElem(); 27712109SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(lrid, phys_elem); 27812109SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry(lrid, phys_elem); 27912109SRekai.GonzalezAlberquilla@arm.com } 28012109SRekai.GonzalezAlberquilla@arm.com } 28112109SRekai.GonzalezAlberquilla@arm.com } 28212109SRekai.GonzalezAlberquilla@arm.com 28313610Sgiacomo.gabrielli@arm.com for (RegIndex ridx = 0; ridx < TheISA::NumVecPredRegs; ++ridx) { 28413610Sgiacomo.gabrielli@arm.com PhysRegIdPtr phys_reg = freeList.getVecPredReg(); 28513610Sgiacomo.gabrielli@arm.com renameMap[tid].setEntry(RegId(VecPredRegClass, ridx), phys_reg); 28613610Sgiacomo.gabrielli@arm.com commitRenameMap[tid].setEntry( 28713610Sgiacomo.gabrielli@arm.com RegId(VecPredRegClass, ridx), phys_reg); 28813610Sgiacomo.gabrielli@arm.com } 28913610Sgiacomo.gabrielli@arm.com 2909920Syasuko.eckert@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) { 29112105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getCCReg(); 29212106SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg); 29312106SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg); 2949920Syasuko.eckert@amd.com } 2959919Ssteve.reinhardt@amd.com } 2969919Ssteve.reinhardt@amd.com 2972292SN/A rename.setRenameMap(renameMap); 2982292SN/A commit.setRenameMap(commitRenameMap); 2991060SN/A rename.setFreeList(&freeList); 3002292SN/A 3011060SN/A // Setup the ROB for whichever stages need it. 3021060SN/A commit.setROB(&rob); 3032292SN/A 3049158Sandreas.hansson@arm.com lastActivatedCycle = 0; 3053093Sksewell@umich.edu 3065595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3075595Sgblack@eecs.umich.edu 3085595Sgblack@eecs.umich.edu // Setup any thread state. 3095595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 3105595Sgblack@eecs.umich.edu 3116221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 3128793Sgblack@eecs.umich.edu if (FullSystem) { 3138793Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 3148793Sgblack@eecs.umich.edu assert(this->numThreads == 1); 3158793Sgblack@eecs.umich.edu this->thread[tid] = new Thread(this, 0, NULL); 3168793Sgblack@eecs.umich.edu } else { 3178793Sgblack@eecs.umich.edu if (tid < params->workload.size()) { 3188793Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 3198793Sgblack@eecs.umich.edu tid, this->thread[tid]); 3208793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3218793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3228793Sgblack@eecs.umich.edu tid, params->workload[tid]); 3235595Sgblack@eecs.umich.edu 3248793Sgblack@eecs.umich.edu //usedTids[tid] = true; 3258793Sgblack@eecs.umich.edu //threadMap[tid] = tid; 3268793Sgblack@eecs.umich.edu } else { 3278793Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 3288793Sgblack@eecs.umich.edu //when scheduling threads to CPU 3298793Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 3305595Sgblack@eecs.umich.edu 3318793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3328793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3338793Sgblack@eecs.umich.edu tid, dummy_proc); 3348793Sgblack@eecs.umich.edu //usedTids[tid] = false; 3358793Sgblack@eecs.umich.edu } 3365595Sgblack@eecs.umich.edu } 3375595Sgblack@eecs.umich.edu 3385595Sgblack@eecs.umich.edu ThreadContext *tc; 3395595Sgblack@eecs.umich.edu 3405595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 3415595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 3425595Sgblack@eecs.umich.edu 3435595Sgblack@eecs.umich.edu tc = o3_tc; 3445595Sgblack@eecs.umich.edu 3455595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 3465595Sgblack@eecs.umich.edu // CheckerThreadContext. 3475595Sgblack@eecs.umich.edu if (params->checker) { 3485595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 3495595Sgblack@eecs.umich.edu o3_tc, this->checker); 3505595Sgblack@eecs.umich.edu } 3515595Sgblack@eecs.umich.edu 3525595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 3535595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 3546221Snate@binkert.org o3_tc->thread = this->thread[tid]; 3555595Sgblack@eecs.umich.edu 35611627Smichael.lebeane@amd.com // Setup quiesce event. 35711627Smichael.lebeane@amd.com this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 35811627Smichael.lebeane@amd.com 3595595Sgblack@eecs.umich.edu // Give the thread the TC. 3606221Snate@binkert.org this->thread[tid]->tc = tc; 3615595Sgblack@eecs.umich.edu 3625595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 3635595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 3645595Sgblack@eecs.umich.edu } 3655595Sgblack@eecs.umich.edu 3668876Sandreas.hansson@arm.com // FullO3CPU always requires an interrupt controller. 36711150Smitch.hayenga@arm.com if (!params->switched_out && interrupts.empty()) { 3688876Sandreas.hansson@arm.com fatal("FullO3CPU %s has no interrupt controller.\n" 3698876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 3708876Sandreas.hansson@arm.com } 3718876Sandreas.hansson@arm.com 3726221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 3736221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 3741060SN/A} 3751060SN/A 3761060SN/Atemplate <class Impl> 3771755SN/AFullO3CPU<Impl>::~FullO3CPU() 3781060SN/A{ 3791060SN/A} 3801060SN/A 3811060SN/Atemplate <class Impl> 3821060SN/Avoid 38310023Smatt.horsnell@ARM.comFullO3CPU<Impl>::regProbePoints() 38410023Smatt.horsnell@ARM.com{ 38510464SAndreas.Sandberg@ARM.com BaseCPU::regProbePoints(); 38610464SAndreas.Sandberg@ARM.com 38710023Smatt.horsnell@ARM.com ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete"); 38810023Smatt.horsnell@ARM.com ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete"); 38910464SAndreas.Sandberg@ARM.com 39010023Smatt.horsnell@ARM.com fetch.regProbePoints(); 39111246Sradhika.jagtap@ARM.com rename.regProbePoints(); 39210023Smatt.horsnell@ARM.com iew.regProbePoints(); 39310023Smatt.horsnell@ARM.com commit.regProbePoints(); 39410023Smatt.horsnell@ARM.com} 39510023Smatt.horsnell@ARM.com 39610023Smatt.horsnell@ARM.comtemplate <class Impl> 39710023Smatt.horsnell@ARM.comvoid 3985595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 3991062SN/A{ 4002733Sktlim@umich.edu BaseO3CPU::regStats(); 4012292SN/A 4022733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4032292SN/A timesIdled 4042292SN/A .name(name() + ".timesIdled") 4052292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4062292SN/A " unscheduled itself") 4072292SN/A .prereq(timesIdled); 4082292SN/A 4092292SN/A idleCycles 4102292SN/A .name(name() + ".idleCycles") 4112292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4122292SN/A "to idling") 4132292SN/A .prereq(idleCycles); 4142292SN/A 4158627SAli.Saidi@ARM.com quiesceCycles 4168627SAli.Saidi@ARM.com .name(name() + ".quiesceCycles") 4178627SAli.Saidi@ARM.com .desc("Total number of cycles that CPU has spent quiesced or waiting " 4188627SAli.Saidi@ARM.com "for an interrupt") 4198627SAli.Saidi@ARM.com .prereq(quiesceCycles); 4208627SAli.Saidi@ARM.com 4212292SN/A // Number of Instructions simulated 4222292SN/A // -------------------------------- 4232292SN/A // Should probably be in Base CPU but need templated 4242292SN/A // MaxThreads so put in here instead 4252292SN/A committedInsts 4262292SN/A .init(numThreads) 4272292SN/A .name(name() + ".committedInsts") 42810225Snilay@cs.wisc.edu .desc("Number of Instructions Simulated") 42910225Snilay@cs.wisc.edu .flags(Stats::total); 4302292SN/A 4318834Satgutier@umich.edu committedOps 4328834Satgutier@umich.edu .init(numThreads) 4338834Satgutier@umich.edu .name(name() + ".committedOps") 43410225Snilay@cs.wisc.edu .desc("Number of Ops (including micro ops) Simulated") 43510225Snilay@cs.wisc.edu .flags(Stats::total); 4362292SN/A 4372292SN/A cpi 4382292SN/A .name(name() + ".cpi") 4392292SN/A .desc("CPI: Cycles Per Instruction") 4402292SN/A .precision(6); 4414392Sktlim@umich.edu cpi = numCycles / committedInsts; 4422292SN/A 4432292SN/A totalCpi 4442292SN/A .name(name() + ".cpi_total") 4452292SN/A .desc("CPI: Total CPI of All Threads") 4462292SN/A .precision(6); 44710225Snilay@cs.wisc.edu totalCpi = numCycles / sum(committedInsts); 4482292SN/A 4492292SN/A ipc 4502292SN/A .name(name() + ".ipc") 4512292SN/A .desc("IPC: Instructions Per Cycle") 4522292SN/A .precision(6); 4534392Sktlim@umich.edu ipc = committedInsts / numCycles; 4542292SN/A 4552292SN/A totalIpc 4562292SN/A .name(name() + ".ipc_total") 4572292SN/A .desc("IPC: Total IPC of All Threads") 4582292SN/A .precision(6); 45910225Snilay@cs.wisc.edu totalIpc = sum(committedInsts) / numCycles; 4602292SN/A 4615595Sgblack@eecs.umich.edu this->fetch.regStats(); 4625595Sgblack@eecs.umich.edu this->decode.regStats(); 4635595Sgblack@eecs.umich.edu this->rename.regStats(); 4645595Sgblack@eecs.umich.edu this->iew.regStats(); 4655595Sgblack@eecs.umich.edu this->commit.regStats(); 4667897Shestness@cs.utexas.edu this->rob.regStats(); 4677897Shestness@cs.utexas.edu 4687897Shestness@cs.utexas.edu intRegfileReads 4697897Shestness@cs.utexas.edu .name(name() + ".int_regfile_reads") 4707897Shestness@cs.utexas.edu .desc("number of integer regfile reads") 4717897Shestness@cs.utexas.edu .prereq(intRegfileReads); 4727897Shestness@cs.utexas.edu 4737897Shestness@cs.utexas.edu intRegfileWrites 4747897Shestness@cs.utexas.edu .name(name() + ".int_regfile_writes") 4757897Shestness@cs.utexas.edu .desc("number of integer regfile writes") 4767897Shestness@cs.utexas.edu .prereq(intRegfileWrites); 4777897Shestness@cs.utexas.edu 4787897Shestness@cs.utexas.edu fpRegfileReads 4797897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_reads") 4807897Shestness@cs.utexas.edu .desc("number of floating regfile reads") 4817897Shestness@cs.utexas.edu .prereq(fpRegfileReads); 4827897Shestness@cs.utexas.edu 4837897Shestness@cs.utexas.edu fpRegfileWrites 4847897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_writes") 4857897Shestness@cs.utexas.edu .desc("number of floating regfile writes") 4867897Shestness@cs.utexas.edu .prereq(fpRegfileWrites); 4877897Shestness@cs.utexas.edu 48812109SRekai.GonzalezAlberquilla@arm.com vecRegfileReads 48912109SRekai.GonzalezAlberquilla@arm.com .name(name() + ".vec_regfile_reads") 49012109SRekai.GonzalezAlberquilla@arm.com .desc("number of vector regfile reads") 49112109SRekai.GonzalezAlberquilla@arm.com .prereq(vecRegfileReads); 49212109SRekai.GonzalezAlberquilla@arm.com 49312109SRekai.GonzalezAlberquilla@arm.com vecRegfileWrites 49412109SRekai.GonzalezAlberquilla@arm.com .name(name() + ".vec_regfile_writes") 49512109SRekai.GonzalezAlberquilla@arm.com .desc("number of vector regfile writes") 49612109SRekai.GonzalezAlberquilla@arm.com .prereq(vecRegfileWrites); 49712109SRekai.GonzalezAlberquilla@arm.com 49813610Sgiacomo.gabrielli@arm.com vecPredRegfileReads 49913610Sgiacomo.gabrielli@arm.com .name(name() + ".pred_regfile_reads") 50013610Sgiacomo.gabrielli@arm.com .desc("number of predicate regfile reads") 50113610Sgiacomo.gabrielli@arm.com .prereq(vecPredRegfileReads); 50213610Sgiacomo.gabrielli@arm.com 50313610Sgiacomo.gabrielli@arm.com vecPredRegfileWrites 50413610Sgiacomo.gabrielli@arm.com .name(name() + ".pred_regfile_writes") 50513610Sgiacomo.gabrielli@arm.com .desc("number of predicate regfile writes") 50613610Sgiacomo.gabrielli@arm.com .prereq(vecPredRegfileWrites); 50713610Sgiacomo.gabrielli@arm.com 5089920Syasuko.eckert@amd.com ccRegfileReads 5099920Syasuko.eckert@amd.com .name(name() + ".cc_regfile_reads") 5109920Syasuko.eckert@amd.com .desc("number of cc regfile reads") 5119920Syasuko.eckert@amd.com .prereq(ccRegfileReads); 5129920Syasuko.eckert@amd.com 5139920Syasuko.eckert@amd.com ccRegfileWrites 5149920Syasuko.eckert@amd.com .name(name() + ".cc_regfile_writes") 5159920Syasuko.eckert@amd.com .desc("number of cc regfile writes") 5169920Syasuko.eckert@amd.com .prereq(ccRegfileWrites); 5179920Syasuko.eckert@amd.com 5187897Shestness@cs.utexas.edu miscRegfileReads 5197897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_reads") 5207897Shestness@cs.utexas.edu .desc("number of misc regfile reads") 5217897Shestness@cs.utexas.edu .prereq(miscRegfileReads); 5227897Shestness@cs.utexas.edu 5237897Shestness@cs.utexas.edu miscRegfileWrites 5247897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_writes") 5257897Shestness@cs.utexas.edu .desc("number of misc regfile writes") 5267897Shestness@cs.utexas.edu .prereq(miscRegfileWrites); 5271062SN/A} 5281062SN/A 5291062SN/Atemplate <class Impl> 5301062SN/Avoid 5311755SN/AFullO3CPU<Impl>::tick() 5321060SN/A{ 5332733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5349444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 53510913Sandreas.sandberg@arm.com assert(drainState() != DrainState::Drained); 5361060SN/A 5372292SN/A ++numCycles; 53812284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_ON); 5392292SN/A 5402325SN/A// activity = false; 5412292SN/A 5422292SN/A //Tick each of the stages 5431060SN/A fetch.tick(); 5441060SN/A 5451060SN/A decode.tick(); 5461060SN/A 5471060SN/A rename.tick(); 5481060SN/A 5491060SN/A iew.tick(); 5501060SN/A 5511060SN/A commit.tick(); 5521060SN/A 5532292SN/A // Now advance the time buffers 5541060SN/A timeBuffer.advance(); 5551060SN/A 5561060SN/A fetchQueue.advance(); 5571060SN/A decodeQueue.advance(); 5581060SN/A renameQueue.advance(); 5591060SN/A iewQueue.advance(); 5601060SN/A 5612325SN/A activityRec.advance(); 5622292SN/A 5632292SN/A if (removeInstsThisCycle) { 5642292SN/A cleanUpRemovedInsts(); 5652292SN/A } 5662292SN/A 5672325SN/A if (!tickEvent.scheduled()) { 5689444SAndreas.Sandberg@ARM.com if (_status == SwitchedOut) { 5693226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 5702325SN/A // increment stat 5719179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 5723221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 5733226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 5749179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 5752325SN/A timesIdled++; 5762325SN/A } else { 5779180Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(Cycles(1))); 5783226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 5792325SN/A } 5802292SN/A } 5812292SN/A 5828793Sgblack@eecs.umich.edu if (!FullSystem) 5838793Sgblack@eecs.umich.edu updateThreadPriority(); 5849444SAndreas.Sandberg@ARM.com 5859444SAndreas.Sandberg@ARM.com tryDrain(); 5861060SN/A} 5871060SN/A 5881060SN/Atemplate <class Impl> 5891060SN/Avoid 5901755SN/AFullO3CPU<Impl>::init() 5911060SN/A{ 5925714Shsul@eecs.umich.edu BaseCPU::init(); 5931060SN/A 5948921Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 5959382SAli.Saidi@ARM.com // Set noSquashFromTC so that the CPU doesn't squash when initially 5968921Sandreas.hansson@arm.com // setting up registers. 5979382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = true; 5988921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 5998921Sandreas.hansson@arm.com thread[tid]->initMemProxies(thread[tid]->getTC()); 6008921Sandreas.hansson@arm.com } 6012292SN/A 6029433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 6038793Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 6048793Sgblack@eecs.umich.edu ThreadContext *src_tc = threadContexts[tid]; 6058793Sgblack@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->contextId()); 6068793Sgblack@eecs.umich.edu } 6076034Ssteve.reinhardt@amd.com } 6082292SN/A 6099382SAli.Saidi@ARM.com // Clear noSquashFromTC. 6106221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 6119382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 6122292SN/A 6139427SAndreas.Sandberg@ARM.com commit.setThreads(thread); 6149427SAndreas.Sandberg@ARM.com} 6152292SN/A 6169427SAndreas.Sandberg@ARM.comtemplate <class Impl> 6179427SAndreas.Sandberg@ARM.comvoid 6189427SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::startup() 6199427SAndreas.Sandberg@ARM.com{ 6209992Snilay@cs.wisc.edu BaseCPU::startup(); 6219461Snilay@cs.wisc.edu for (int tid = 0; tid < numThreads; ++tid) 6229461Snilay@cs.wisc.edu isa[tid]->startup(threadContexts[tid]); 6239461Snilay@cs.wisc.edu 6249427SAndreas.Sandberg@ARM.com fetch.startupStage(); 6259444SAndreas.Sandberg@ARM.com decode.startupStage(); 6269427SAndreas.Sandberg@ARM.com iew.startupStage(); 6279427SAndreas.Sandberg@ARM.com rename.startupStage(); 6289427SAndreas.Sandberg@ARM.com commit.startupStage(); 6292292SN/A} 6302292SN/A 6312292SN/Atemplate <class Impl> 6322292SN/Avoid 6336221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 6342875Sksewell@umich.edu{ 6356221Snate@binkert.org list<ThreadID>::iterator isActive = 6365314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6372875Sksewell@umich.edu 63813831SAndrea.Mondelli@ucf.edu DPRINTF(O3CPU, "[tid:%i] Calling activate thread.\n", tid); 6399444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 6403226Sktlim@umich.edu 6412875Sksewell@umich.edu if (isActive == activeThreads.end()) { 64213831SAndrea.Mondelli@ucf.edu DPRINTF(O3CPU, "[tid:%i] Adding to active threads list\n", 6432875Sksewell@umich.edu tid); 6442875Sksewell@umich.edu 6452875Sksewell@umich.edu activeThreads.push_back(tid); 6462875Sksewell@umich.edu } 6472875Sksewell@umich.edu} 6482875Sksewell@umich.edu 6492875Sksewell@umich.edutemplate <class Impl> 6502875Sksewell@umich.eduvoid 6516221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 6522875Sksewell@umich.edu{ 6532875Sksewell@umich.edu //Remove From Active List, if Active 6546221Snate@binkert.org list<ThreadID>::iterator thread_it = 6555314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6562875Sksewell@umich.edu 65713831SAndrea.Mondelli@ucf.edu DPRINTF(O3CPU, "[tid:%i] Calling deactivate thread.\n", tid); 6589444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 6593226Sktlim@umich.edu 6602875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 66113831SAndrea.Mondelli@ucf.edu DPRINTF(O3CPU,"[tid:%i] Removing from active threads list\n", 6622875Sksewell@umich.edu tid); 6632875Sksewell@umich.edu activeThreads.erase(thread_it); 6642875Sksewell@umich.edu } 66510331Smitch.hayenga@arm.com 66610331Smitch.hayenga@arm.com fetch.deactivateThread(tid); 66710331Smitch.hayenga@arm.com commit.deactivateThread(tid); 6682875Sksewell@umich.edu} 6692875Sksewell@umich.edu 6702875Sksewell@umich.edutemplate <class Impl> 6716221Snate@binkert.orgCounter 6728834Satgutier@umich.eduFullO3CPU<Impl>::totalInsts() const 6736221Snate@binkert.org{ 6746221Snate@binkert.org Counter total(0); 6756221Snate@binkert.org 6766221Snate@binkert.org ThreadID size = thread.size(); 6776221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 6786221Snate@binkert.org total += thread[i]->numInst; 6796221Snate@binkert.org 6806221Snate@binkert.org return total; 6816221Snate@binkert.org} 6826221Snate@binkert.org 6836221Snate@binkert.orgtemplate <class Impl> 6848834Satgutier@umich.eduCounter 6858834Satgutier@umich.eduFullO3CPU<Impl>::totalOps() const 6868834Satgutier@umich.edu{ 6878834Satgutier@umich.edu Counter total(0); 6888834Satgutier@umich.edu 6898834Satgutier@umich.edu ThreadID size = thread.size(); 6908834Satgutier@umich.edu for (ThreadID i = 0; i < size; i++) 6918834Satgutier@umich.edu total += thread[i]->numOp; 6928834Satgutier@umich.edu 6938834Satgutier@umich.edu return total; 6948834Satgutier@umich.edu} 6958834Satgutier@umich.edu 6968834Satgutier@umich.edutemplate <class Impl> 6972875Sksewell@umich.eduvoid 69810407Smitch.hayenga@arm.comFullO3CPU<Impl>::activateContext(ThreadID tid) 6992875Sksewell@umich.edu{ 7009444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 7019444SAndreas.Sandberg@ARM.com 7022875Sksewell@umich.edu // Needs to set each stage to running as well. 70310407Smitch.hayenga@arm.com activateThread(tid); 7042875Sksewell@umich.edu 7059444SAndreas.Sandberg@ARM.com // We don't want to wake the CPU if it is drained. In that case, 7069444SAndreas.Sandberg@ARM.com // we just want to flag the thread as active and schedule the tick 7079444SAndreas.Sandberg@ARM.com // event from drainResume() instead. 70810913Sandreas.sandberg@arm.com if (drainState() == DrainState::Drained) 7099444SAndreas.Sandberg@ARM.com return; 7109444SAndreas.Sandberg@ARM.com 7119158Sandreas.hansson@arm.com // If we are time 0 or if the last activation time is in the past, 7129158Sandreas.hansson@arm.com // schedule the next tick and wake up the fetch unit 7139158Sandreas.hansson@arm.com if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) { 71410407Smitch.hayenga@arm.com scheduleTickEvent(Cycles(0)); 7152875Sksewell@umich.edu 7162875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 7172875Sksewell@umich.edu // deschedule itself. 7182875Sksewell@umich.edu activityRec.activity(); 7192875Sksewell@umich.edu fetch.wakeFromQuiesce(); 7202875Sksewell@umich.edu 7219180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 7229180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 7239179Sandreas.hansson@arm.com if (cycles != 0) 7249179Sandreas.hansson@arm.com --cycles; 7259179Sandreas.hansson@arm.com quiesceCycles += cycles; 7268627SAli.Saidi@ARM.com 7277823Ssteve.reinhardt@amd.com lastActivatedCycle = curTick(); 7282875Sksewell@umich.edu 7292875Sksewell@umich.edu _status = Running; 73011526Sdavid.guillen@arm.com 73111526Sdavid.guillen@arm.com BaseCPU::activateContext(tid); 7322875Sksewell@umich.edu } 7332875Sksewell@umich.edu} 7342875Sksewell@umich.edu 7352875Sksewell@umich.edutemplate <class Impl> 73610407Smitch.hayenga@arm.comvoid 7376221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 7382875Sksewell@umich.edu{ 73913831SAndrea.Mondelli@ucf.edu DPRINTF(O3CPU,"[tid:%i] Suspending Thread Context.\n", tid); 7409444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 74110408Smitch.hayenga@arm.com 74210408Smitch.hayenga@arm.com deactivateThread(tid); 74310407Smitch.hayenga@arm.com 7443221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 74510683Salexandru.dutu@amd.com if (activeThreads.size() == 0) { 7462910Sksewell@umich.edu unscheduleTickEvent(); 74710683Salexandru.dutu@amd.com lastRunningCycle = curCycle(); 74810683Salexandru.dutu@amd.com _status = Idle; 74910683Salexandru.dutu@amd.com } 7508627SAli.Saidi@ARM.com 7518627SAli.Saidi@ARM.com DPRINTF(Quiesce, "Suspending Context\n"); 75211526Sdavid.guillen@arm.com 75311526Sdavid.guillen@arm.com BaseCPU::suspendContext(tid); 7542875Sksewell@umich.edu} 7552875Sksewell@umich.edu 7562875Sksewell@umich.edutemplate <class Impl> 7572875Sksewell@umich.eduvoid 7586221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 7592875Sksewell@umich.edu{ 7602910Sksewell@umich.edu //For now, this is the same as deallocate 76113831SAndrea.Mondelli@ucf.edu DPRINTF(O3CPU,"[tid:%i] Halt Context called. Deallocating\n", tid); 7629444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 76310408Smitch.hayenga@arm.com 76410408Smitch.hayenga@arm.com deactivateThread(tid); 76510408Smitch.hayenga@arm.com removeThread(tid); 76612284Sjose.marinho@arm.com 76712284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_SLEEP); 7682875Sksewell@umich.edu} 7692875Sksewell@umich.edu 7702875Sksewell@umich.edutemplate <class Impl> 7712875Sksewell@umich.eduvoid 7726221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 7732292SN/A{ 7742847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 7752292SN/A // Will change now that the PC and thread state is internal to the CPU 7762683Sktlim@umich.edu // and not in the ThreadContext. 7778793Sgblack@eecs.umich.edu ThreadContext *src_tc; 7788793Sgblack@eecs.umich.edu if (FullSystem) 7798793Sgblack@eecs.umich.edu src_tc = system->threadContexts[tid]; 7808793Sgblack@eecs.umich.edu else 7818793Sgblack@eecs.umich.edu src_tc = tcBase(tid); 7822292SN/A 7832292SN/A //Bind Int Regs to Rename Map 78412104Snathanael.premillieu@arm.com 78512106SRekai.GonzalezAlberquilla@arm.com for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs; 78612106SRekai.GonzalezAlberquilla@arm.com reg_id.index()++) { 78712105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getIntReg(); 78812104Snathanael.premillieu@arm.com renameMap[tid].setEntry(reg_id, phys_reg); 7892292SN/A scoreboard.setReg(phys_reg); 7902292SN/A } 7912292SN/A 7922292SN/A //Bind Float Regs to Rename Map 79312106SRekai.GonzalezAlberquilla@arm.com for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs; 79412106SRekai.GonzalezAlberquilla@arm.com reg_id.index()++) { 79512105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getFloatReg(); 79612104Snathanael.premillieu@arm.com renameMap[tid].setEntry(reg_id, phys_reg); 7972292SN/A scoreboard.setReg(phys_reg); 7982292SN/A } 7992292SN/A 8009920Syasuko.eckert@amd.com //Bind condition-code Regs to Rename Map 80112106SRekai.GonzalezAlberquilla@arm.com for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs; 80212106SRekai.GonzalezAlberquilla@arm.com reg_id.index()++) { 80312105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getCCReg(); 80412104Snathanael.premillieu@arm.com renameMap[tid].setEntry(reg_id, phys_reg); 8059920Syasuko.eckert@amd.com scoreboard.setReg(phys_reg); 8069920Syasuko.eckert@amd.com } 8079920Syasuko.eckert@amd.com 8082292SN/A //Copy Thread Data Into RegFile 8092847Sksewell@umich.edu //this->copyFromTC(tid); 8102292SN/A 8112847Sksewell@umich.edu //Set PC/NPC/NNPC 8127720Sgblack@eecs.umich.edu pcState(src_tc->pcState(), tid); 8132292SN/A 8142680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 8152292SN/A 81610407Smitch.hayenga@arm.com activateContext(tid); 8172292SN/A 8182292SN/A //Reset ROB/IQ/LSQ Entries 8192292SN/A commit.rob->resetEntries(); 8202292SN/A} 8212292SN/A 8222292SN/Atemplate <class Impl> 8232292SN/Avoid 8246221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 8252292SN/A{ 8262877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 8272847Sksewell@umich.edu 8282847Sksewell@umich.edu // Copy Thread Data From RegFile 8292847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 8305364Sksewell@umich.edu // this->copyToTC(tid); 8315364Sksewell@umich.edu 8325364Sksewell@umich.edu 8335364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 8345364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 8355364Sksewell@umich.edu // in SMT workloads. 8362847Sksewell@umich.edu 83713641Sqtt2@cornell.edu // clear all thread-specific states in each stage of the pipeline 83813641Sqtt2@cornell.edu // since this thread is going to be completely removed from the CPU 83913641Sqtt2@cornell.edu commit.clearStates(tid); 84013641Sqtt2@cornell.edu fetch.clearStates(tid); 84113641Sqtt2@cornell.edu decode.clearStates(tid); 84213641Sqtt2@cornell.edu rename.clearStates(tid); 84313641Sqtt2@cornell.edu iew.clearStates(tid); 8442292SN/A 84513641Sqtt2@cornell.edu // at this step, all instructions in the pipeline should be already 84613641Sqtt2@cornell.edu // either committed successfully or squashed. All thread-specific 84713641Sqtt2@cornell.edu // queues in the pipeline must be empty. 8485362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 8492292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 85013641Sqtt2@cornell.edu assert(commit.rob->isEmpty(tid)); 8512292SN/A 8522847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 8533229Sktlim@umich.edu 8543229Sktlim@umich.edu // Commented out for now. This should be possible to do by 8553229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 8563229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 8573229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 8583229Sktlim@umich.edu/* 8592292SN/A if (activeThreads.size() >= 1) { 8602292SN/A commit.rob->resetEntries(); 8612292SN/A iew.resetEntries(); 8622292SN/A } 8633229Sktlim@umich.edu*/ 8642292SN/A} 8652292SN/A 8664192Sktlim@umich.edutemplate <class Impl> 86713601Sgiacomo.travaglini@arm.comvoid 86813601Sgiacomo.travaglini@arm.comFullO3CPU<Impl>::switchRenameMode(ThreadID tid, UnifiedFreeList* freelist) 86913601Sgiacomo.travaglini@arm.com{ 87013601Sgiacomo.travaglini@arm.com auto pc = this->pcState(tid); 87113601Sgiacomo.travaglini@arm.com 87213601Sgiacomo.travaglini@arm.com // new_mode is the new vector renaming mode 87313601Sgiacomo.travaglini@arm.com auto new_mode = RenameMode<TheISA::ISA>::mode(pc); 87413601Sgiacomo.travaglini@arm.com 87513601Sgiacomo.travaglini@arm.com // We update vecMode only if there has been a change 87613601Sgiacomo.travaglini@arm.com if (new_mode != vecMode) { 87713601Sgiacomo.travaglini@arm.com vecMode = new_mode; 87813601Sgiacomo.travaglini@arm.com 87913601Sgiacomo.travaglini@arm.com renameMap[tid].switchMode(vecMode); 88013601Sgiacomo.travaglini@arm.com commitRenameMap[tid].switchMode(vecMode); 88113601Sgiacomo.travaglini@arm.com renameMap[tid].switchFreeList(freelist); 88213601Sgiacomo.travaglini@arm.com } 88313601Sgiacomo.travaglini@arm.com} 88413601Sgiacomo.travaglini@arm.com 88513601Sgiacomo.travaglini@arm.comtemplate <class Impl> 8865702Ssaidi@eecs.umich.eduFault 8875595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 8885595Sgblack@eecs.umich.edu{ 8895595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 89011150Smitch.hayenga@arm.com return this->interrupts[0]->getInterrupt(this->threadContexts[0]); 8915595Sgblack@eecs.umich.edu} 8925595Sgblack@eecs.umich.edu 8935595Sgblack@eecs.umich.edutemplate <class Impl> 8945595Sgblack@eecs.umich.eduvoid 89510379Sandreas.hansson@arm.comFullO3CPU<Impl>::processInterrupts(const Fault &interrupt) 8965595Sgblack@eecs.umich.edu{ 8975595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 8985595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 8995595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 9005595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 9015595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 9025595Sgblack@eecs.umich.edu 9035595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 90411150Smitch.hayenga@arm.com this->interrupts[0]->updateIntrInfo(this->threadContexts[0]); 9055595Sgblack@eecs.umich.edu 9065595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 90710417Sandreas.hansson@arm.com this->trap(interrupt, 0, nullptr); 9085595Sgblack@eecs.umich.edu} 9095595Sgblack@eecs.umich.edu 9101060SN/Atemplate <class Impl> 9112852Sktlim@umich.eduvoid 91210417Sandreas.hansson@arm.comFullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid, 91310417Sandreas.hansson@arm.com const StaticInstPtr &inst) 9145595Sgblack@eecs.umich.edu{ 9155595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 9167684Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid], inst); 9175595Sgblack@eecs.umich.edu} 9185595Sgblack@eecs.umich.edu 9195595Sgblack@eecs.umich.edutemplate <class Impl> 9205595Sgblack@eecs.umich.eduvoid 92111877Sbrandon.potter@amd.comFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid, Fault *fault) 9225595Sgblack@eecs.umich.edu{ 9235595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 9245595Sgblack@eecs.umich.edu 9255595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 9265595Sgblack@eecs.umich.edu 9275595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 9285595Sgblack@eecs.umich.edu // instruction. 9295595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 9305595Sgblack@eecs.umich.edu 9315595Sgblack@eecs.umich.edu // Execute the actual syscall. 93211877Sbrandon.potter@amd.com this->thread[tid]->syscall(callnum, fault); 9335595Sgblack@eecs.umich.edu 9345595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 9355595Sgblack@eecs.umich.edu // incrementing it. 9365595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 9375595Sgblack@eecs.umich.edu} 9385595Sgblack@eecs.umich.edu 9395595Sgblack@eecs.umich.edutemplate <class Impl> 9405595Sgblack@eecs.umich.eduvoid 94110905Sandreas.sandberg@arm.comFullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const 9422864Sktlim@umich.edu{ 94310905Sandreas.sandberg@arm.com thread[tid]->serialize(cp); 9442864Sktlim@umich.edu} 9452864Sktlim@umich.edu 9462864Sktlim@umich.edutemplate <class Impl> 9472864Sktlim@umich.eduvoid 94810905Sandreas.sandberg@arm.comFullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid) 9492864Sktlim@umich.edu{ 95010905Sandreas.sandberg@arm.com thread[tid]->unserialize(cp); 9512864Sktlim@umich.edu} 9522864Sktlim@umich.edu 9532864Sktlim@umich.edutemplate <class Impl> 95410913Sandreas.sandberg@arm.comDrainState 95510913Sandreas.sandberg@arm.comFullO3CPU<Impl>::drain() 9561060SN/A{ 95712276Sanouk.vanlaer@arm.com // Deschedule any power gating event (if any) 95812276Sanouk.vanlaer@arm.com deschedulePowerGatingEvent(); 95912276Sanouk.vanlaer@arm.com 9609444SAndreas.Sandberg@ARM.com // If the CPU isn't doing anything, then return immediately. 96110913Sandreas.sandberg@arm.com if (switchedOut()) 96210913Sandreas.sandberg@arm.com return DrainState::Drained; 9633512Sktlim@umich.edu 9649444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Draining...\n"); 9653512Sktlim@umich.edu 9669444SAndreas.Sandberg@ARM.com // We only need to signal a drain to the commit stage as this 9679444SAndreas.Sandberg@ARM.com // initiates squashing controls the draining. Once the commit 9689444SAndreas.Sandberg@ARM.com // stage commits an instruction where it is safe to stop, it'll 9699444SAndreas.Sandberg@ARM.com // squash the rest of the instructions in the pipeline and force 9709444SAndreas.Sandberg@ARM.com // the fetch stage to stall. The pipeline will be drained once all 9719444SAndreas.Sandberg@ARM.com // in-flight instructions have retired. 9722843Sktlim@umich.edu commit.drain(); 9732325SN/A 9742325SN/A // Wake the CPU and record activity so everything can drain out if 9752863Sktlim@umich.edu // the CPU was not able to immediately drain. 97614085Sgiacomo.travaglini@arm.com if (!isCpuDrained()) { 97712143Sanouk.vanlaer@arm.com // If a thread is suspended, wake it up so it can be drained 97812143Sanouk.vanlaer@arm.com for (auto t : threadContexts) { 97912143Sanouk.vanlaer@arm.com if (t->status() == ThreadContext::Suspended){ 98012143Sanouk.vanlaer@arm.com DPRINTF(Drain, "Currently suspended so activate %i \n", 98112143Sanouk.vanlaer@arm.com t->threadId()); 98212143Sanouk.vanlaer@arm.com t->activate(); 98312143Sanouk.vanlaer@arm.com // As the thread is now active, change the power state as well 98412143Sanouk.vanlaer@arm.com activateContext(t->threadId()); 98512143Sanouk.vanlaer@arm.com } 98612143Sanouk.vanlaer@arm.com } 98712143Sanouk.vanlaer@arm.com 9882863Sktlim@umich.edu wakeCPU(); 9892863Sktlim@umich.edu activityRec.activity(); 9902852Sktlim@umich.edu 9919152Satgutier@umich.edu DPRINTF(Drain, "CPU not drained\n"); 9929152Satgutier@umich.edu 99310913Sandreas.sandberg@arm.com return DrainState::Draining; 9942863Sktlim@umich.edu } else { 9959444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU is already drained\n"); 9969444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 9979444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 9989444SAndreas.Sandberg@ARM.com 9999444SAndreas.Sandberg@ARM.com // Flush out any old data from the time buffers. In 10009444SAndreas.Sandberg@ARM.com // particular, there might be some data in flight from the 10019444SAndreas.Sandberg@ARM.com // fetch stage that isn't visible in any of the CPU buffers we 100214085Sgiacomo.travaglini@arm.com // test in isCpuDrained(). 10039444SAndreas.Sandberg@ARM.com for (int i = 0; i < timeBuffer.getSize(); ++i) { 10049444SAndreas.Sandberg@ARM.com timeBuffer.advance(); 10059444SAndreas.Sandberg@ARM.com fetchQueue.advance(); 10069444SAndreas.Sandberg@ARM.com decodeQueue.advance(); 10079444SAndreas.Sandberg@ARM.com renameQueue.advance(); 10089444SAndreas.Sandberg@ARM.com iewQueue.advance(); 10099444SAndreas.Sandberg@ARM.com } 10109444SAndreas.Sandberg@ARM.com 10119444SAndreas.Sandberg@ARM.com drainSanityCheck(); 101210913Sandreas.sandberg@arm.com return DrainState::Drained; 10132863Sktlim@umich.edu } 10142316SN/A} 10152310SN/A 10162316SN/Atemplate <class Impl> 10179444SAndreas.Sandberg@ARM.combool 10189444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::tryDrain() 10199444SAndreas.Sandberg@ARM.com{ 102014085Sgiacomo.travaglini@arm.com if (drainState() != DrainState::Draining || !isCpuDrained()) 10219444SAndreas.Sandberg@ARM.com return false; 10229444SAndreas.Sandberg@ARM.com 10239444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 10249444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 10259444SAndreas.Sandberg@ARM.com 10269444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 102710913Sandreas.sandberg@arm.com signalDrainDone(); 10289444SAndreas.Sandberg@ARM.com 10299444SAndreas.Sandberg@ARM.com return true; 10309444SAndreas.Sandberg@ARM.com} 10319444SAndreas.Sandberg@ARM.com 10329444SAndreas.Sandberg@ARM.comtemplate <class Impl> 10339444SAndreas.Sandberg@ARM.comvoid 10349444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::drainSanityCheck() const 10359444SAndreas.Sandberg@ARM.com{ 103614085Sgiacomo.travaglini@arm.com assert(isCpuDrained()); 10379444SAndreas.Sandberg@ARM.com fetch.drainSanityCheck(); 10389444SAndreas.Sandberg@ARM.com decode.drainSanityCheck(); 10399444SAndreas.Sandberg@ARM.com rename.drainSanityCheck(); 10409444SAndreas.Sandberg@ARM.com iew.drainSanityCheck(); 10419444SAndreas.Sandberg@ARM.com commit.drainSanityCheck(); 10429444SAndreas.Sandberg@ARM.com} 10439444SAndreas.Sandberg@ARM.com 10449444SAndreas.Sandberg@ARM.comtemplate <class Impl> 10459444SAndreas.Sandberg@ARM.combool 104614085Sgiacomo.travaglini@arm.comFullO3CPU<Impl>::isCpuDrained() const 10479444SAndreas.Sandberg@ARM.com{ 10489444SAndreas.Sandberg@ARM.com bool drained(true); 10499444SAndreas.Sandberg@ARM.com 10509444SAndreas.Sandberg@ARM.com if (!instList.empty() || !removeList.empty()) { 10519444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Main CPU structures not drained.\n"); 10529444SAndreas.Sandberg@ARM.com drained = false; 10539444SAndreas.Sandberg@ARM.com } 10549444SAndreas.Sandberg@ARM.com 10559444SAndreas.Sandberg@ARM.com if (!fetch.isDrained()) { 10569444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Fetch not drained.\n"); 10579444SAndreas.Sandberg@ARM.com drained = false; 10589444SAndreas.Sandberg@ARM.com } 10599444SAndreas.Sandberg@ARM.com 10609444SAndreas.Sandberg@ARM.com if (!decode.isDrained()) { 10619444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Decode not drained.\n"); 10629444SAndreas.Sandberg@ARM.com drained = false; 10639444SAndreas.Sandberg@ARM.com } 10649444SAndreas.Sandberg@ARM.com 10659444SAndreas.Sandberg@ARM.com if (!rename.isDrained()) { 10669444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Rename not drained.\n"); 10679444SAndreas.Sandberg@ARM.com drained = false; 10689444SAndreas.Sandberg@ARM.com } 10699444SAndreas.Sandberg@ARM.com 10709444SAndreas.Sandberg@ARM.com if (!iew.isDrained()) { 10719444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "IEW not drained.\n"); 10729444SAndreas.Sandberg@ARM.com drained = false; 10739444SAndreas.Sandberg@ARM.com } 10749444SAndreas.Sandberg@ARM.com 10759444SAndreas.Sandberg@ARM.com if (!commit.isDrained()) { 10769444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Commit not drained.\n"); 10779444SAndreas.Sandberg@ARM.com drained = false; 10789444SAndreas.Sandberg@ARM.com } 10799444SAndreas.Sandberg@ARM.com 10809444SAndreas.Sandberg@ARM.com return drained; 10819444SAndreas.Sandberg@ARM.com} 10829444SAndreas.Sandberg@ARM.com 10839444SAndreas.Sandberg@ARM.comtemplate <class Impl> 10849444SAndreas.Sandberg@ARM.comvoid 10859444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::commitDrained(ThreadID tid) 10869444SAndreas.Sandberg@ARM.com{ 10879444SAndreas.Sandberg@ARM.com fetch.drainStall(tid); 10889444SAndreas.Sandberg@ARM.com} 10899444SAndreas.Sandberg@ARM.com 10909444SAndreas.Sandberg@ARM.comtemplate <class Impl> 10912316SN/Avoid 10929342SAndreas.Sandberg@arm.comFullO3CPU<Impl>::drainResume() 10932316SN/A{ 10949444SAndreas.Sandberg@ARM.com if (switchedOut()) 10959444SAndreas.Sandberg@ARM.com return; 10962316SN/A 10979444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Resuming...\n"); 10989523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 10993319Shsul@eecs.umich.edu 11009444SAndreas.Sandberg@ARM.com fetch.drainResume(); 11019444SAndreas.Sandberg@ARM.com commit.drainResume(); 11022316SN/A 11039444SAndreas.Sandberg@ARM.com _status = Idle; 11049444SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < thread.size(); i++) { 11059444SAndreas.Sandberg@ARM.com if (thread[i]->status() == ThreadContext::Active) { 11069444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Activating thread: %i\n", i); 11079444SAndreas.Sandberg@ARM.com activateThread(i); 11089444SAndreas.Sandberg@ARM.com _status = Running; 11092863Sktlim@umich.edu } 11102310SN/A } 11119444SAndreas.Sandberg@ARM.com 11129444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 11139444SAndreas.Sandberg@ARM.com if (_status == Running) 11149444SAndreas.Sandberg@ARM.com schedule(tickEvent, nextCycle()); 111512276Sanouk.vanlaer@arm.com 111612276Sanouk.vanlaer@arm.com // Reschedule any power gating event (if any) 111712276Sanouk.vanlaer@arm.com schedulePowerGatingEvent(); 11182843Sktlim@umich.edu} 11192843Sktlim@umich.edu 11202843Sktlim@umich.edutemplate <class Impl> 11212843Sktlim@umich.eduvoid 11222843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 11232843Sktlim@umich.edu{ 11249444SAndreas.Sandberg@ARM.com DPRINTF(O3CPU, "Switching out\n"); 11259429SAndreas.Sandberg@ARM.com BaseCPU::switchOut(); 11269429SAndreas.Sandberg@ARM.com 11279444SAndreas.Sandberg@ARM.com activityRec.reset(); 11282843Sktlim@umich.edu 11292843Sktlim@umich.edu _status = SwitchedOut; 11308887Sgeoffrey.blake@arm.com 11312843Sktlim@umich.edu if (checker) 11322843Sktlim@umich.edu checker->switchOut(); 11331060SN/A} 11341060SN/A 11351060SN/Atemplate <class Impl> 11361060SN/Avoid 11371755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 11381060SN/A{ 11398737Skoansin.tan@gmail.com BaseCPU::takeOverFrom(oldCPU); 11401060SN/A 11412307SN/A fetch.takeOverFrom(); 11422307SN/A decode.takeOverFrom(); 11432307SN/A rename.takeOverFrom(); 11442307SN/A iew.takeOverFrom(); 11452307SN/A commit.takeOverFrom(); 11462307SN/A 11479444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 11481060SN/A 11499152Satgutier@umich.edu FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU); 11509152Satgutier@umich.edu if (oldO3CPU) 11519152Satgutier@umich.edu globalSeqNum = oldO3CPU->globalSeqNum; 11529152Satgutier@umich.edu 11539179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 11549444SAndreas.Sandberg@ARM.com _status = Idle; 11551060SN/A} 11561060SN/A 11571060SN/Atemplate <class Impl> 11589523SAndreas.Sandberg@ARM.comvoid 11599523SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::verifyMemoryMode() const 11609523SAndreas.Sandberg@ARM.com{ 11619524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 11629523SAndreas.Sandberg@ARM.com fatal("The O3 CPU requires the memory system to be in " 11639523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 11649523SAndreas.Sandberg@ARM.com } 11659523SAndreas.Sandberg@ARM.com} 11669523SAndreas.Sandberg@ARM.com 11679523SAndreas.Sandberg@ARM.comtemplate <class Impl> 116813557Sgabeblack@google.comRegVal 116910698Sandreas.hansson@arm.comFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const 11705595Sgblack@eecs.umich.edu{ 11719384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscRegNoEffect(misc_reg); 11725595Sgblack@eecs.umich.edu} 11735595Sgblack@eecs.umich.edu 11745595Sgblack@eecs.umich.edutemplate <class Impl> 117513557Sgabeblack@google.comRegVal 11766221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 11775595Sgblack@eecs.umich.edu{ 11787897Shestness@cs.utexas.edu miscRegfileReads++; 11799384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid)); 11805595Sgblack@eecs.umich.edu} 11815595Sgblack@eecs.umich.edu 11825595Sgblack@eecs.umich.edutemplate <class Impl> 11835595Sgblack@eecs.umich.eduvoid 118413582Sgabeblack@google.comFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) 11855595Sgblack@eecs.umich.edu{ 11869384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscRegNoEffect(misc_reg, val); 11875595Sgblack@eecs.umich.edu} 11885595Sgblack@eecs.umich.edu 11895595Sgblack@eecs.umich.edutemplate <class Impl> 11905595Sgblack@eecs.umich.eduvoid 119113582Sgabeblack@google.comFullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid) 11925595Sgblack@eecs.umich.edu{ 11937897Shestness@cs.utexas.edu miscRegfileWrites++; 11949384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); 11955595Sgblack@eecs.umich.edu} 11965595Sgblack@eecs.umich.edu 11975595Sgblack@eecs.umich.edutemplate <class Impl> 119813557Sgabeblack@google.comRegVal 119912105Snathanael.premillieu@arm.comFullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg) 12001060SN/A{ 12017897Shestness@cs.utexas.edu intRegfileReads++; 120212105Snathanael.premillieu@arm.com return regFile.readIntReg(phys_reg); 12031060SN/A} 12041060SN/A 12051060SN/Atemplate <class Impl> 120613557Sgabeblack@google.comRegVal 120713611Sgabeblack@google.comFullO3CPU<Impl>::readFloatReg(PhysRegIdPtr phys_reg) 12082455SN/A{ 12097897Shestness@cs.utexas.edu fpRegfileReads++; 121013611Sgabeblack@google.com return regFile.readFloatReg(phys_reg); 12111060SN/A} 12121060SN/A 12131060SN/Atemplate <class Impl> 121412109SRekai.GonzalezAlberquilla@arm.comauto 121512109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::readVecReg(PhysRegIdPtr phys_reg) const 121612109SRekai.GonzalezAlberquilla@arm.com -> const VecRegContainer& 121712109SRekai.GonzalezAlberquilla@arm.com{ 121812109SRekai.GonzalezAlberquilla@arm.com vecRegfileReads++; 121912109SRekai.GonzalezAlberquilla@arm.com return regFile.readVecReg(phys_reg); 122012109SRekai.GonzalezAlberquilla@arm.com} 122112109SRekai.GonzalezAlberquilla@arm.com 122212109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 122312109SRekai.GonzalezAlberquilla@arm.comauto 122412109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::getWritableVecReg(PhysRegIdPtr phys_reg) 122512109SRekai.GonzalezAlberquilla@arm.com -> VecRegContainer& 122612109SRekai.GonzalezAlberquilla@arm.com{ 122712109SRekai.GonzalezAlberquilla@arm.com vecRegfileWrites++; 122812109SRekai.GonzalezAlberquilla@arm.com return regFile.getWritableVecReg(phys_reg); 122912109SRekai.GonzalezAlberquilla@arm.com} 123012109SRekai.GonzalezAlberquilla@arm.com 123112109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 123212109SRekai.GonzalezAlberquilla@arm.comauto 123312109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::readVecElem(PhysRegIdPtr phys_reg) const -> const VecElem& 123412109SRekai.GonzalezAlberquilla@arm.com{ 123512109SRekai.GonzalezAlberquilla@arm.com vecRegfileReads++; 123612109SRekai.GonzalezAlberquilla@arm.com return regFile.readVecElem(phys_reg); 123712109SRekai.GonzalezAlberquilla@arm.com} 123812109SRekai.GonzalezAlberquilla@arm.com 123912109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 124013610Sgiacomo.gabrielli@arm.comauto 124113610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::readVecPredReg(PhysRegIdPtr phys_reg) const 124213610Sgiacomo.gabrielli@arm.com -> const VecPredRegContainer& 124313610Sgiacomo.gabrielli@arm.com{ 124413610Sgiacomo.gabrielli@arm.com vecPredRegfileReads++; 124513610Sgiacomo.gabrielli@arm.com return regFile.readVecPredReg(phys_reg); 124613610Sgiacomo.gabrielli@arm.com} 124713610Sgiacomo.gabrielli@arm.com 124813610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 124913610Sgiacomo.gabrielli@arm.comauto 125013610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::getWritableVecPredReg(PhysRegIdPtr phys_reg) 125113610Sgiacomo.gabrielli@arm.com -> VecPredRegContainer& 125213610Sgiacomo.gabrielli@arm.com{ 125313610Sgiacomo.gabrielli@arm.com vecPredRegfileWrites++; 125413610Sgiacomo.gabrielli@arm.com return regFile.getWritableVecPredReg(phys_reg); 125513610Sgiacomo.gabrielli@arm.com} 125613610Sgiacomo.gabrielli@arm.com 125713610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 125813622Sgabeblack@google.comRegVal 125912105Snathanael.premillieu@arm.comFullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg) 12609920Syasuko.eckert@amd.com{ 12619920Syasuko.eckert@amd.com ccRegfileReads++; 126212105Snathanael.premillieu@arm.com return regFile.readCCReg(phys_reg); 12639920Syasuko.eckert@amd.com} 12649920Syasuko.eckert@amd.com 12659920Syasuko.eckert@amd.comtemplate <class Impl> 12661060SN/Avoid 126713557Sgabeblack@google.comFullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, RegVal val) 12681060SN/A{ 12697897Shestness@cs.utexas.edu intRegfileWrites++; 127012105Snathanael.premillieu@arm.com regFile.setIntReg(phys_reg, val); 12711060SN/A} 12721060SN/A 12731060SN/Atemplate <class Impl> 12741060SN/Avoid 127513611Sgabeblack@google.comFullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, RegVal val) 12762455SN/A{ 12777897Shestness@cs.utexas.edu fpRegfileWrites++; 127813611Sgabeblack@google.com regFile.setFloatReg(phys_reg, val); 12791060SN/A} 12801060SN/A 12811060SN/Atemplate <class Impl> 12829920Syasuko.eckert@amd.comvoid 128312109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val) 128412109SRekai.GonzalezAlberquilla@arm.com{ 128512109SRekai.GonzalezAlberquilla@arm.com vecRegfileWrites++; 128612109SRekai.GonzalezAlberquilla@arm.com regFile.setVecReg(phys_reg, val); 128712109SRekai.GonzalezAlberquilla@arm.com} 128812109SRekai.GonzalezAlberquilla@arm.com 128912109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 129012109SRekai.GonzalezAlberquilla@arm.comvoid 129112109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::setVecElem(PhysRegIdPtr phys_reg, const VecElem& val) 129212109SRekai.GonzalezAlberquilla@arm.com{ 129312109SRekai.GonzalezAlberquilla@arm.com vecRegfileWrites++; 129412109SRekai.GonzalezAlberquilla@arm.com regFile.setVecElem(phys_reg, val); 129512109SRekai.GonzalezAlberquilla@arm.com} 129612109SRekai.GonzalezAlberquilla@arm.com 129712109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 129812109SRekai.GonzalezAlberquilla@arm.comvoid 129913610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::setVecPredReg(PhysRegIdPtr phys_reg, 130013610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& val) 130113610Sgiacomo.gabrielli@arm.com{ 130213610Sgiacomo.gabrielli@arm.com vecPredRegfileWrites++; 130313610Sgiacomo.gabrielli@arm.com regFile.setVecPredReg(phys_reg, val); 130413610Sgiacomo.gabrielli@arm.com} 130513610Sgiacomo.gabrielli@arm.com 130613610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 130713610Sgiacomo.gabrielli@arm.comvoid 130813622Sgabeblack@google.comFullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, RegVal val) 13099920Syasuko.eckert@amd.com{ 13109920Syasuko.eckert@amd.com ccRegfileWrites++; 131112105Snathanael.premillieu@arm.com regFile.setCCReg(phys_reg, val); 13129920Syasuko.eckert@amd.com} 13139920Syasuko.eckert@amd.com 13149920Syasuko.eckert@amd.comtemplate <class Impl> 131513557Sgabeblack@google.comRegVal 13166221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 13171060SN/A{ 13187897Shestness@cs.utexas.edu intRegfileReads++; 131912106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 132012106SRekai.GonzalezAlberquilla@arm.com RegId(IntRegClass, reg_idx)); 13212292SN/A 13222292SN/A return regFile.readIntReg(phys_reg); 13232292SN/A} 13242292SN/A 13252292SN/Atemplate <class Impl> 132613557Sgabeblack@google.comRegVal 132713611Sgabeblack@google.comFullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 13282292SN/A{ 13297897Shestness@cs.utexas.edu fpRegfileReads++; 133012106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 133112106SRekai.GonzalezAlberquilla@arm.com RegId(FloatRegClass, reg_idx)); 13322292SN/A 133313611Sgabeblack@google.com return regFile.readFloatReg(phys_reg); 13341060SN/A} 13351060SN/A 13361060SN/Atemplate <class Impl> 133712109SRekai.GonzalezAlberquilla@arm.comauto 133812109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::readArchVecReg(int reg_idx, ThreadID tid) const 133912109SRekai.GonzalezAlberquilla@arm.com -> const VecRegContainer& 134012109SRekai.GonzalezAlberquilla@arm.com{ 134112109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 134212109SRekai.GonzalezAlberquilla@arm.com RegId(VecRegClass, reg_idx)); 134312109SRekai.GonzalezAlberquilla@arm.com return readVecReg(phys_reg); 134412109SRekai.GonzalezAlberquilla@arm.com} 134512109SRekai.GonzalezAlberquilla@arm.com 134612109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 134712109SRekai.GonzalezAlberquilla@arm.comauto 134812109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::getWritableArchVecReg(int reg_idx, ThreadID tid) 134912109SRekai.GonzalezAlberquilla@arm.com -> VecRegContainer& 135012109SRekai.GonzalezAlberquilla@arm.com{ 135112109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 135212109SRekai.GonzalezAlberquilla@arm.com RegId(VecRegClass, reg_idx)); 135312109SRekai.GonzalezAlberquilla@arm.com return getWritableVecReg(phys_reg); 135412109SRekai.GonzalezAlberquilla@arm.com} 135512109SRekai.GonzalezAlberquilla@arm.com 135612109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 135712109SRekai.GonzalezAlberquilla@arm.comauto 135812109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::readArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 135912109SRekai.GonzalezAlberquilla@arm.com ThreadID tid) const -> const VecElem& 136012109SRekai.GonzalezAlberquilla@arm.com{ 136112109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 136213598Sgiacomo.travaglini@arm.com RegId(VecElemClass, reg_idx, ldx)); 136312109SRekai.GonzalezAlberquilla@arm.com return readVecElem(phys_reg); 136412109SRekai.GonzalezAlberquilla@arm.com} 136512109SRekai.GonzalezAlberquilla@arm.com 136612109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 136713610Sgiacomo.gabrielli@arm.comauto 136813610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::readArchVecPredReg(int reg_idx, ThreadID tid) const 136913610Sgiacomo.gabrielli@arm.com -> const VecPredRegContainer& 137013610Sgiacomo.gabrielli@arm.com{ 137113610Sgiacomo.gabrielli@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 137213610Sgiacomo.gabrielli@arm.com RegId(VecPredRegClass, reg_idx)); 137313610Sgiacomo.gabrielli@arm.com return readVecPredReg(phys_reg); 137413610Sgiacomo.gabrielli@arm.com} 137513610Sgiacomo.gabrielli@arm.com 137613610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 137713610Sgiacomo.gabrielli@arm.comauto 137813610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::getWritableArchVecPredReg(int reg_idx, ThreadID tid) 137913610Sgiacomo.gabrielli@arm.com -> VecPredRegContainer& 138013610Sgiacomo.gabrielli@arm.com{ 138113610Sgiacomo.gabrielli@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 138213610Sgiacomo.gabrielli@arm.com RegId(VecPredRegClass, reg_idx)); 138313610Sgiacomo.gabrielli@arm.com return getWritableVecPredReg(phys_reg); 138413610Sgiacomo.gabrielli@arm.com} 138513610Sgiacomo.gabrielli@arm.com 138613610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 138713622Sgabeblack@google.comRegVal 13889920Syasuko.eckert@amd.comFullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid) 13899920Syasuko.eckert@amd.com{ 13909920Syasuko.eckert@amd.com ccRegfileReads++; 139112106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 139212106SRekai.GonzalezAlberquilla@arm.com RegId(CCRegClass, reg_idx)); 13939920Syasuko.eckert@amd.com 13949920Syasuko.eckert@amd.com return regFile.readCCReg(phys_reg); 13959920Syasuko.eckert@amd.com} 13969920Syasuko.eckert@amd.com 13979920Syasuko.eckert@amd.comtemplate <class Impl> 13981060SN/Avoid 139913557Sgabeblack@google.comFullO3CPU<Impl>::setArchIntReg(int reg_idx, RegVal val, ThreadID tid) 14001060SN/A{ 14017897Shestness@cs.utexas.edu intRegfileWrites++; 140212106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 140312106SRekai.GonzalezAlberquilla@arm.com RegId(IntRegClass, reg_idx)); 14042292SN/A 14052292SN/A regFile.setIntReg(phys_reg, val); 14061060SN/A} 14071060SN/A 14081060SN/Atemplate <class Impl> 14091060SN/Avoid 141013611Sgabeblack@google.comFullO3CPU<Impl>::setArchFloatReg(int reg_idx, RegVal val, ThreadID tid) 14111060SN/A{ 14127897Shestness@cs.utexas.edu fpRegfileWrites++; 141312106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 141412106SRekai.GonzalezAlberquilla@arm.com RegId(FloatRegClass, reg_idx)); 14151060SN/A 141613611Sgabeblack@google.com regFile.setFloatReg(phys_reg, val); 14172292SN/A} 14182292SN/A 14192292SN/Atemplate <class Impl> 14209920Syasuko.eckert@amd.comvoid 142112109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::setArchVecReg(int reg_idx, const VecRegContainer& val, 142212109SRekai.GonzalezAlberquilla@arm.com ThreadID tid) 142312109SRekai.GonzalezAlberquilla@arm.com{ 142412109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 142512109SRekai.GonzalezAlberquilla@arm.com RegId(VecRegClass, reg_idx)); 142612109SRekai.GonzalezAlberquilla@arm.com setVecReg(phys_reg, val); 142712109SRekai.GonzalezAlberquilla@arm.com} 142812109SRekai.GonzalezAlberquilla@arm.com 142912109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 143012109SRekai.GonzalezAlberquilla@arm.comvoid 143112109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 143212109SRekai.GonzalezAlberquilla@arm.com const VecElem& val, ThreadID tid) 143312109SRekai.GonzalezAlberquilla@arm.com{ 143412109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 143513546Sgiacomo.travaglini@arm.com RegId(VecElemClass, reg_idx, ldx)); 143612109SRekai.GonzalezAlberquilla@arm.com setVecElem(phys_reg, val); 143712109SRekai.GonzalezAlberquilla@arm.com} 143812109SRekai.GonzalezAlberquilla@arm.com 143912109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 144012109SRekai.GonzalezAlberquilla@arm.comvoid 144113610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::setArchVecPredReg(int reg_idx, const VecPredRegContainer& val, 144213610Sgiacomo.gabrielli@arm.com ThreadID tid) 144313610Sgiacomo.gabrielli@arm.com{ 144413610Sgiacomo.gabrielli@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 144513610Sgiacomo.gabrielli@arm.com RegId(VecPredRegClass, reg_idx)); 144613610Sgiacomo.gabrielli@arm.com setVecPredReg(phys_reg, val); 144713610Sgiacomo.gabrielli@arm.com} 144813610Sgiacomo.gabrielli@arm.com 144913610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 145013610Sgiacomo.gabrielli@arm.comvoid 145113622Sgabeblack@google.comFullO3CPU<Impl>::setArchCCReg(int reg_idx, RegVal val, ThreadID tid) 14529920Syasuko.eckert@amd.com{ 14539920Syasuko.eckert@amd.com ccRegfileWrites++; 145412106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 145512106SRekai.GonzalezAlberquilla@arm.com RegId(CCRegClass, reg_idx)); 14569920Syasuko.eckert@amd.com 14579920Syasuko.eckert@amd.com regFile.setCCReg(phys_reg, val); 14589920Syasuko.eckert@amd.com} 14599920Syasuko.eckert@amd.com 14609920Syasuko.eckert@amd.comtemplate <class Impl> 14617720Sgblack@eecs.umich.eduTheISA::PCState 14627720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(ThreadID tid) 14632292SN/A{ 14647720Sgblack@eecs.umich.edu return commit.pcState(tid); 14651060SN/A} 14661060SN/A 14671060SN/Atemplate <class Impl> 14681060SN/Avoid 14697720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 14701060SN/A{ 14717720Sgblack@eecs.umich.edu commit.pcState(val, tid); 14722292SN/A} 14731060SN/A 14742292SN/Atemplate <class Impl> 14757720Sgblack@eecs.umich.eduAddr 14767720Sgblack@eecs.umich.eduFullO3CPU<Impl>::instAddr(ThreadID tid) 14774636Sgblack@eecs.umich.edu{ 14787720Sgblack@eecs.umich.edu return commit.instAddr(tid); 14794636Sgblack@eecs.umich.edu} 14804636Sgblack@eecs.umich.edu 14814636Sgblack@eecs.umich.edutemplate <class Impl> 14827720Sgblack@eecs.umich.eduAddr 14837720Sgblack@eecs.umich.eduFullO3CPU<Impl>::nextInstAddr(ThreadID tid) 14844636Sgblack@eecs.umich.edu{ 14857720Sgblack@eecs.umich.edu return commit.nextInstAddr(tid); 14864636Sgblack@eecs.umich.edu} 14874636Sgblack@eecs.umich.edu 14884636Sgblack@eecs.umich.edutemplate <class Impl> 14897720Sgblack@eecs.umich.eduMicroPC 14907720Sgblack@eecs.umich.eduFullO3CPU<Impl>::microPC(ThreadID tid) 14912292SN/A{ 14927720Sgblack@eecs.umich.edu return commit.microPC(tid); 14934636Sgblack@eecs.umich.edu} 14944636Sgblack@eecs.umich.edu 14954636Sgblack@eecs.umich.edutemplate <class Impl> 14965595Sgblack@eecs.umich.eduvoid 14976221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 14985595Sgblack@eecs.umich.edu{ 14999382SAli.Saidi@ARM.com this->thread[tid]->noSquashFromTC = true; 15005595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 15015595Sgblack@eecs.umich.edu} 15025595Sgblack@eecs.umich.edu 15035595Sgblack@eecs.umich.edutemplate <class Impl> 15042292SN/Atypename FullO3CPU<Impl>::ListIt 150513429Srekai.gonzalezalberquilla@arm.comFullO3CPU<Impl>::addInst(const DynInstPtr &inst) 15062292SN/A{ 15072292SN/A instList.push_back(inst); 15081060SN/A 15092292SN/A return --(instList.end()); 15102292SN/A} 15111060SN/A 15122292SN/Atemplate <class Impl> 15132292SN/Avoid 151413429Srekai.gonzalezalberquilla@arm.comFullO3CPU<Impl>::instDone(ThreadID tid, const DynInstPtr &inst) 15152292SN/A{ 15162292SN/A // Keep an instruction count. 15178834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) { 15188834Satgutier@umich.edu thread[tid]->numInst++; 15198834Satgutier@umich.edu thread[tid]->numInsts++; 15208834Satgutier@umich.edu committedInsts[tid]++; 152110774Snikos.nikoleris@gmail.com system->totalNumInsts++; 152210774Snikos.nikoleris@gmail.com 152310774Snikos.nikoleris@gmail.com // Check for instruction-count-based events. 152410774Snikos.nikoleris@gmail.com comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 152510774Snikos.nikoleris@gmail.com system->instEventQueue.serviceEvents(system->totalNumInsts); 15268834Satgutier@umich.edu } 15278834Satgutier@umich.edu thread[tid]->numOp++; 15288834Satgutier@umich.edu thread[tid]->numOps++; 15298834Satgutier@umich.edu committedOps[tid]++; 15308834Satgutier@umich.edu 153113818Sjavier.bueno@metempsy.com probeInstCommit(inst->staticInst, inst->instAddr()); 15322292SN/A} 15332292SN/A 15342292SN/Atemplate <class Impl> 15352292SN/Avoid 153613429Srekai.gonzalezalberquilla@arm.comFullO3CPU<Impl>::removeFrontInst(const DynInstPtr &inst) 15371060SN/A{ 15387720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 15392292SN/A "[sn:%lli]\n", 15407720Sgblack@eecs.umich.edu inst->threadNumber, inst->pcState(), inst->seqNum); 15411060SN/A 15422292SN/A removeInstsThisCycle = true; 15431060SN/A 15441060SN/A // Remove the front instruction. 15452292SN/A removeList.push(inst->getInstListIt()); 15461060SN/A} 15471060SN/A 15481060SN/Atemplate <class Impl> 15491060SN/Avoid 15506221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 15511060SN/A{ 15522733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 15532292SN/A " list.\n", tid); 15541060SN/A 15552292SN/A ListIt end_it; 15561060SN/A 15572292SN/A bool rob_empty = false; 15582292SN/A 15592292SN/A if (instList.empty()) { 15602292SN/A return; 156110164Ssleimanf@umich.edu } else if (rob.isEmpty(tid)) { 15622733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 15632292SN/A end_it = instList.begin(); 15642292SN/A rob_empty = true; 15652292SN/A } else { 15662292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 15672733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 15682292SN/A } 15692292SN/A 15702292SN/A removeInstsThisCycle = true; 15712292SN/A 15722292SN/A ListIt inst_it = instList.end(); 15732292SN/A 15742292SN/A inst_it--; 15752292SN/A 15762292SN/A // Walk through the instruction list, removing any instructions 15772292SN/A // that were inserted after the given instruction iterator, end_it. 15782292SN/A while (inst_it != end_it) { 15792292SN/A assert(!instList.empty()); 15802292SN/A 15812292SN/A squashInstIt(inst_it, tid); 15822292SN/A 15832292SN/A inst_it--; 15842292SN/A } 15852292SN/A 15862292SN/A // If the ROB was empty, then we actually need to remove the first 15872292SN/A // instruction as well. 15882292SN/A if (rob_empty) { 15892292SN/A squashInstIt(inst_it, tid); 15902292SN/A } 15911060SN/A} 15921060SN/A 15931060SN/Atemplate <class Impl> 15941060SN/Avoid 15956221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 15961062SN/A{ 15972292SN/A assert(!instList.empty()); 15982292SN/A 15992292SN/A removeInstsThisCycle = true; 16002292SN/A 16012292SN/A ListIt inst_iter = instList.end(); 16022292SN/A 16032292SN/A inst_iter--; 16042292SN/A 16052733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 16062292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 16072292SN/A tid, seq_num, (*inst_iter)->seqNum); 16081062SN/A 16092292SN/A while ((*inst_iter)->seqNum > seq_num) { 16101062SN/A 16112292SN/A bool break_loop = (inst_iter == instList.begin()); 16121062SN/A 16132292SN/A squashInstIt(inst_iter, tid); 16141062SN/A 16152292SN/A inst_iter--; 16161062SN/A 16172292SN/A if (break_loop) 16182292SN/A break; 16192292SN/A } 16202292SN/A} 16212292SN/A 16222292SN/Atemplate <class Impl> 16232292SN/Ainline void 16246221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 16252292SN/A{ 16262292SN/A if ((*instIt)->threadNumber == tid) { 16272733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 16287720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 16292292SN/A (*instIt)->threadNumber, 16302292SN/A (*instIt)->seqNum, 16317720Sgblack@eecs.umich.edu (*instIt)->pcState()); 16321062SN/A 16331062SN/A // Mark it as squashed. 16342292SN/A (*instIt)->setSquashed(); 16352292SN/A 16362325SN/A // @todo: Formulate a consistent method for deleting 16372325SN/A // instructions from the instruction list 16382292SN/A // Remove the instruction from the list. 16392292SN/A removeList.push(instIt); 16402292SN/A } 16412292SN/A} 16422292SN/A 16432292SN/Atemplate <class Impl> 16442292SN/Avoid 16452292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 16462292SN/A{ 16472292SN/A while (!removeList.empty()) { 16482733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 16497720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 16502292SN/A (*removeList.front())->threadNumber, 16512292SN/A (*removeList.front())->seqNum, 16527720Sgblack@eecs.umich.edu (*removeList.front())->pcState()); 16532292SN/A 16542292SN/A instList.erase(removeList.front()); 16552292SN/A 16562292SN/A removeList.pop(); 16571062SN/A } 16581062SN/A 16592292SN/A removeInstsThisCycle = false; 16601062SN/A} 16612325SN/A/* 16621062SN/Atemplate <class Impl> 16631062SN/Avoid 16641755SN/AFullO3CPU<Impl>::removeAllInsts() 16651060SN/A{ 16661060SN/A instList.clear(); 16671060SN/A} 16682325SN/A*/ 16691060SN/Atemplate <class Impl> 16701060SN/Avoid 16711755SN/AFullO3CPU<Impl>::dumpInsts() 16721060SN/A{ 16731060SN/A int num = 0; 16741060SN/A 16752292SN/A ListIt inst_list_it = instList.begin(); 16762292SN/A 16772292SN/A cprintf("Dumping Instruction List\n"); 16782292SN/A 16792292SN/A while (inst_list_it != instList.end()) { 16802292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 16812292SN/A "Squashed:%i\n\n", 16827720Sgblack@eecs.umich.edu num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 16832292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 16842292SN/A (*inst_list_it)->isSquashed()); 16851060SN/A inst_list_it++; 16861060SN/A ++num; 16871060SN/A } 16881060SN/A} 16892325SN/A/* 16901060SN/Atemplate <class Impl> 16911060SN/Avoid 169213429Srekai.gonzalezalberquilla@arm.comFullO3CPU<Impl>::wakeDependents(const DynInstPtr &inst) 16931060SN/A{ 16941060SN/A iew.wakeDependents(inst); 16951060SN/A} 16962325SN/A*/ 16972292SN/Atemplate <class Impl> 16982292SN/Avoid 16992292SN/AFullO3CPU<Impl>::wakeCPU() 17002292SN/A{ 17012325SN/A if (activityRec.active() || tickEvent.scheduled()) { 17022325SN/A DPRINTF(Activity, "CPU already running.\n"); 17032292SN/A return; 17042292SN/A } 17052292SN/A 17062325SN/A DPRINTF(Activity, "Waking up CPU\n"); 17072325SN/A 17089180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 17099180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 171010464SAndreas.Sandberg@ARM.com if (cycles > 1) { 17119179Sandreas.hansson@arm.com --cycles; 171210464SAndreas.Sandberg@ARM.com idleCycles += cycles; 171310464SAndreas.Sandberg@ARM.com numCycles += cycles; 171410464SAndreas.Sandberg@ARM.com } 17152292SN/A 17169648Sdam.sunwoo@arm.com schedule(tickEvent, clockEdge()); 17172292SN/A} 17182292SN/A 17195807Snate@binkert.orgtemplate <class Impl> 17205807Snate@binkert.orgvoid 172111151Smitch.hayenga@arm.comFullO3CPU<Impl>::wakeup(ThreadID tid) 17225807Snate@binkert.org{ 172311151Smitch.hayenga@arm.com if (this->thread[tid]->status() != ThreadContext::Suspended) 17245807Snate@binkert.org return; 17255807Snate@binkert.org 17265807Snate@binkert.org this->wakeCPU(); 17275807Snate@binkert.org 17285807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 172911151Smitch.hayenga@arm.com this->threadContexts[tid]->activate(); 17305807Snate@binkert.org} 17315807Snate@binkert.org 17322292SN/Atemplate <class Impl> 17336221Snate@binkert.orgThreadID 17342292SN/AFullO3CPU<Impl>::getFreeTid() 17352292SN/A{ 17366221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 17376221Snate@binkert.org if (!tids[tid]) { 17386221Snate@binkert.org tids[tid] = true; 17396221Snate@binkert.org return tid; 17402292SN/A } 17412292SN/A } 17422292SN/A 17436221Snate@binkert.org return InvalidThreadID; 17442292SN/A} 17452292SN/A 17462292SN/Atemplate <class Impl> 17472292SN/Avoid 17482292SN/AFullO3CPU<Impl>::updateThreadPriority() 17492292SN/A{ 17506221Snate@binkert.org if (activeThreads.size() > 1) { 17512292SN/A //DEFAULT TO ROUND ROBIN SCHEME 17522292SN/A //e.g. Move highest priority to end of thread list 17536221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 17542292SN/A 17552292SN/A unsigned high_thread = *list_begin; 17562292SN/A 17572292SN/A activeThreads.erase(list_begin); 17582292SN/A 17592292SN/A activeThreads.push_back(high_thread); 17602292SN/A } 17612292SN/A} 17621060SN/A 176313641Sqtt2@cornell.edutemplate <class Impl> 176413641Sqtt2@cornell.eduvoid 176513641Sqtt2@cornell.eduFullO3CPU<Impl>::addThreadToExitingList(ThreadID tid) 176613641Sqtt2@cornell.edu{ 176713641Sqtt2@cornell.edu DPRINTF(O3CPU, "Thread %d is inserted to exitingThreads list\n", tid); 176813641Sqtt2@cornell.edu 176913644Sqtt2@cornell.edu // the thread trying to exit can't be already halted 177013644Sqtt2@cornell.edu assert(tcBase(tid)->status() != ThreadContext::Halted); 177113641Sqtt2@cornell.edu 177213641Sqtt2@cornell.edu // make sure the thread has not been added to the list yet 177313641Sqtt2@cornell.edu assert(exitingThreads.count(tid) == 0); 177413641Sqtt2@cornell.edu 177513641Sqtt2@cornell.edu // add the thread to exitingThreads list to mark that this thread is 177613641Sqtt2@cornell.edu // trying to exit. The boolean value in the pair denotes if a thread is 177713641Sqtt2@cornell.edu // ready to exit. The thread is not ready to exit until the corresponding 177813641Sqtt2@cornell.edu // exit trap event is processed in the future. Until then, it'll be still 177913641Sqtt2@cornell.edu // an active thread that is trying to exit. 178013641Sqtt2@cornell.edu exitingThreads.emplace(std::make_pair(tid, false)); 178113641Sqtt2@cornell.edu} 178213641Sqtt2@cornell.edu 178313641Sqtt2@cornell.edutemplate <class Impl> 178413641Sqtt2@cornell.edubool 178513641Sqtt2@cornell.eduFullO3CPU<Impl>::isThreadExiting(ThreadID tid) const 178613641Sqtt2@cornell.edu{ 178713641Sqtt2@cornell.edu return exitingThreads.count(tid) == 1; 178813641Sqtt2@cornell.edu} 178913641Sqtt2@cornell.edu 179013641Sqtt2@cornell.edutemplate <class Impl> 179113641Sqtt2@cornell.eduvoid 179213641Sqtt2@cornell.eduFullO3CPU<Impl>::scheduleThreadExitEvent(ThreadID tid) 179313641Sqtt2@cornell.edu{ 179413641Sqtt2@cornell.edu assert(exitingThreads.count(tid) == 1); 179513641Sqtt2@cornell.edu 179613641Sqtt2@cornell.edu // exit trap event has been processed. Now, the thread is ready to exit 179713641Sqtt2@cornell.edu // and be removed from the CPU. 179813641Sqtt2@cornell.edu exitingThreads[tid] = true; 179913641Sqtt2@cornell.edu 180013641Sqtt2@cornell.edu // we schedule a threadExitEvent in the next cycle to properly clean 180113641Sqtt2@cornell.edu // up the thread's states in the pipeline. threadExitEvent has lower 180213641Sqtt2@cornell.edu // priority than tickEvent, so the cleanup will happen at the very end 180313641Sqtt2@cornell.edu // of the next cycle after all pipeline stages complete their operations. 180413641Sqtt2@cornell.edu // We want all stages to complete squashing instructions before doing 180513641Sqtt2@cornell.edu // the cleanup. 180613641Sqtt2@cornell.edu if (!threadExitEvent.scheduled()) { 180713641Sqtt2@cornell.edu schedule(threadExitEvent, nextCycle()); 180813641Sqtt2@cornell.edu } 180913641Sqtt2@cornell.edu} 181013641Sqtt2@cornell.edu 181113641Sqtt2@cornell.edutemplate <class Impl> 181213641Sqtt2@cornell.eduvoid 181313641Sqtt2@cornell.eduFullO3CPU<Impl>::exitThreads() 181413641Sqtt2@cornell.edu{ 181513641Sqtt2@cornell.edu // there must be at least one thread trying to exit 181613641Sqtt2@cornell.edu assert(exitingThreads.size() > 0); 181713641Sqtt2@cornell.edu 181813641Sqtt2@cornell.edu // terminate all threads that are ready to exit 181913641Sqtt2@cornell.edu auto it = exitingThreads.begin(); 182013641Sqtt2@cornell.edu while (it != exitingThreads.end()) { 182113641Sqtt2@cornell.edu ThreadID thread_id = it->first; 182213641Sqtt2@cornell.edu bool readyToExit = it->second; 182313641Sqtt2@cornell.edu 182413641Sqtt2@cornell.edu if (readyToExit) { 182513641Sqtt2@cornell.edu DPRINTF(O3CPU, "Exiting thread %d\n", thread_id); 182613641Sqtt2@cornell.edu haltContext(thread_id); 182713641Sqtt2@cornell.edu tcBase(thread_id)->setStatus(ThreadContext::Halted); 182813641Sqtt2@cornell.edu it = exitingThreads.erase(it); 182913641Sqtt2@cornell.edu } else { 183013641Sqtt2@cornell.edu it++; 183113641Sqtt2@cornell.edu } 183213641Sqtt2@cornell.edu } 183313641Sqtt2@cornell.edu} 183413641Sqtt2@cornell.edu 18351755SN/A// Forward declaration of FullO3CPU. 18362818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1837