Searched hist:8707 (Results 1 - 17 of 17) sorted by relevance
| /gem5/src/cpu/simple/ | ||
| H A D | TimingSimpleCPU.py | 8707:489489c67fd9 Tue Jan 17 01:55:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> CPU: Moving towards a more general port across CPU models This patch performs minimal changes to move the instruction and data ports from specialised subclasses to the base CPU (to the largest degree possible). Ultimately it servers to make the CPU(s) have a well-defined interface to the memory sub-system. |
| H A D | AtomicSimpleCPU.py | 8707:489489c67fd9 Tue Jan 17 01:55:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> CPU: Moving towards a more general port across CPU models This patch performs minimal changes to move the instruction and data ports from specialised subclasses to the base CPU (to the largest degree possible). Ultimately it servers to make the CPU(s) have a well-defined interface to the memory sub-system. |
| H A D | timing.hh | 8707:489489c67fd9 Tue Jan 17 01:55:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> CPU: Moving towards a more general port across CPU models This patch performs minimal changes to move the instruction and data ports from specialised subclasses to the base CPU (to the largest degree possible). Ultimately it servers to make the CPU(s) have a well-defined interface to the memory sub-system. |
| H A D | atomic.hh | 8707:489489c67fd9 Tue Jan 17 01:55:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> CPU: Moving towards a more general port across CPU models This patch performs minimal changes to move the instruction and data ports from specialised subclasses to the base CPU (to the largest degree possible). Ultimately it servers to make the CPU(s) have a well-defined interface to the memory sub-system. |
| H A D | timing.cc | 8707:489489c67fd9 Tue Jan 17 01:55:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> CPU: Moving towards a more general port across CPU models This patch performs minimal changes to move the instruction and data ports from specialised subclasses to the base CPU (to the largest degree possible). Ultimately it servers to make the CPU(s) have a well-defined interface to the memory sub-system. |
| H A D | atomic.cc | 8707:489489c67fd9 Tue Jan 17 01:55:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> CPU: Moving towards a more general port across CPU models This patch performs minimal changes to move the instruction and data ports from specialised subclasses to the base CPU (to the largest degree possible). Ultimately it servers to make the CPU(s) have a well-defined interface to the memory sub-system. |
| /gem5/src/cpu/o3/ | ||
| H A D | O3CPU.py | 8707:489489c67fd9 Tue Jan 17 01:55:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> CPU: Moving towards a more general port across CPU models This patch performs minimal changes to move the instruction and data ports from specialised subclasses to the base CPU (to the largest degree possible). Ultimately it servers to make the CPU(s) have a well-defined interface to the memory sub-system. |
| H A D | iew.hh | 8707:489489c67fd9 Tue Jan 17 01:55:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> CPU: Moving towards a more general port across CPU models This patch performs minimal changes to move the instruction and data ports from specialised subclasses to the base CPU (to the largest degree possible). Ultimately it servers to make the CPU(s) have a well-defined interface to the memory sub-system. |
| H A D | lsq.hh | 8707:489489c67fd9 Tue Jan 17 01:55:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> CPU: Moving towards a more general port across CPU models This patch performs minimal changes to move the instruction and data ports from specialised subclasses to the base CPU (to the largest degree possible). Ultimately it servers to make the CPU(s) have a well-defined interface to the memory sub-system. |
| H A D | lsq_impl.hh | 8707:489489c67fd9 Tue Jan 17 01:55:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> CPU: Moving towards a more general port across CPU models This patch performs minimal changes to move the instruction and data ports from specialised subclasses to the base CPU (to the largest degree possible). Ultimately it servers to make the CPU(s) have a well-defined interface to the memory sub-system. |
| H A D | fetch.hh | 8707:489489c67fd9 Tue Jan 17 01:55:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> CPU: Moving towards a more general port across CPU models This patch performs minimal changes to move the instruction and data ports from specialised subclasses to the base CPU (to the largest degree possible). Ultimately it servers to make the CPU(s) have a well-defined interface to the memory sub-system. |
| H A D | cpu.hh | 8707:489489c67fd9 Tue Jan 17 01:55:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> CPU: Moving towards a more general port across CPU models This patch performs minimal changes to move the instruction and data ports from specialised subclasses to the base CPU (to the largest degree possible). Ultimately it servers to make the CPU(s) have a well-defined interface to the memory sub-system. |
| H A D | cpu.cc | 8707:489489c67fd9 Tue Jan 17 01:55:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> CPU: Moving towards a more general port across CPU models This patch performs minimal changes to move the instruction and data ports from specialised subclasses to the base CPU (to the largest degree possible). Ultimately it servers to make the CPU(s) have a well-defined interface to the memory sub-system. |
| H A D | fetch_impl.hh | 8707:489489c67fd9 Tue Jan 17 01:55:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> CPU: Moving towards a more general port across CPU models This patch performs minimal changes to move the instruction and data ports from specialised subclasses to the base CPU (to the largest degree possible). Ultimately it servers to make the CPU(s) have a well-defined interface to the memory sub-system. |
| /gem5/src/cpu/ | ||
| H A D | BaseCPU.py | 8707:489489c67fd9 Tue Jan 17 01:55:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> CPU: Moving towards a more general port across CPU models This patch performs minimal changes to move the instruction and data ports from specialised subclasses to the base CPU (to the largest degree possible). Ultimately it servers to make the CPU(s) have a well-defined interface to the memory sub-system. |
| H A D | base.cc | 8707:489489c67fd9 Tue Jan 17 01:55:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> CPU: Moving towards a more general port across CPU models This patch performs minimal changes to move the instruction and data ports from specialised subclasses to the base CPU (to the largest degree possible). Ultimately it servers to make the CPU(s) have a well-defined interface to the memory sub-system. |
| H A D | base.hh | 8707:489489c67fd9 Tue Jan 17 01:55:00 EST 2012 Andreas Hansson <andreas.hansson@arm.com> CPU: Moving towards a more general port across CPU models This patch performs minimal changes to move the instruction and data ports from specialised subclasses to the base CPU (to the largest degree possible). Ultimately it servers to make the CPU(s) have a well-defined interface to the memory sub-system. |
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