Searched hist:2007 (Results 851 - 875 of 895) sorted by relevance

<<313233343536

/gem5/src/mem/
H A Drequest.hh5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
4610:97834b18a8b4 Thu Jun 21 13:50:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Use FastAlloc for Packet, Request, CoherenceState, and SenderState so we don't spend so much time calling malloc()
4167:ce5d0f62f13b Tue Mar 06 14:13:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Move all of the parameters of the Root SimObject so they are
directly configured by python. Move stuff from root.(cc|hh) to
core.(cc|hh) since it really belogs there now.
In the process, simplify how ticks are used in the python code.
4040:eb894f3fc168 Mon Feb 12 13:06:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> rename store conditional stuff as extra data so it can be used for conditional swaps as well
Add support for a twin 64 bit int load
Add Memory barrier and write barrier flags as appropriate
Make atomic memory ops atomic

src/arch/alpha/isa/mem.isa:
src/arch/alpha/locked_mem.hh:
src/cpu/base_dyn_inst.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/arch/alpha/types.hh:
src/arch/mips/types.hh:
src/arch/sparc/types.hh:
add a largest read data type for statically allocating read buffers in atomic simple cpu
src/arch/isa_parser.py:
Add support for a twin 64 bit int load
src/arch/sparc/isa/decoder.isa:
Make atomic memory ops atomic
Add Memory barrier and write barrier flags as appropriate
src/arch/sparc/isa/formats/mem/basicmem.isa:
add post access code block and define a twinload format for twin loads
src/arch/sparc/isa/formats/mem/blockmem.isa:
remove old microcoded twin load coad
src/arch/sparc/isa/formats/mem/mem.isa:
swap.isa replaces the code in loadstore.isa
src/arch/sparc/isa/formats/mem/util.isa:
add a post access code block
src/arch/sparc/isa/includes.isa:
need bigint.hh for Twin64_t
src/arch/sparc/isa/operands.isa:
add a twin 64 int type
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
add support for twinloads
add support for swap and conditional swap instructions
rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/mem/packet.cc:
src/mem/packet.hh:
Add support for atomic swap memory commands
src/mem/packet_access.hh:
Add endian conversion function for Twin64_t type
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
Add support for atomic swap memory commands
Rename sc code to extradata
/gem5/src/arch/sparc/
H A Dvtophys.cc4172:141705d83494 Wed Mar 07 15:04:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
4070:74449a198a44 Sun Feb 18 19:57:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> implement vtophys and 32bit gdb support

src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
src/arch/sparc/arguments.hh:
move Copy* to vport since it's generic for all the ISAs
src/arch/sparc/isa_traits.hh:
the Solaris kernel sets up a virtual-> real mapping for all memory starting at SegKPMBase
src/arch/sparc/pagetable.hh:
add a class for getting bits out of the TteTag
src/arch/sparc/remote_gdb.cc:
add 32bit support kinda.... If its 32 bit
src/arch/sparc/remote_gdb.hh:
Add 32bit register offsets too.
src/arch/sparc/tlb.cc:
cleanup generation of tsb pointers
src/arch/sparc/tlb.hh:
add function to return tsb pointers for an address
make lookup public so vtophys can use it
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
write vtophys for sparc
src/base/bitfield.hh:
return a mask of bits first->last
src/mem/vport.cc:
src/mem/vport.hh:
move Copy* here since it's ISA generic
H A Dutility.cc4826:259b996a6da6 Wed Aug 01 16:59:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Arguments: Get rid of duplicate code for the Arguments class in each architecture.
Move the argument files to src/sim and add a utility.cc file with a function
getArguments() that returns the given argument in the architecture specific fashion.
getArguments() was getArg() is the architecture specific Argument class and has had
all magic numbers replaced with meaningful constants. Also add a function to the
Argument class for testing if an argument is NULL.
/gem5/util/m5/
H A Dm5.c4098:9b57d3d6af2a Sat Feb 24 22:05:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make m5 readfile work on solaris... we can have a solaris regression soon!

src/arch/sparc/isa/decoder.isa:
add readfile and break to sparc decoder
src/arch/sparc/isa/operands.isa:
fix O0-O5 operands registers
util/m5/Makefile.sparc:
Make sparc makefile compile a 64bit binary
util/m5/m5.c:
readfile was in here twice, once will be sufficient I think
util/m5/m5op_sparc.S:
implement readfile and debugbreak
4090:08bd6439b907 Wed Feb 21 21:06:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> add pseduo instruction support for sparc

util/m5/Makefile.alpha:
Clean up to make it a bit easier to muck with
util/m5/Makefile.alpha:
Make the makefile more reasonable
util/m5/Makefile.alpha:
Remove authors from copyright.
util/m5/Makefile.alpha:
Updated Authors from bk prs info
util/m5/Makefile.alpha:
bk cp Makefile Makefile.alpha
src/arch/sparc/tlb.cc:
Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate
src/arch/alpha/isa/decoder.isa:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
Rename AlphaPseudo -> PseudoInst since it's all generic
src/arch/sparc/isa/bitfields.isa:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/includes.isa:
src/arch/sparc/isa/operands.isa:
Add support for pseudo instructions in sparc
util/m5/Makefile.alpha:
util/m5/Makefile.sparc:
split off alpha make file and sparc make file for m5 app
util/m5/m5.c:
ivle and ivlb aren't used anymore
util/m5/m5op.h:
stdint seems like a more generic better fit here
util/m5/m5op_alpha.S:
move the op ids into their own header file since we can share them between sparc and alpha
/gem5/src/arch/alpha/
H A Dremote_gdb.cc4572:5499df089a6c Thu Jun 14 16:52:00 EDT 2007 Vincentius Robby <acolyte@umich.edu> Modified instruction decode method.
Make code compatible with new decode method.

src/arch/alpha/remote_gdb.cc:
src/cpu/base_dyn_inst_impl.hh:
src/cpu/exetrace.cc:
src/cpu/simple/base.cc:
Make code compatible with new decode method.
src/cpu/static_inst.cc:
src/cpu/static_inst.hh:
Modified instruction decode method.
4172:141705d83494 Wed Mar 07 15:04:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
H A Dsystem.cc4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
H A Dutility.cc4826:259b996a6da6 Wed Aug 01 16:59:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Arguments: Get rid of duplicate code for the Arguments class in each architecture.
Move the argument files to src/sim and add a utility.cc file with a function
getArguments() that returns the given argument in the architecture specific fashion.
getArguments() was getArg() is the architecture specific Argument class and has had
all magic numbers replaced with meaningful constants. Also add a function to the
Argument class for testing if an argument is NULL.
/gem5/src/cpu/o3/
H A Dcomm.hh4636:afc8da9f526e Sat Apr 14 13:13:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect.
4632:be5b8f67b8fb Fri Apr 13 09:59:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Remove most of the special handling for delay slots since they have to be squashed anyway on a mispredict. This is because the NNPC value they saw when executing was incorrect.
H A Drob_impl.hh4329:52057dbec096 Wed Apr 04 15:38:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions.

src/cpu/o3/alpha/cpu_impl.hh:
Pass ISA-specific O3 CPU to FullO3CPU as a constructor parameter instead of using setCPU functions.
4318:eb4241362a80 Mon Apr 02 13:55:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Remove/comment out DPRINTFs that were causing a segfault.

The removed ones were unnecessary. The commented out ones could be useful in the future, should this problem get fixed. See flyspray task #243.

src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob_impl.hh:
Remove/comment out DPRINTFs that were causing a segfault.
H A Dlsq.hh4475:fb185cc1c845 Tue May 22 02:36:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Change getDeviceAddressRanges to use bool for snoop arg.
4329:52057dbec096 Wed Apr 04 15:38:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions.

src/cpu/o3/alpha/cpu_impl.hh:
Pass ISA-specific O3 CPU to FullO3CPU as a constructor parameter instead of using setCPU functions.
4192:7accc6365bb9 Fri Mar 09 10:06:00 EST 2007 Kevin Lim <ktlim@umich.edu> Two fixes:
1. Make sure connectMemPorts() only gets called when the CPU's peer gets changed. This is done by making setPeer() virtual, and overriding it in the CPU's ports. When it gets called on a CPU's port (dcache specifically), it calls the normal setPeer() function, and also connectMemPorts().
2. Consolidate redundant code that handles switching in a CPU.

src/cpu/base.cc:
Move common code of switching over peers to base CPU.
src/cpu/base.hh:
Move common code of switching over peers to BaseCPU.
src/cpu/o3/cpu.cc:
Add in function that updates thread context's ports.
Also use updated function to takeOverFrom() in BaseCPU. This gets rid of some repeated code.
src/cpu/o3/cpu.hh:
Include function to update thread context's memory ports.
src/cpu/o3/lsq.hh:
Add function to dcache port that will update the memory ports upon getting a new peer.
Also include a function that will tell the CPU to update those memory ports.
src/cpu/o3/lsq_impl.hh:
Add function that will update the memory ports upon getting a new peer.
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
Add function that will update thread context's memory ports upon getting a new peer.
Also use the new BaseCPU's take over from function.
src/cpu/simple/atomic.hh:
Add in function (and dcache port) that will allow the dcache to update memory ports when it gets assigned a new peer.
src/cpu/simple/timing.hh:
Add function that will update thread context's memory ports upon getting a new peer.
src/mem/port.hh:
Make setPeer virtual so that other classes can override it.
H A Dfree_list.hh4642:d7b2de2d72f1 Sun Apr 22 13:50:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the floating point zero register special handling only apply for ALPHA.
H A Drob.hh4329:52057dbec096 Wed Apr 04 15:38:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions.

src/cpu/o3/alpha/cpu_impl.hh:
Pass ISA-specific O3 CPU to FullO3CPU as a constructor parameter instead of using setCPU functions.
/gem5/src/arch/alpha/linux/
H A Dprocess.cc5154:7e6431213487 Tue Oct 16 21:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the process objects use the Params structs in their constructors, and use a limit to check if access are on the stack.
5074:14404677893a Thu Sep 13 00:30:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Syscall Emulation: Add stat64 syscall.

Patch submitted by: Jonas Diemer [diemer (a) ida.ing.tu-bs.de]
/gem5/src/arch/x86/linux/
H A Dprocess.cc5154:7e6431213487 Tue Oct 16 21:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the process objects use the Params structs in their constructors, and use a limit to check if access are on the stack.
4166:ecebe3ac19b4 Tue Mar 06 10:42:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Get X86 to load an elf and start a process for it.

src/arch/x86/SConscript:
Add in process source files.
src/arch/x86/isa_traits.hh:
Replace magic constant numbers with the x86 register names.
src/arch/x86/miscregfile.cc:
Make clear the miscreg file succeed. There aren't any misc regs, so clearing them is very easy.
src/arch/x86/process.hh:
An X86 process class.
src/base/loader/elf_object.cc:
Add in code to recognize x86 as an architecture.
src/base/traceflags.py:
Add an x86 traceflag
src/sim/process.cc:
Add in code to create an x86 process.
src/arch/x86/intregs.hh:
A file which declares names for the integer register indices.
src/arch/x86/linux/linux.cc:
src/arch/x86/linux/linux.hh:
A very simple translation of SPARC's linux.cc and linux.hh. It's probably not correct for x86, but it might not be correct for SPARC either.
src/arch/x86/linux/process.cc:
src/arch/x86/linux/process.hh:
An x86 linux process. The syscall table is split out into it's own file.
src/arch/x86/linux/syscalls.cc:
The x86 Linux syscall table and the uname function.
src/arch/x86/process.cc:
The x86 process base class.
tests/test-progs/hello/bin/x86/linux/hello:
An x86 hello world test binary.
/gem5/src/arch/x86/
H A Dpagetable_walker.cc5304:a685ea6cc8b8 Sun Dec 02 04:46:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make the page not present panic more descriptive.
5245:d94bb8af9f76 Mon Nov 12 21:06:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Separate out the page table walker into it's own cc and hh.
H A Dpagetable_walker.hh5245:d94bb8af9f76 Mon Nov 12 21:06:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Separate out the page table walker into it's own cc and hh.
/gem5/src/cpu/
H A Dthread_state.cc4434:2ea7b6e0b78f Wed May 09 15:37:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> fix the translating ports so it can add a page on a fault
4190:5069dfa3d62e Thu Mar 08 18:57:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> stop m5 from leaking like a sieve
don't create a new physPort/virtPort every time activateContext() is called
add the ability to tell a memory object to delete it's reference to a port and a method to have a port call deletePortRefs()
on the port owner as well as delete it's peer
still need to stop calling connectMemoPorts() every time activateContext() is called or we'll overflow the bus id and panic

src/cpu/thread_state.cc:
if we hav ea (phys|virt)Port don't create a new on, have it delete it's peer and then reuse it
src/mem/bus.cc:
src/mem/bus.hh:
add ability to delete a port by usig a hash_map instead of an array to store port ids
add a function to do deleting
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/mem_object.cc:
src/mem/mem_object.hh:
adda function to delete port references from a memory object
src/mem/port.cc:
src/mem/port.hh:
add a removeConn function that tell the owener to delete any references to the port and then deletes its peer
H A Dsimple_thread.cc4997:e7380529bd2d Sun Aug 26 23:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
4400:619191b2f011 Mon Apr 16 11:31:00 EDT 2007 Ron Dreslinski <rdreslin@umich.edu> Fixes for splash, may conflict with Korey's SMT work and doesn't support 03cpu yet.

src/cpu/simple/base.cc:
Cpu's should start as unallocated, not suspended
src/cpu/simple_thread.cc:
Wait for a thread to be assigned to activate the cpu
src/kern/tru64/tru64.hh:
When looking for a open cpu to assign threads, look for an unallocated one, not a suspended one.
4217:4c966fec2324 Tue Mar 13 17:34:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> fix segfault when peer owner attempts to use functional port
H A Dthread_context.cc5217:bb810bb8ca2d Thu Nov 08 10:46:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> CPU: Add function to explictly compare thread contexts after copying.
/gem5/src/sim/
H A Dsyscall_emul.hh5282:2dba627b6646 Thu Nov 29 00:22:00 EST 2007 Rick Strong <rstrong@cs.ucsd.edu> Serialization: Fix serialization of file descriptors. Make sure open
file descriptors are reopened and the file pointer is in the same
place as when the checkpoint occured.

Signed-off by: Ali Saidi
5208:8ec8ba9ee9fd Fri Nov 02 02:11:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> SE: fix stat64 syscall on os x
5074:14404677893a Thu Sep 13 00:30:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Syscall Emulation: Add stat64 syscall.

Patch submitted by: Jonas Diemer [diemer (a) ida.ing.tu-bs.de]
4189:8e5222bea9ba Fri Mar 09 17:14:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Use the TheISA namespace in case we're coming from a file that doesn't do that for us. This should be contained in the scope of the function and not leak elsewhere.
4131:660ebc4994a9 Sun Mar 04 22:26:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Don't use the exact same name as a system header #define
4118:ddd23e5282d7 Fri Mar 02 22:34:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Implement the _llseek syscall. It's Linux only, so we'll actually use the lseek syscall.
4061:45162dc462a7 Wed Feb 14 00:58:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Force the st_blksize field of a stat call to be 8k.
H A Dpseudo_inst.hh4090:08bd6439b907 Wed Feb 21 21:06:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> add pseduo instruction support for sparc

util/m5/Makefile.alpha:
Clean up to make it a bit easier to muck with
util/m5/Makefile.alpha:
Make the makefile more reasonable
util/m5/Makefile.alpha:
Remove authors from copyright.
util/m5/Makefile.alpha:
Updated Authors from bk prs info
util/m5/Makefile.alpha:
bk cp Makefile Makefile.alpha
src/arch/sparc/tlb.cc:
Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate
src/arch/alpha/isa/decoder.isa:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
Rename AlphaPseudo -> PseudoInst since it's all generic
src/arch/sparc/isa/bitfields.isa:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/includes.isa:
src/arch/sparc/isa/operands.isa:
Add support for pseudo instructions in sparc
util/m5/Makefile.alpha:
util/m5/Makefile.sparc:
split off alpha make file and sparc make file for m5 app
util/m5/m5.c:
ivle and ivlb aren't used anymore
util/m5/m5op.h:
stdint seems like a more generic better fit here
util/m5/m5op_alpha.S:
move the op ids into their own header file since we can share them between sparc and alpha
H A Dsim_events.hh4167:ce5d0f62f13b Tue Mar 06 14:13:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Move all of the parameters of the Root SimObject so they are
directly configured by python. Move stuff from root.(cc|hh) to
core.(cc|hh) since it really belogs there now.
In the process, simplify how ticks are used in the python code.
H A Dserialize.hh4841:89a9419e7361 Thu Aug 02 14:43:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Serialization: Provide array serialization methods that work on std::vector
4000:9bf49767a9e4 Tue Jan 30 18:25:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Make SPARC checkpointing work

src/arch/sparc/floatregfile.cc:
Fix serialization for fpreg
src/arch/sparc/intregfile.cc:
fix serialization for intreg
src/arch/sparc/miscregfile.cc:
fix serialization from miscreg
src/arch/sparc/pagetable.cc:
fix serialization for page table
src/arch/sparc/regfile.cc:
need to serialize nnpc
src/arch/sparc/tlb.cc:
write serialization code for tlb
src/cpu/base.cc:
provide a way to find the thread number a context is
serialize the instruction counter
src/cpu/base.hh:
provide a way to find the thread number a context is
and given a thread number find a context pointer
src/cpu/cpuevent.hh:
provide method to get thread context from a cpu event for serialization
src/dev/sparc/t1000.cc:
src/dev/sparc/t1000.hh:
nothing to serialize in t1000
src/sim/serialize.cc:
src/sim/serialize.hh:
Make findObj() work (it hasn't since we did the python conversion stuff)
/gem5/src/arch/sparc/isa/formats/
H A Dpriv.isa5094:10b8551e3e3f Tue Sep 25 23:09:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> SPARC: Clean up of privileged instructions.
/gem5/configs/example/
H A Dse.py5056:11789c986e14 Wed Sep 05 14:57:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Configuration: Fix example script to only create one L2 if --l2cache and -nX are given as parameters.

Patch submitted by: Jonas Diemer [diemer (a) ida.ing.tu-bs.de]
4968:f1c856d8c460 Wed Aug 08 18:43:00 EDT 2007 Vincentius Robby <acolyte@umich.edu> Added fastmem option.
Lets CPU accesses to physical memory bypass Bus.
4847:41126ac89de7 Wed Aug 01 21:19:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fix how the "cmd" parameter is set in se.py and remove hack in x86 process initialization code.
4455:18ff8ee46de8 Tue May 15 18:06:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> add an l2 cache option to se example config

configs/common/Options.py:
configs/example/fs.py:
move l2 cache option to Options.py

Completed in 320 milliseconds

<<313233343536