sparc: Pull flat static instruction classes out of the ISA.

These classes are just used as base classes for other instructions
and don't need to be part of the ISA definition. Pull them into
standard C++ files.

Change-Id: If3e0bd82b1e676f20459bc0293fbda49de66b554
Reviewed-on: https://gem5-review.googlesource.com/5422
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.

The ISA parser used to generate different copies of exec functions
for each exec context class a particular CPU wanted to use. That's
since been changed so that those functions take a pointer to the base
ExecContext, so the code which would generate those extra functions
can be removed, and some functions which used to be templated on an
ExecContext subclass can be untemplated, or minimally less templated.

Now that some functions aren't going to be instantiated multiple times
with different signatures, there are also opportunities to collapse
templates and make many instruction definitions simpler within the
parser. Since those changes will be less mechanical, they're left for
later changes and will probably be done in smaller increments.

Change-Id: I0015307bb02dfb9c60380b56d2a820f12169ebea
Reviewed-on: https://gem5-review.googlesource.com/5381
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Simplify the rename interface and use RegId

With the hierarchical RegId there are a lot of functions that are
redundant now.

The idea behind the simplification is that instead of having the regId,
telling which kind of register read/write/rename/lookup/etc. and then
the function panic_if'ing if the regId is not of the appropriate type,
we provide an interface that decides what kind of register to read
depending on the register type of the given regId.

Change-Id: I7d52e9e21fc01205ae365d86921a4ceb67a57178
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2702

arch, cpu: Architectural Register structural indexing

Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.

Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700

arch: Use shared_ptr for all Faults

This patch takes quite a large step in transitioning from the ad-hoc
RefCountingPtr to the c++11 shared_ptr by adopting its use for all
Faults. There are no changes in behaviour, and the code modifications
are mostly just replacing "new" with "make_shared".

arch: teach ISA parser how to split code across files

This patch encompasses several interrelated and interdependent changes
to the ISA generation step. The end goal is to reduce the size of the
generated compilation units for instruction execution and decoding so
that batch compilation can proceed with all CPUs active without
exhausting physical memory.

The ISA parser (src/arch/isa_parser.py) has been improved so that it can
accept 'split [output_type];' directives at the top level of the grammar
and 'split(output_type)' python calls within 'exec {{ ... }}' blocks.
This has the effect of "splitting" the files into smaller compilation
units. I use air-quotes around "splitting" because the files themselves
are not split, but preprocessing directives are inserted to have the same
effect.

Architecturally, the ISA parser has had some changes in how it works.
In general, it emits code sooner. It doesn't generate per-CPU files,
and instead defers to the C preprocessor to create the duplicate copies
for each CPU type. Likewise there are more files emitted and the C
preprocessor does more substitution that used to be done by the ISA parser.

Finally, the build system (SCons) needs to be able to cope with a
dynamic list of source files coming out of the ISA parser. The changes
to the SCons{cript,truct} files support this. In broad strokes, the
targets requested on the command line are hidden from SCons until all
the build dependencies are determined, otherwise it would try, realize
it can't reach the goal, and terminate in failure. Since build steps
(i.e. running the ISA parser) must be taken to determine the file list,
several new build stages have been inserted at the very start of the
build. First, the build dependencies from the ISA parser will be emitted
to arch/$ISA/generated/inc.d, which is then read by a new SCons builder
to finalize the dependencies. (Once inc.d exists, the ISA parser will not
need to be run to complete this step.) Once the dependencies are known,
the 'Environments' are made by the makeEnv() function. This function used
to be called before the build began but now happens during the build.
It is easy to see that this step is quite slow; this is a known issue
and it's important to realize that it was already slow, but there was
no obvious cause to attribute it to since nothing was displayed to the
terminal. Since new steps that used to be performed serially are now in a
potentially-parallel build phase, the pathname handling in the SCons scripts
has been tightened up to deal with chdir() race conditions. In general,
pathnames are computed earlier and more likely to be stored, passed around,
and processed as absolute paths rather than relative paths. In the end,
some of these issues had to be fixed by inserting serializing dependencies
in the build.

Minor note:
For the null ISA, we just provide a dummy inc.d so SCons is never
compelled to try to generate it. While it seems slightly wrong to have
anything in src/arch/*/generated (i.e. a non-generated 'generated' file),
it's by far the simplest solution.

arch: remove inline specifiers on all inst constrs, all ISAs

With (upcoming) separate compilation, they are useless. Only
link-time optimization could re-inline them, but ideally
feedback-directed optimization would choose to do so only for
profitable (i.e. common) instructions.

SPARC: Make PSTATE and HPSTATE a BitUnion.

This gets rid of cryptic bits of code with lots of bit manipulation, and makes
some comments redundant.

SPARC: Clean up some historical style issues.

SPARC: Clean up of privileged instructions.

Changes to the isa_parser and affected files to fix an indexing problem with split execute instructions and miscregs aliasing with integer registers.

src/arch/isa_parser.py:
Rearranged things so that classes with more than one execute function treat operands properly.
1. Eliminated the CodeBlock class
2. Created a SubOperandList
3. Redefined how InstObjParams is constructed

To define an InstObjParam, you can either pass in a single code literal which will be named "code", or you can pass in a dictionary of code snippets which will be substituted into the Templates. In order to get this to work, there is a new restriction that each template has only one function in it. These changes should only affect memory instructions which have regular and split execute functions.

Also changed the MiscRegs so that they use the instrunctions srcReg and destReg arrays.
src/arch/sparc/isa/formats/basic.isa:
src/arch/sparc/isa/formats/branch.isa:
src/arch/sparc/isa/formats/integerop.isa:
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/isa/formats/nop.isa:
src/arch/sparc/isa/formats/priv.isa:
src/arch/sparc/isa/formats/trap.isa:
Rearranged to work with new InstObjParam scheme.
src/cpu/o3/sparc/dyn_inst.hh:
Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays. Also changed the names of the other accessors so that they have the suffix "Operand" if they use those arrays.
src/cpu/simple/base.hh:
Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays.

Fix up the disassembly a little.

Put in provisions for rd, rdpr, rdhpr, wr, wrpr, and wrhpr to disassemble properly.

Fix up instructions to read and write control registers, and got rid of the control register fields which won't work on a big endian host.

Fixed the priv instruction format.

src/arch/sparc/isa/formats/priv.isa:
Fix the priv format so that it uses isa_parser operands rather than accessing the registers directly in checkCode. Also, the expressions needed to be negated.
src/arch/sparc/isa/operands.isa:
Added an Hpstate operand, and adjusted the numbering.

Fix how additional template parameters are handled. Non string parameters are not processed as code.

src/arch/isa_parser.py:
Changed the way the extra template parameters are specified. MIPS might need to be adjusted.
src/arch/sparc/isa/decoder.isa:
Changed how Frd_N was set up.
src/arch/sparc/isa/formats/blockmem.isa:
Fixed up handling of block memory operations
src/arch/sparc/isa/formats/integerop.isa:
src/arch/sparc/isa/formats/mem.isa:
src/arch/sparc/isa/formats/priv.isa:
Fix up extra template parameters.

Cleaned things up a little.

Added in the IprAccessOp flag for priveleged and hyperpriveleged instructions.

Used the Priv and new HPriv instruction formats, which have been tweaked to let some checks be done by the misc reg file.

Implement PR/HPR/ASR for full system
Rip out storage in miscreg file that will never store anything
Add storage and defines for Priv and Hyperpriv registers
Change defines to match the spec register numbers
Change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR.
Change contextval to an int since both global registers and windowed registers are indexed by int in UA2005.
Use bitfields for things that are rarely used in decoder
Instead of decoding ASR/PR/HPR and having a specfic instruction, use a generic instruction instead

Still todo:
Protect rdpr, rdhpr, wrpr, wrhpr with checks that fault in insufficient privs
Deal with signaling interrupts on timer expiration
Deal with writes to softint/PIL generating interrupts how those are vectored to the CPU

Other misc:
Instruction decoding needs major help!

src/arch/sparc/isa/decoder.isa:
Remove tons of MISCREG_XXXX defines that weren't used and ControlRegs in that were never used. Ones that were used rarely
changed to bitfields.
src/arch/sparc/isa/formats/integerop.isa:
These seems like a whole lot of overkill in printing, but i'll leave it the way it is for now. Allow Ccr to be set
at once
src/arch/sparc/isa/formats/priv.isa:
PrivTick is handled by miscreg now, don't need a seperate class for it
src/arch/sparc/isa/operands.isa:
prune the number of control regs down to a reasonable amount
src/arch/sparc/isa_traits.hh:
Replace 8 defines with 1 and flick some bits
src/arch/sparc/process.cc:
Better to clean the entire registers that specific bits which leads to indetermanistic behavior.
src/arch/sparc/regfile.hh:
Rip out storage that will never be backed by anything
Add storage for Priv and Hyperpriv registers
change defines to match the spec
change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR.
change contextval to an int since both global registers and windowed registers are indexed by int in UA2005.

New directory structure:
- simulator source now in 'src' subdirectory
- imported files from 'ext' repository
- support building in arbitrary places, including
outside of the source tree. See comment at top
of SConstruct file for more details.
Regression tests are temporarily disabled; that
syetem needs more extensive revisions.

SConstruct:
Update for new directory structure.
Modify to support build trees that are not subdirectories
of the source tree. See comment at top of file for
more details.
Regression tests are temporarily disabled.
src/arch/SConscript:
src/arch/isa_parser.py:
src/python/SConscript:
Update for new directory structure.