| /gem5/src/arch/mips/ |
| H A D | interrupts.hh | 65 setCPU(BaseCPU *_cpu) argument
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| /gem5/src/cpu/o3/ |
| H A D | thread_state.hh | 91 O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process) argument
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| H A D | decode_impl.hh | 62 DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params) argument
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| H A D | rob_impl.hh | 58 ROB<Impl>::ROB(O3CPU *_cpu, DerivO3CPUParams *params) argument
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| H A D | commit_impl.hh | 84 DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params) argument
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| H A D | iew_impl.hh | 68 DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) argument
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| H A D | rename_impl.hh | 63 DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) argument
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| H A D | fetch_impl.hh | 83 DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params) argument
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| H A D | fetch.hh | 101 IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) argument
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| H A D | lsq.hh | 134 DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) argument
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| /gem5/src/arch/power/ |
| H A D | interrupts.hh | 61 setCPU(BaseCPU * _cpu) argument
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| /gem5/src/cpu/ |
| H A D | base.cc | 87 CPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival) argument
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| H A D | simple_thread.cc | 76 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, argument
87 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, argument
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| /gem5/src/arch/alpha/ |
| H A D | interrupts.hh | 78 setCPU(BaseCPU * _cpu) argument
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| /gem5/src/arch/riscv/ |
| H A D | interrupts.hh | 72 void setCPU(BaseCPU * _cpu) { cpu = _cpu; } argument
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| /gem5/src/arch/sparc/ |
| H A D | interrupts.hh | 69 setCPU(BaseCPU * _cpu) argument
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| /gem5/src/cpu/simple/ |
| H A D | atomic.hh | 119 AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu) argument
142 AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu) argument
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| H A D | timing.hh | 115 FetchTranslation(TimingSimpleCPU *_cpu) argument
164 TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu) argument
178 TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {} argument
190 IcachePort(TimingSimpleCPU *_cpu) argument
204 ITickEvent(TimingSimpleCPU *_cpu) argument
218 DcachePort(TimingSimpleCPU *_cpu) argument
244 DTickEvent(TimingSimpleCPU *_cpu) argument
[all...] |
| H A D | exec_context.hh | 171 SimpleExecContext(BaseSimpleCPU* _cpu, SimpleThread* _thread) argument
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| /gem5/src/arch/arm/ |
| H A D | interrupts.hh | 70 setCPU(BaseCPU * _cpu) argument
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| /gem5/src/cpu/kvm/ |
| H A D | base.hh | 583 KVMCpuPort(const std::string &_name, BaseKvmCPU *_cpu) argument
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| /gem5/src/dev/arm/ |
| H A D | generic_timer.hh | 286 GenericTimerISA(GenericTimer &_parent, unsigned _cpu) argument
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| /gem5/src/cpu/trace/ |
| H A D | trace_cpu.hh | 232 IcachePort(TraceCPU* _cpu) argument
273 DcachePort(TraceCPU* _cpu) argument
|