Searched refs:MISCREG_CPSR (Results 1 - 24 of 24) sorted by relevance

/gem5/src/arch/arm/tracers/
H A Dtarmac_base.cc76 const CPSR cpsr = thread->readMiscRegNoEffect(MISCREG_CPSR);
H A Dtarmac_record.hh233 (reg->regRel == ArmISA::MISCREG_CPSR);
243 RegId reg(MiscRegClass, ArmISA::MISCREG_CPSR);
H A Dtarmac_record.cc203 if (regRelIdx == MISCREG_CPSR) {
204 CPSR cpsr = thread->readMiscRegNoEffect(MISCREG_CPSR);
252 CPSR cpsr = thread->readMiscRegNoEffect(MISCREG_CPSR);
H A Dtarmac_parser.cc76 { "cpsr", MISCREG_CPSR },
683 if (it->index == MISCREG_CPSR) {
/gem5/src/arch/arm/
H A Dremote_gdb.cc210 r.cpsr = context->readMiscRegNoEffect(MISCREG_CPSR);
234 context->setMiscRegNoEffect(MISCREG_CPSR, r.cpsr);
274 r.cpsr = context->readMiscRegNoEffect(MISCREG_CPSR);
310 context->setMiscRegNoEffect(MISCREG_CPSR, r.cpsr);
H A Disa.cc224 miscRegs[MISCREG_CPSR] = cpsr;
296 miscRegs[MISCREG_CPSR] = cpsr;
458 if (misc_reg == MISCREG_CPSR) {
498 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
522 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
632 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
649 return miscRegs[MISCREG_CPSR] & 0x1;
653 return miscRegs[MISCREG_CPSR] & 0xc;
657 return miscRegs[MISCREG_CPSR] & 0x400000;
677 readMiscRegNoEffect(MISCREG_CPSR),
[all...]
H A Disa.hh424 CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
429 CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
481 CPSR cpsr = miscRegs[MISCREG_CPSR];
546 CPSR cpsr = miscRegs[MISCREG_CPSR];
647 miscRegs[MISCREG_CPSR]);
652 miscRegs[MISCREG_CPSR]));
680 miscRegs[MISCREG_CPSR]);
716 CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
H A Dfaults.cc301 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
426 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
500 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR);
525 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
555 tc->setMiscReg(MISCREG_CPSR, cpsr);
644 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
688 tc->setMiscReg(MISCREG_CPSR, cpsr);
730 CPSR M5_VAR_USED cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
757 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
759 tc->setMiscReg(MISCREG_CPSR, cps
[all...]
H A Dutility.cc185 dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
201 scr, tc->readMiscReg(MISCREG_CPSR));
214 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
340 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
472 const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
H A Dinterrupts.cc57 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
H A Dinterrupts.hh143 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
230 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
H A Dutility.hh129 return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
149 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
H A Dnativetrace.cc119 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
H A Dprocess.cc130 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
132 tc->setMiscReg(MISCREG_CPSR, cpsr);
H A Dpmu.cc501 const CPSR cpsr(pmu.isa->readMiscRegNoEffect(MISCREG_CPSR));
H A Dmiscregs.hh58 MISCREG_CPSR = 0, enumerator in enum:ArmISA::MiscRegIndex
H A Dtlb.cc1304 cpsr = tc->readMiscReg(MISCREG_CPSR);
H A Dtable_walker.cc241 TLB::tranTypeEL(_tc->readMiscReg(MISCREG_CPSR), tranType);
H A Dmiscregs.cc2893 InitReg(MISCREG_CPSR)
/gem5/src/arch/arm/insts/
H A Dmisc.cc58 if (reg.index() == MISCREG_CPSR) {
86 if (reg.index() == MISCREG_CPSR) {
H A Dmisc64.cc149 const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
377 const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
/gem5/src/arch/arm/kvm/
H A Darmv8_cpu.cc221 CPSR cpsr(tc->readMiscReg(MISCREG_CPSR));
289 tc->setMiscRegNoEffect(MISCREG_CPSR, cpsr);
H A Darm_cpu.cc236 { REG_CORE32(usr_regs.ARM_cpsr), MISCREG_CPSR, "CPSR" },
743 tc->setMiscReg(MISCREG_CPSR, tc->readMiscRegNoEffect(MISCREG_CPSR));
/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc2331 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2339 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2391 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2399 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);

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