1/*
2 * Copyright (c) 2011-2013,2017-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 *          Giacomo Travaglini
39 */
40
41#include "arch/arm/insts/misc64.hh"
42#include "arch/arm/isa.hh"
43
44std::string
45ImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
46{
47    std::stringstream ss;
48    printMnemonic(ss, "", false);
49    ccprintf(ss, "#0x%x", imm);
50    return ss.str();
51}
52
53std::string
54RegRegImmImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
55{
56    std::stringstream ss;
57    printMnemonic(ss, "", false);
58    printIntReg(ss, dest);
59    ss << ", ";
60    printIntReg(ss, op1);
61    ccprintf(ss, ", #%d, #%d", imm1, imm2);
62    return ss.str();
63}
64
65std::string
66RegRegRegImmOp64::generateDisassembly(
67    Addr pc, const SymbolTable *symtab) const
68{
69    std::stringstream ss;
70    printMnemonic(ss, "", false);
71    printIntReg(ss, dest);
72    ss << ", ";
73    printIntReg(ss, op1);
74    ss << ", ";
75    printIntReg(ss, op2);
76    ccprintf(ss, ", #%d", imm);
77    return ss.str();
78}
79
80std::string
81UnknownOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
82{
83    return csprintf("%-10s (inst %#08x)", "unknown", encoding());
84}
85
86Fault
87MiscRegOp64::trap(ThreadContext *tc, MiscRegIndex misc_reg,
88                  ExceptionLevel el, uint32_t immediate) const
89{
90    bool is_vfp_neon = false;
91
92    // Check for traps to supervisor (FP/SIMD regs)
93    if (el <= EL1 && checkEL1Trap(tc, misc_reg, el)) {
94
95        return std::make_shared<SupervisorTrap>(machInst, 0x1E00000,
96                                                EC_TRAPPED_SIMD_FP);
97    }
98
99    // Check for traps to hypervisor
100    if ((ArmSystem::haveVirtualization(tc) && el <= EL2) &&
101        checkEL2Trap(tc, misc_reg, el, &is_vfp_neon)) {
102
103        return std::make_shared<HypervisorTrap>(
104            machInst, is_vfp_neon ? 0x1E00000 : immediate,
105            is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64);
106    }
107
108    // Check for traps to secure monitor
109    if ((ArmSystem::haveSecurity(tc) && el <= EL3) &&
110        checkEL3Trap(tc, misc_reg, el, &is_vfp_neon)) {
111
112        return std::make_shared<SecureMonitorTrap>(
113            machInst,
114            is_vfp_neon ? 0x1E00000 : immediate,
115            is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64);
116    }
117
118    return NoFault;
119}
120
121bool
122MiscRegOp64::checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
123                          ExceptionLevel el) const
124{
125    const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
126
127    bool trap_to_sup = false;
128    switch (misc_reg) {
129      case MISCREG_FPCR:
130      case MISCREG_FPSR:
131      case MISCREG_FPEXC32_EL2:
132        if ((el == EL0 && cpacr.fpen != 0x3) ||
133            (el == EL1 && !(cpacr.fpen & 0x1)))
134            trap_to_sup = true;
135        break;
136      default:
137        break;
138    }
139    return trap_to_sup;
140}
141
142bool
143MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
144                          ExceptionLevel el, bool * is_vfp_neon) const
145{
146    const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL2);
147    const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
148    const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
149    const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
150
151    bool trap_to_hyp = false;
152    *is_vfp_neon = false;
153
154    if (!inSecureState(scr, cpsr) && (el != EL2)) {
155        switch (misc_reg) {
156          // FP/SIMD regs
157          case MISCREG_FPCR:
158          case MISCREG_FPSR:
159          case MISCREG_FPEXC32_EL2:
160            trap_to_hyp = cptr.tfp;
161            *is_vfp_neon = true;
162            break;
163          // CPACR
164          case MISCREG_CPACR_EL1:
165            trap_to_hyp = cptr.tcpac && el == EL1;
166            break;
167          // Virtual memory control regs
168          case MISCREG_SCTLR_EL1:
169          case MISCREG_TTBR0_EL1:
170          case MISCREG_TTBR1_EL1:
171          case MISCREG_TCR_EL1:
172          case MISCREG_ESR_EL1:
173          case MISCREG_FAR_EL1:
174          case MISCREG_AFSR0_EL1:
175          case MISCREG_AFSR1_EL1:
176          case MISCREG_MAIR_EL1:
177          case MISCREG_AMAIR_EL1:
178          case MISCREG_CONTEXTIDR_EL1:
179            trap_to_hyp =
180                ((hcr.trvm && miscRead) || (hcr.tvm && !miscRead)) &&
181                el == EL1;
182            break;
183          // TLB maintenance instructions
184          case MISCREG_TLBI_VMALLE1:
185          case MISCREG_TLBI_VAE1_Xt:
186          case MISCREG_TLBI_ASIDE1_Xt:
187          case MISCREG_TLBI_VAAE1_Xt:
188          case MISCREG_TLBI_VALE1_Xt:
189          case MISCREG_TLBI_VAALE1_Xt:
190          case MISCREG_TLBI_VMALLE1IS:
191          case MISCREG_TLBI_VAE1IS_Xt:
192          case MISCREG_TLBI_ASIDE1IS_Xt:
193          case MISCREG_TLBI_VAAE1IS_Xt:
194          case MISCREG_TLBI_VALE1IS_Xt:
195          case MISCREG_TLBI_VAALE1IS_Xt:
196            trap_to_hyp = hcr.ttlb && el == EL1;
197            break;
198          // Cache maintenance instructions to the point of unification
199          case MISCREG_IC_IVAU_Xt:
200          case MISCREG_ICIALLU:
201          case MISCREG_ICIALLUIS:
202          case MISCREG_DC_CVAU_Xt:
203            trap_to_hyp = hcr.tpu && el <= EL1;
204            break;
205          // Data/Unified cache maintenance instructions to the
206          // point of coherency
207          case MISCREG_DC_IVAC_Xt:
208          case MISCREG_DC_CIVAC_Xt:
209          case MISCREG_DC_CVAC_Xt:
210            trap_to_hyp = hcr.tpc && el <= EL1;
211            break;
212          // Data/Unified cache maintenance instructions by set/way
213          case MISCREG_DC_ISW_Xt:
214          case MISCREG_DC_CSW_Xt:
215          case MISCREG_DC_CISW_Xt:
216            trap_to_hyp = hcr.tsw && el == EL1;
217            break;
218          // ACTLR
219          case MISCREG_ACTLR_EL1:
220            trap_to_hyp = hcr.tacr && el == EL1;
221            break;
222
223          // @todo: Trap implementation-dependent functionality based on
224          // hcr.tidcp
225
226          // ID regs, group 3
227          case MISCREG_ID_PFR0_EL1:
228          case MISCREG_ID_PFR1_EL1:
229          case MISCREG_ID_DFR0_EL1:
230          case MISCREG_ID_AFR0_EL1:
231          case MISCREG_ID_MMFR0_EL1:
232          case MISCREG_ID_MMFR1_EL1:
233          case MISCREG_ID_MMFR2_EL1:
234          case MISCREG_ID_MMFR3_EL1:
235          case MISCREG_ID_ISAR0_EL1:
236          case MISCREG_ID_ISAR1_EL1:
237          case MISCREG_ID_ISAR2_EL1:
238          case MISCREG_ID_ISAR3_EL1:
239          case MISCREG_ID_ISAR4_EL1:
240          case MISCREG_ID_ISAR5_EL1:
241          case MISCREG_MVFR0_EL1:
242          case MISCREG_MVFR1_EL1:
243          case MISCREG_MVFR2_EL1:
244          case MISCREG_ID_AA64PFR0_EL1:
245          case MISCREG_ID_AA64PFR1_EL1:
246          case MISCREG_ID_AA64DFR0_EL1:
247          case MISCREG_ID_AA64DFR1_EL1:
248          case MISCREG_ID_AA64ISAR0_EL1:
249          case MISCREG_ID_AA64ISAR1_EL1:
250          case MISCREG_ID_AA64MMFR0_EL1:
251          case MISCREG_ID_AA64MMFR1_EL1:
252          case MISCREG_ID_AA64MMFR2_EL1:
253          case MISCREG_ID_AA64AFR0_EL1:
254          case MISCREG_ID_AA64AFR1_EL1:
255            assert(miscRead);
256            trap_to_hyp = hcr.tid3 && el == EL1;
257            break;
258          // ID regs, group 2
259          case MISCREG_CTR_EL0:
260          case MISCREG_CCSIDR_EL1:
261          case MISCREG_CLIDR_EL1:
262          case MISCREG_CSSELR_EL1:
263            trap_to_hyp = hcr.tid2 && el <= EL1;
264            break;
265          // ID regs, group 1
266          case MISCREG_AIDR_EL1:
267          case MISCREG_REVIDR_EL1:
268            assert(miscRead);
269            trap_to_hyp = hcr.tid1 && el == EL1;
270            break;
271          case MISCREG_IMPDEF_UNIMPL:
272            trap_to_hyp = hcr.tidcp && el == EL1;
273            break;
274          // GICv3 regs
275          case MISCREG_ICC_SGI0R_EL1:
276            if (tc->getIsaPtr()->haveGICv3CpuIfc())
277                trap_to_hyp = hcr.fmo && el == EL1;
278            break;
279          case MISCREG_ICC_SGI1R_EL1:
280          case MISCREG_ICC_ASGI1R_EL1:
281            if (tc->getIsaPtr()->haveGICv3CpuIfc())
282                trap_to_hyp = hcr.imo && el == EL1;
283            break;
284          default:
285            break;
286        }
287    }
288    return trap_to_hyp;
289}
290
291bool
292MiscRegOp64::checkEL3Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
293                          ExceptionLevel el, bool * is_vfp_neon) const
294{
295    const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL3);
296
297    bool trap_to_mon = false;
298    *is_vfp_neon = false;
299
300    switch (misc_reg) {
301      // FP/SIMD regs
302      case MISCREG_FPCR:
303      case MISCREG_FPSR:
304      case MISCREG_FPEXC32_EL2:
305        trap_to_mon = cptr.tfp;
306        *is_vfp_neon = true;
307        break;
308      // CPACR, CPTR
309      case MISCREG_CPACR_EL1:
310        if (el == EL1 || el == EL2) {
311           trap_to_mon = cptr.tcpac;
312        }
313        break;
314      case MISCREG_CPTR_EL2:
315        if (el == EL2) {
316            trap_to_mon = cptr.tcpac;
317        }
318        break;
319      default:
320        break;
321    }
322    return trap_to_mon;
323}
324
325RegVal
326MiscRegImmOp64::miscRegImm() const
327{
328    if (dest == MISCREG_SPSEL) {
329        return imm & 0x1;
330    } else if (dest == MISCREG_PAN) {
331        return (imm & 0x1) << 22;
332    } else {
333        panic("Not a valid PSTATE field register\n");
334    }
335}
336
337std::string
338MiscRegImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
339{
340    std::stringstream ss;
341    printMnemonic(ss);
342    printMiscReg(ss, dest);
343    ss << ", ";
344    ccprintf(ss, "#0x%x", imm);
345    return ss.str();
346}
347
348std::string
349MiscRegRegImmOp64::generateDisassembly(
350    Addr pc, const SymbolTable *symtab) const
351{
352    std::stringstream ss;
353    printMnemonic(ss);
354    printMiscReg(ss, dest);
355    ss << ", ";
356    printIntReg(ss, op1);
357    return ss.str();
358}
359
360std::string
361RegMiscRegImmOp64::generateDisassembly(
362    Addr pc, const SymbolTable *symtab) const
363{
364    std::stringstream ss;
365    printMnemonic(ss);
366    printIntReg(ss, dest);
367    ss << ", ";
368    printMiscReg(ss, op1);
369    return ss.str();
370}
371
372Fault
373MiscRegImplDefined64::execute(ExecContext *xc,
374                              Trace::InstRecord *traceData) const
375{
376    auto tc = xc->tcBase();
377    const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
378    const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
379
380    Fault fault = trap(tc, miscReg, el, imm);
381
382    if (fault != NoFault) {
383        return fault;
384
385    } else if (warning) {
386        warn_once("\tinstruction '%s' unimplemented\n", fullMnemonic.c_str());
387        return NoFault;
388
389    } else {
390        return std::make_shared<UndefinedInstruction>(machInst, false,
391                                                      mnemonic);
392    }
393}
394
395std::string
396MiscRegImplDefined64::generateDisassembly(Addr pc,
397                                          const SymbolTable *symtab) const
398{
399    return csprintf("%-10s (implementation defined)", fullMnemonic.c_str());
400}
401