113531Sjairo.balart@metempsy.com/* 214227Sgiacomo.travaglini@arm.com * Copyright (c) 2019 ARM Limited 314227Sgiacomo.travaglini@arm.com * All rights reserved 414227Sgiacomo.travaglini@arm.com * 514227Sgiacomo.travaglini@arm.com * The license below extends only to copyright in the software and shall 614227Sgiacomo.travaglini@arm.com * not be construed as granting a license to any other intellectual 714227Sgiacomo.travaglini@arm.com * property including but not limited to intellectual property relating 814227Sgiacomo.travaglini@arm.com * to a hardware implementation of the functionality of the software 914227Sgiacomo.travaglini@arm.com * licensed hereunder. You may use the software subject to the license 1014227Sgiacomo.travaglini@arm.com * terms below provided that you ensure that this notice is replicated 1114227Sgiacomo.travaglini@arm.com * unmodified and in its entirety in all distributions of the software, 1214227Sgiacomo.travaglini@arm.com * modified or unmodified, in source code or in binary form. 1314227Sgiacomo.travaglini@arm.com * 1413531Sjairo.balart@metempsy.com * Copyright (c) 2018 Metempsy Technology Consulting 1513531Sjairo.balart@metempsy.com * All rights reserved. 1613531Sjairo.balart@metempsy.com * 1713531Sjairo.balart@metempsy.com * Redistribution and use in source and binary forms, with or without 1813531Sjairo.balart@metempsy.com * modification, are permitted provided that the following conditions are 1913531Sjairo.balart@metempsy.com * met: redistributions of source code must retain the above copyright 2013531Sjairo.balart@metempsy.com * notice, this list of conditions and the following disclaimer; 2113531Sjairo.balart@metempsy.com * redistributions in binary form must reproduce the above copyright 2213531Sjairo.balart@metempsy.com * notice, this list of conditions and the following disclaimer in the 2313531Sjairo.balart@metempsy.com * documentation and/or other materials provided with the distribution; 2413531Sjairo.balart@metempsy.com * neither the name of the copyright holders nor the names of its 2513531Sjairo.balart@metempsy.com * contributors may be used to endorse or promote products derived from 2613531Sjairo.balart@metempsy.com * this software without specific prior written permission. 2713531Sjairo.balart@metempsy.com * 2813531Sjairo.balart@metempsy.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2913531Sjairo.balart@metempsy.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3013531Sjairo.balart@metempsy.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3113531Sjairo.balart@metempsy.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3213531Sjairo.balart@metempsy.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3313531Sjairo.balart@metempsy.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3413531Sjairo.balart@metempsy.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3513531Sjairo.balart@metempsy.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3613531Sjairo.balart@metempsy.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3713531Sjairo.balart@metempsy.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3813531Sjairo.balart@metempsy.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3913531Sjairo.balart@metempsy.com * 4013531Sjairo.balart@metempsy.com * Authors: Jairo Balart 4113531Sjairo.balart@metempsy.com */ 4213531Sjairo.balart@metempsy.com 4313531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_cpu_interface.hh" 4413531Sjairo.balart@metempsy.com 4513531Sjairo.balart@metempsy.com#include "arch/arm/isa.hh" 4613531Sjairo.balart@metempsy.com#include "debug/GIC.hh" 4713531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3.hh" 4813531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_distributor.hh" 4913531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_redistributor.hh" 5013531Sjairo.balart@metempsy.com 5113926Sgiacomo.travaglini@arm.comconst uint8_t Gicv3CPUInterface::GIC_MIN_BPR; 5213926Sgiacomo.travaglini@arm.comconst uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS; 5313926Sgiacomo.travaglini@arm.com 5413531Sjairo.balart@metempsy.comGicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id) 5513531Sjairo.balart@metempsy.com : BaseISADevice(), 5613531Sjairo.balart@metempsy.com gic(gic), 5713531Sjairo.balart@metempsy.com redistributor(nullptr), 5813531Sjairo.balart@metempsy.com distributor(nullptr), 5913531Sjairo.balart@metempsy.com cpuId(cpu_id) 6013531Sjairo.balart@metempsy.com{ 6114258Sgiacomo.travaglini@arm.com hppi.prio = 0xff; 6214258Sgiacomo.travaglini@arm.com hppi.intid = Gicv3::INTID_SPURIOUS; 6313531Sjairo.balart@metempsy.com} 6413531Sjairo.balart@metempsy.com 6513531Sjairo.balart@metempsy.comvoid 6613531Sjairo.balart@metempsy.comGicv3CPUInterface::init() 6713531Sjairo.balart@metempsy.com{ 6813531Sjairo.balart@metempsy.com redistributor = gic->getRedistributor(cpuId); 6913531Sjairo.balart@metempsy.com distributor = gic->getDistributor(); 7013531Sjairo.balart@metempsy.com} 7113531Sjairo.balart@metempsy.com 7213531Sjairo.balart@metempsy.comvoid 7314259Sgiacomo.travaglini@arm.comGicv3CPUInterface::resetHppi(uint32_t intid) 7414259Sgiacomo.travaglini@arm.com{ 7514259Sgiacomo.travaglini@arm.com if (intid == hppi.intid) 7614259Sgiacomo.travaglini@arm.com hppi.prio = 0xff; 7714259Sgiacomo.travaglini@arm.com} 7814259Sgiacomo.travaglini@arm.com 7914259Sgiacomo.travaglini@arm.comvoid 8013826Sgiacomo.travaglini@arm.comGicv3CPUInterface::setThreadContext(ThreadContext *tc) 8113826Sgiacomo.travaglini@arm.com{ 8213826Sgiacomo.travaglini@arm.com maintenanceInterrupt = gic->params()->maint_int->get(tc); 8313826Sgiacomo.travaglini@arm.com} 8413826Sgiacomo.travaglini@arm.com 8513531Sjairo.balart@metempsy.combool 8613760Sjairo.balart@metempsy.comGicv3CPUInterface::getHCREL2FMO() const 8713531Sjairo.balart@metempsy.com{ 8813531Sjairo.balart@metempsy.com HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2); 8913531Sjairo.balart@metempsy.com 9013531Sjairo.balart@metempsy.com if (hcr.tge && hcr.e2h) { 9113531Sjairo.balart@metempsy.com return false; 9213531Sjairo.balart@metempsy.com } else if (hcr.tge) { 9313531Sjairo.balart@metempsy.com return true; 9413531Sjairo.balart@metempsy.com } else { 9513531Sjairo.balart@metempsy.com return hcr.fmo; 9613531Sjairo.balart@metempsy.com } 9713531Sjairo.balart@metempsy.com} 9813531Sjairo.balart@metempsy.com 9913531Sjairo.balart@metempsy.combool 10013760Sjairo.balart@metempsy.comGicv3CPUInterface::getHCREL2IMO() const 10113531Sjairo.balart@metempsy.com{ 10213531Sjairo.balart@metempsy.com HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2); 10313531Sjairo.balart@metempsy.com 10413531Sjairo.balart@metempsy.com if (hcr.tge && hcr.e2h) { 10513531Sjairo.balart@metempsy.com return false; 10613531Sjairo.balart@metempsy.com } else if (hcr.tge) { 10713531Sjairo.balart@metempsy.com return true; 10813531Sjairo.balart@metempsy.com } else { 10913531Sjairo.balart@metempsy.com return hcr.imo; 11013531Sjairo.balart@metempsy.com } 11113531Sjairo.balart@metempsy.com} 11213531Sjairo.balart@metempsy.com 11313580Sgabeblack@google.comRegVal 11413531Sjairo.balart@metempsy.comGicv3CPUInterface::readMiscReg(int misc_reg) 11513531Sjairo.balart@metempsy.com{ 11613580Sgabeblack@google.com RegVal value = isa->readMiscRegNoEffect(misc_reg); 11713531Sjairo.balart@metempsy.com bool hcr_fmo = getHCREL2FMO(); 11813531Sjairo.balart@metempsy.com bool hcr_imo = getHCREL2IMO(); 11913531Sjairo.balart@metempsy.com 12013531Sjairo.balart@metempsy.com switch (misc_reg) { 12113760Sjairo.balart@metempsy.com // Active Priorities Group 1 Registers 12213531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0: 12313531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0_EL1: { 12413531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 12513531Sjairo.balart@metempsy.com return isa->readMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1); 12613531Sjairo.balart@metempsy.com } 12713531Sjairo.balart@metempsy.com 12814246Sgiacomo.travaglini@arm.com return readBankedMiscReg(MISCREG_ICC_AP1R0_EL1); 12913531Sjairo.balart@metempsy.com } 13013531Sjairo.balart@metempsy.com 13113531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1: 13213531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1_EL1: 13313531Sjairo.balart@metempsy.com 13413531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 13513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2: 13613531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2_EL1: 13713531Sjairo.balart@metempsy.com 13813531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 13913531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3: 14013531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3_EL1: 14113531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 14213531Sjairo.balart@metempsy.com return 0; 14313531Sjairo.balart@metempsy.com 14413760Sjairo.balart@metempsy.com // Active Priorities Group 0 Registers 14513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0: 14613531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0_EL1: { 14713531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 14813531Sjairo.balart@metempsy.com return isa->readMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1); 14913531Sjairo.balart@metempsy.com } 15013531Sjairo.balart@metempsy.com 15113531Sjairo.balart@metempsy.com break; 15213531Sjairo.balart@metempsy.com } 15313531Sjairo.balart@metempsy.com 15413531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1: 15513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1_EL1: 15613531Sjairo.balart@metempsy.com 15713531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 15813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2: 15913531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2_EL1: 16013531Sjairo.balart@metempsy.com 16113531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 16213531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3: 16313531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3_EL1: 16413531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 16513531Sjairo.balart@metempsy.com return 0; 16613531Sjairo.balart@metempsy.com 16713760Sjairo.balart@metempsy.com // Interrupt Group 0 Enable register EL1 16813531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0: 16913531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0_EL1: { 17013531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 17114057Sgiacomo.travaglini@arm.com return readMiscReg(MISCREG_ICV_IGRPEN0_EL1); 17213531Sjairo.balart@metempsy.com } 17313531Sjairo.balart@metempsy.com 17413531Sjairo.balart@metempsy.com break; 17513531Sjairo.balart@metempsy.com } 17613531Sjairo.balart@metempsy.com 17714057Sgiacomo.travaglini@arm.com case MISCREG_ICV_IGRPEN0_EL1: { 17814057Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 17914057Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 18014057Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VENG0; 18114057Sgiacomo.travaglini@arm.com break; 18214057Sgiacomo.travaglini@arm.com } 18314057Sgiacomo.travaglini@arm.com 18413760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register EL1 18513531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1: 18613531Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1_EL1: { 18713531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 18814057Sgiacomo.travaglini@arm.com return readMiscReg(MISCREG_ICV_IGRPEN1_EL1); 18913531Sjairo.balart@metempsy.com } 19013531Sjairo.balart@metempsy.com 19114247Sgiacomo.travaglini@arm.com value = readBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1); 19213531Sjairo.balart@metempsy.com break; 19313531Sjairo.balart@metempsy.com } 19413531Sjairo.balart@metempsy.com 19514057Sgiacomo.travaglini@arm.com case MISCREG_ICV_IGRPEN1_EL1: { 19614057Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 19714057Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 19814057Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VENG1; 19914057Sgiacomo.travaglini@arm.com break; 20014057Sgiacomo.travaglini@arm.com } 20114057Sgiacomo.travaglini@arm.com 20213760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register EL3 20313760Sjairo.balart@metempsy.com case MISCREG_ICC_MGRPEN1: 20414254Sgiacomo.travaglini@arm.com case MISCREG_ICC_IGRPEN1_EL3: { 20514254Sgiacomo.travaglini@arm.com ICC_IGRPEN1_EL3 igrp_el3 = 0; 20614254Sgiacomo.travaglini@arm.com igrp_el3.EnableGrp1S = ((ICC_IGRPEN1_EL1)isa->readMiscRegNoEffect( 20714254Sgiacomo.travaglini@arm.com MISCREG_ICC_IGRPEN1_EL1_S)).Enable; 20814254Sgiacomo.travaglini@arm.com 20914254Sgiacomo.travaglini@arm.com igrp_el3.EnableGrp1NS = ((ICC_IGRPEN1_EL1)isa->readMiscRegNoEffect( 21014254Sgiacomo.travaglini@arm.com MISCREG_ICC_IGRPEN1_EL1_NS)).Enable; 21114254Sgiacomo.travaglini@arm.com 21214254Sgiacomo.travaglini@arm.com value = igrp_el3; 21313739Sgiacomo.travaglini@arm.com break; 21414254Sgiacomo.travaglini@arm.com } 21513760Sjairo.balart@metempsy.com 21613760Sjairo.balart@metempsy.com // Running Priority Register 21713531Sjairo.balart@metempsy.com case MISCREG_ICC_RPR: 21813531Sjairo.balart@metempsy.com case MISCREG_ICC_RPR_EL1: { 21913531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && 22013760Sjairo.balart@metempsy.com (hcr_imo || hcr_fmo)) { 22113531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_RPR_EL1); 22213531Sjairo.balart@metempsy.com } 22313531Sjairo.balart@metempsy.com 22413531Sjairo.balart@metempsy.com uint8_t rprio = highestActivePriority(); 22513531Sjairo.balart@metempsy.com 22613531Sjairo.balart@metempsy.com if (haveEL(EL3) && !inSecureState() && 22713760Sjairo.balart@metempsy.com (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) { 22813760Sjairo.balart@metempsy.com // Spec section 4.8.1 22913760Sjairo.balart@metempsy.com // For Non-secure access to ICC_RPR_EL1 when SCR_EL3.FIQ == 1 23013531Sjairo.balart@metempsy.com if ((rprio & 0x80) == 0) { 23113760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 23213760Sjairo.balart@metempsy.com // 0x00-0x7F a read access returns the value 0x0 23313531Sjairo.balart@metempsy.com rprio = 0; 23413531Sjairo.balart@metempsy.com } else if (rprio != 0xff) { 23513760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 23613760Sjairo.balart@metempsy.com // 0x80-0xFF a read access returns the Non-secure read of 23713760Sjairo.balart@metempsy.com // the current value 23813531Sjairo.balart@metempsy.com rprio = (rprio << 1) & 0xff; 23913531Sjairo.balart@metempsy.com } 24013531Sjairo.balart@metempsy.com } 24113531Sjairo.balart@metempsy.com 24213531Sjairo.balart@metempsy.com value = rprio; 24313531Sjairo.balart@metempsy.com break; 24413531Sjairo.balart@metempsy.com } 24513531Sjairo.balart@metempsy.com 24613760Sjairo.balart@metempsy.com // Virtual Running Priority Register 24713531Sjairo.balart@metempsy.com case MISCREG_ICV_RPR_EL1: { 24813531Sjairo.balart@metempsy.com value = virtualHighestActivePriority(); 24913531Sjairo.balart@metempsy.com break; 25013531Sjairo.balart@metempsy.com } 25113531Sjairo.balart@metempsy.com 25213760Sjairo.balart@metempsy.com // Highest Priority Pending Interrupt Register 0 25313531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR0: 25413531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR0_EL1: { 25513531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 25613531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_HPPIR0_EL1); 25713531Sjairo.balart@metempsy.com } 25813531Sjairo.balart@metempsy.com 25913531Sjairo.balart@metempsy.com value = getHPPIR0(); 26013531Sjairo.balart@metempsy.com break; 26113531Sjairo.balart@metempsy.com } 26213531Sjairo.balart@metempsy.com 26313760Sjairo.balart@metempsy.com // Virtual Highest Priority Pending Interrupt Register 0 26413531Sjairo.balart@metempsy.com case MISCREG_ICV_HPPIR0_EL1: { 26513531Sjairo.balart@metempsy.com value = Gicv3::INTID_SPURIOUS; 26613531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 26713531Sjairo.balart@metempsy.com 26813531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 26913760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 27013531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 27113531Sjairo.balart@metempsy.com Gicv3::GroupId group = 27213760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 27313531Sjairo.balart@metempsy.com 27413531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 27513760Sjairo.balart@metempsy.com value = ich_lr_el2.vINTID; 27613531Sjairo.balart@metempsy.com } 27713531Sjairo.balart@metempsy.com } 27813531Sjairo.balart@metempsy.com 27913531Sjairo.balart@metempsy.com break; 28013531Sjairo.balart@metempsy.com } 28113531Sjairo.balart@metempsy.com 28213760Sjairo.balart@metempsy.com // Highest Priority Pending Interrupt Register 1 28313531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR1: 28413531Sjairo.balart@metempsy.com case MISCREG_ICC_HPPIR1_EL1: { 28513531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 28613531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_HPPIR1_EL1); 28713531Sjairo.balart@metempsy.com } 28813531Sjairo.balart@metempsy.com 28913531Sjairo.balart@metempsy.com value = getHPPIR1(); 29013531Sjairo.balart@metempsy.com break; 29113531Sjairo.balart@metempsy.com } 29213531Sjairo.balart@metempsy.com 29313760Sjairo.balart@metempsy.com // Virtual Highest Priority Pending Interrupt Register 1 29413531Sjairo.balart@metempsy.com case MISCREG_ICV_HPPIR1_EL1: { 29513531Sjairo.balart@metempsy.com value = Gicv3::INTID_SPURIOUS; 29613531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 29713531Sjairo.balart@metempsy.com 29813531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 29913760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 30013531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 30113531Sjairo.balart@metempsy.com Gicv3::GroupId group = 30213760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 30313531Sjairo.balart@metempsy.com 30413531Sjairo.balart@metempsy.com if (group == Gicv3::G1NS) { 30513760Sjairo.balart@metempsy.com value = ich_lr_el2.vINTID; 30613531Sjairo.balart@metempsy.com } 30713531Sjairo.balart@metempsy.com } 30813531Sjairo.balart@metempsy.com 30913531Sjairo.balart@metempsy.com break; 31013531Sjairo.balart@metempsy.com } 31113531Sjairo.balart@metempsy.com 31213760Sjairo.balart@metempsy.com // Binary Point Register 0 31313531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR0: 31414237Sgiacomo.travaglini@arm.com case MISCREG_ICC_BPR0_EL1: { 31513531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 31613531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_BPR0_EL1); 31713531Sjairo.balart@metempsy.com } 31813531Sjairo.balart@metempsy.com 31914237Sgiacomo.travaglini@arm.com value = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1); 32014237Sgiacomo.travaglini@arm.com break; 32114237Sgiacomo.travaglini@arm.com } 32213531Sjairo.balart@metempsy.com 32313760Sjairo.balart@metempsy.com // Binary Point Register 1 32413531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1: 32513760Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1_EL1: { 32614237Sgiacomo.travaglini@arm.com value = bpr1(isSecureBelowEL3() ? Gicv3::G1S : Gicv3::G1NS); 32714237Sgiacomo.travaglini@arm.com break; 32813760Sjairo.balart@metempsy.com } 32913760Sjairo.balart@metempsy.com 33014237Sgiacomo.travaglini@arm.com // Virtual Binary Point Register 0 33114237Sgiacomo.travaglini@arm.com case MISCREG_ICV_BPR0_EL1: { 33214237Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 33314237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 33414237Sgiacomo.travaglini@arm.com 33514237Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VBPR0; 33614237Sgiacomo.travaglini@arm.com break; 33714237Sgiacomo.travaglini@arm.com } 33814237Sgiacomo.travaglini@arm.com 33913760Sjairo.balart@metempsy.com // Virtual Binary Point Register 1 34013531Sjairo.balart@metempsy.com case MISCREG_ICV_BPR1_EL1: { 34114237Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 34214237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 34314237Sgiacomo.travaglini@arm.com 34414237Sgiacomo.travaglini@arm.com if (ich_vmcr_el2.VCBPR) { 34514237Sgiacomo.travaglini@arm.com // bpr0 + 1 saturated to 7, WI 34614237Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VBPR0 + 1; 34714237Sgiacomo.travaglini@arm.com value = value < 7 ? value : 7; 34814237Sgiacomo.travaglini@arm.com } else { 34914237Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VBPR1; 35014237Sgiacomo.travaglini@arm.com } 35114237Sgiacomo.travaglini@arm.com 35214237Sgiacomo.travaglini@arm.com break; 35313531Sjairo.balart@metempsy.com } 35413531Sjairo.balart@metempsy.com 35513760Sjairo.balart@metempsy.com // Interrupt Priority Mask Register 35613531Sjairo.balart@metempsy.com case MISCREG_ICC_PMR: 35713760Sjairo.balart@metempsy.com case MISCREG_ICC_PMR_EL1: 35813760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 35914057Sgiacomo.travaglini@arm.com return readMiscReg(MISCREG_ICV_PMR_EL1); 36013531Sjairo.balart@metempsy.com } 36113531Sjairo.balart@metempsy.com 36213531Sjairo.balart@metempsy.com if (haveEL(EL3) && !inSecureState() && 36313760Sjairo.balart@metempsy.com (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) { 36413760Sjairo.balart@metempsy.com // Spec section 4.8.1 36513760Sjairo.balart@metempsy.com // For Non-secure access to ICC_PMR_EL1 when SCR_EL3.FIQ == 1: 36613531Sjairo.balart@metempsy.com if ((value & 0x80) == 0) { 36713760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 36813760Sjairo.balart@metempsy.com // 0x00-0x7F a read access returns the value 0x00. 36913531Sjairo.balart@metempsy.com value = 0; 37013531Sjairo.balart@metempsy.com } else if (value != 0xff) { 37113760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 37213760Sjairo.balart@metempsy.com // 0x80-0xFF a read access returns the Non-secure read of the 37313760Sjairo.balart@metempsy.com // current value. 37413531Sjairo.balart@metempsy.com value = (value << 1) & 0xff; 37513531Sjairo.balart@metempsy.com } 37613531Sjairo.balart@metempsy.com } 37713531Sjairo.balart@metempsy.com 37813531Sjairo.balart@metempsy.com break; 37913531Sjairo.balart@metempsy.com 38014057Sgiacomo.travaglini@arm.com case MISCREG_ICV_PMR_EL1: { // Priority Mask Register 38114057Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 38214057Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 38314057Sgiacomo.travaglini@arm.com 38414057Sgiacomo.travaglini@arm.com value = ich_vmcr_el2.VPMR; 38514057Sgiacomo.travaglini@arm.com break; 38614057Sgiacomo.travaglini@arm.com } 38714057Sgiacomo.travaglini@arm.com 38813760Sjairo.balart@metempsy.com // Interrupt Acknowledge Register 0 38913531Sjairo.balart@metempsy.com case MISCREG_ICC_IAR0: 39013760Sjairo.balart@metempsy.com case MISCREG_ICC_IAR0_EL1: { 39113531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 39213531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_IAR0_EL1); 39313531Sjairo.balart@metempsy.com } 39413531Sjairo.balart@metempsy.com 39513531Sjairo.balart@metempsy.com uint32_t int_id; 39613531Sjairo.balart@metempsy.com 39713531Sjairo.balart@metempsy.com if (hppiCanPreempt()) { 39813531Sjairo.balart@metempsy.com int_id = getHPPIR0(); 39913531Sjairo.balart@metempsy.com 40013531Sjairo.balart@metempsy.com // avoid activation for special interrupts 40113923Sgiacomo.travaglini@arm.com if (int_id < Gicv3::INTID_SECURE || 40213923Sgiacomo.travaglini@arm.com int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 40313531Sjairo.balart@metempsy.com activateIRQ(int_id, hppi.group); 40413531Sjairo.balart@metempsy.com } 40513531Sjairo.balart@metempsy.com } else { 40613531Sjairo.balart@metempsy.com int_id = Gicv3::INTID_SPURIOUS; 40713531Sjairo.balart@metempsy.com } 40813531Sjairo.balart@metempsy.com 40913531Sjairo.balart@metempsy.com value = int_id; 41013531Sjairo.balart@metempsy.com break; 41113531Sjairo.balart@metempsy.com } 41213531Sjairo.balart@metempsy.com 41313760Sjairo.balart@metempsy.com // Virtual Interrupt Acknowledge Register 0 41413531Sjairo.balart@metempsy.com case MISCREG_ICV_IAR0_EL1: { 41513531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 41613531Sjairo.balart@metempsy.com uint32_t int_id = Gicv3::INTID_SPURIOUS; 41713531Sjairo.balart@metempsy.com 41813531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 41913760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 42013531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 42113531Sjairo.balart@metempsy.com 42213760Sjairo.balart@metempsy.com if (!ich_lr_el2.Group && hppviCanPreempt(lr_idx)) { 42313760Sjairo.balart@metempsy.com int_id = ich_lr_el2.vINTID; 42413531Sjairo.balart@metempsy.com 42513531Sjairo.balart@metempsy.com if (int_id < Gicv3::INTID_SECURE || 42613760Sjairo.balart@metempsy.com int_id > Gicv3::INTID_SPURIOUS) { 42713531Sjairo.balart@metempsy.com virtualActivateIRQ(lr_idx); 42813531Sjairo.balart@metempsy.com } else { 42913531Sjairo.balart@metempsy.com // Bogus... Pseudocode says: 43013531Sjairo.balart@metempsy.com // - Move from pending to invalid... 43113531Sjairo.balart@metempsy.com // - Return de bogus id... 43213760Sjairo.balart@metempsy.com ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID; 43313531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, 43413760Sjairo.balart@metempsy.com ich_lr_el2); 43513531Sjairo.balart@metempsy.com } 43613531Sjairo.balart@metempsy.com } 43713531Sjairo.balart@metempsy.com } 43813531Sjairo.balart@metempsy.com 43913531Sjairo.balart@metempsy.com value = int_id; 44013531Sjairo.balart@metempsy.com virtualUpdate(); 44113531Sjairo.balart@metempsy.com break; 44213531Sjairo.balart@metempsy.com } 44313531Sjairo.balart@metempsy.com 44413760Sjairo.balart@metempsy.com // Interrupt Acknowledge Register 1 44513531Sjairo.balart@metempsy.com case MISCREG_ICC_IAR1: 44613760Sjairo.balart@metempsy.com case MISCREG_ICC_IAR1_EL1: { 44713531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 44813531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_IAR1_EL1); 44913531Sjairo.balart@metempsy.com } 45013531Sjairo.balart@metempsy.com 45113531Sjairo.balart@metempsy.com uint32_t int_id; 45213531Sjairo.balart@metempsy.com 45313531Sjairo.balart@metempsy.com if (hppiCanPreempt()) { 45413531Sjairo.balart@metempsy.com int_id = getHPPIR1(); 45513531Sjairo.balart@metempsy.com 45613531Sjairo.balart@metempsy.com // avoid activation for special interrupts 45713923Sgiacomo.travaglini@arm.com if (int_id < Gicv3::INTID_SECURE || 45813923Sgiacomo.travaglini@arm.com int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 45913531Sjairo.balart@metempsy.com activateIRQ(int_id, hppi.group); 46013531Sjairo.balart@metempsy.com } 46113531Sjairo.balart@metempsy.com } else { 46213531Sjairo.balart@metempsy.com int_id = Gicv3::INTID_SPURIOUS; 46313531Sjairo.balart@metempsy.com } 46413531Sjairo.balart@metempsy.com 46513531Sjairo.balart@metempsy.com value = int_id; 46613531Sjairo.balart@metempsy.com break; 46713531Sjairo.balart@metempsy.com } 46813531Sjairo.balart@metempsy.com 46913760Sjairo.balart@metempsy.com // Virtual Interrupt Acknowledge Register 1 47013531Sjairo.balart@metempsy.com case MISCREG_ICV_IAR1_EL1: { 47113531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 47213531Sjairo.balart@metempsy.com uint32_t int_id = Gicv3::INTID_SPURIOUS; 47313531Sjairo.balart@metempsy.com 47413531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 47513760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 47613531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 47713531Sjairo.balart@metempsy.com 47813760Sjairo.balart@metempsy.com if (ich_lr_el2.Group && hppviCanPreempt(lr_idx)) { 47913760Sjairo.balart@metempsy.com int_id = ich_lr_el2.vINTID; 48013531Sjairo.balart@metempsy.com 48113531Sjairo.balart@metempsy.com if (int_id < Gicv3::INTID_SECURE || 48213760Sjairo.balart@metempsy.com int_id > Gicv3::INTID_SPURIOUS) { 48313531Sjairo.balart@metempsy.com virtualActivateIRQ(lr_idx); 48413531Sjairo.balart@metempsy.com } else { 48513531Sjairo.balart@metempsy.com // Bogus... Pseudocode says: 48613531Sjairo.balart@metempsy.com // - Move from pending to invalid... 48713531Sjairo.balart@metempsy.com // - Return de bogus id... 48813760Sjairo.balart@metempsy.com ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID; 48913531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, 49013760Sjairo.balart@metempsy.com ich_lr_el2); 49113531Sjairo.balart@metempsy.com } 49213531Sjairo.balart@metempsy.com } 49313531Sjairo.balart@metempsy.com } 49413531Sjairo.balart@metempsy.com 49513531Sjairo.balart@metempsy.com value = int_id; 49613531Sjairo.balart@metempsy.com virtualUpdate(); 49713531Sjairo.balart@metempsy.com break; 49813531Sjairo.balart@metempsy.com } 49913531Sjairo.balart@metempsy.com 50013760Sjairo.balart@metempsy.com // System Register Enable Register EL1 50113531Sjairo.balart@metempsy.com case MISCREG_ICC_SRE: 50213760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL1: { 50313531Sjairo.balart@metempsy.com /* 50413531Sjairo.balart@metempsy.com * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 50513531Sjairo.balart@metempsy.com * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 50613531Sjairo.balart@metempsy.com * SRE [0] == 1 (Only system register interface supported, RAO/WI) 50713531Sjairo.balart@metempsy.com */ 50813760Sjairo.balart@metempsy.com ICC_SRE_EL1 icc_sre_el1 = 0; 50913760Sjairo.balart@metempsy.com icc_sre_el1.SRE = 1; 51013760Sjairo.balart@metempsy.com icc_sre_el1.DIB = 1; 51113760Sjairo.balart@metempsy.com icc_sre_el1.DFB = 1; 51213760Sjairo.balart@metempsy.com value = icc_sre_el1; 51313760Sjairo.balart@metempsy.com break; 51413760Sjairo.balart@metempsy.com } 51513760Sjairo.balart@metempsy.com 51613760Sjairo.balart@metempsy.com // System Register Enable Register EL2 51713760Sjairo.balart@metempsy.com case MISCREG_ICC_HSRE: 51813760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL2: { 51913531Sjairo.balart@metempsy.com /* 52013531Sjairo.balart@metempsy.com * Enable [3] == 1 52113760Sjairo.balart@metempsy.com * (EL1 accesses to ICC_SRE_EL1 do not trap to EL2, RAO/WI) 52213531Sjairo.balart@metempsy.com * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 52313531Sjairo.balart@metempsy.com * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 52413531Sjairo.balart@metempsy.com * SRE [0] == 1 (Only system register interface supported, RAO/WI) 52513531Sjairo.balart@metempsy.com */ 52613760Sjairo.balart@metempsy.com ICC_SRE_EL2 icc_sre_el2 = 0; 52713760Sjairo.balart@metempsy.com icc_sre_el2.SRE = 1; 52813760Sjairo.balart@metempsy.com icc_sre_el2.DIB = 1; 52913760Sjairo.balart@metempsy.com icc_sre_el2.DFB = 1; 53013760Sjairo.balart@metempsy.com icc_sre_el2.Enable = 1; 53113760Sjairo.balart@metempsy.com value = icc_sre_el2; 53213531Sjairo.balart@metempsy.com break; 53313760Sjairo.balart@metempsy.com } 53413760Sjairo.balart@metempsy.com 53513760Sjairo.balart@metempsy.com // System Register Enable Register EL3 53613760Sjairo.balart@metempsy.com case MISCREG_ICC_MSRE: 53713760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL3: { 53813760Sjairo.balart@metempsy.com /* 53913760Sjairo.balart@metempsy.com * Enable [3] == 1 54013760Sjairo.balart@metempsy.com * (EL1 accesses to ICC_SRE_EL1 do not trap to EL3. 54113760Sjairo.balart@metempsy.com * EL2 accesses to ICC_SRE_EL1 and ICC_SRE_EL2 do not trap to EL3. 54213760Sjairo.balart@metempsy.com * RAO/WI) 54313760Sjairo.balart@metempsy.com * DIB [2] == 1 (IRQ bypass not supported, RAO/WI) 54413760Sjairo.balart@metempsy.com * DFB [1] == 1 (FIQ bypass not supported, RAO/WI) 54513760Sjairo.balart@metempsy.com * SRE [0] == 1 (Only system register interface supported, RAO/WI) 54613760Sjairo.balart@metempsy.com */ 54713760Sjairo.balart@metempsy.com ICC_SRE_EL3 icc_sre_el3 = 0; 54813760Sjairo.balart@metempsy.com icc_sre_el3.SRE = 1; 54913760Sjairo.balart@metempsy.com icc_sre_el3.DIB = 1; 55013760Sjairo.balart@metempsy.com icc_sre_el3.DFB = 1; 55113760Sjairo.balart@metempsy.com icc_sre_el3.Enable = 1; 55213760Sjairo.balart@metempsy.com value = icc_sre_el3; 55313760Sjairo.balart@metempsy.com break; 55413760Sjairo.balart@metempsy.com } 55513760Sjairo.balart@metempsy.com 55613760Sjairo.balart@metempsy.com // Control Register 55713531Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR: 55813760Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL1: { 55913760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 56013531Sjairo.balart@metempsy.com return readMiscReg(MISCREG_ICV_CTLR_EL1); 56113531Sjairo.balart@metempsy.com } 56213531Sjairo.balart@metempsy.com 56314245Sgiacomo.travaglini@arm.com value = readBankedMiscReg(MISCREG_ICC_CTLR_EL1); 56413760Sjairo.balart@metempsy.com // Enforce value for RO bits 56513760Sjairo.balart@metempsy.com // ExtRange [19], INTIDs in the range 1024..8191 not supported 56613760Sjairo.balart@metempsy.com // RSS [18], SGIs with affinity level 0 values of 0-255 are supported 56713760Sjairo.balart@metempsy.com // A3V [15], supports non-zero values of the Aff3 field in SGI 56813760Sjairo.balart@metempsy.com // generation System registers 56913760Sjairo.balart@metempsy.com // SEIS [14], does not support generation of SEIs (deprecated) 57013531Sjairo.balart@metempsy.com // IDbits [13:11], 001 = 24 bits | 000 = 16 bits 57113531Sjairo.balart@metempsy.com // PRIbits [10:8], number of priority bits implemented, minus one 57213760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1 = value; 57313760Sjairo.balart@metempsy.com icc_ctlr_el1.ExtRange = 0; 57413760Sjairo.balart@metempsy.com icc_ctlr_el1.RSS = 1; 57513760Sjairo.balart@metempsy.com icc_ctlr_el1.A3V = 1; 57613760Sjairo.balart@metempsy.com icc_ctlr_el1.SEIS = 0; 57713760Sjairo.balart@metempsy.com icc_ctlr_el1.IDbits = 1; 57813760Sjairo.balart@metempsy.com icc_ctlr_el1.PRIbits = PRIORITY_BITS - 1; 57913760Sjairo.balart@metempsy.com value = icc_ctlr_el1; 58013531Sjairo.balart@metempsy.com break; 58113531Sjairo.balart@metempsy.com } 58213531Sjairo.balart@metempsy.com 58313760Sjairo.balart@metempsy.com // Virtual Control Register 58413531Sjairo.balart@metempsy.com case MISCREG_ICV_CTLR_EL1: { 58513760Sjairo.balart@metempsy.com ICV_CTLR_EL1 icv_ctlr_el1 = value; 58613760Sjairo.balart@metempsy.com icv_ctlr_el1.RSS = 0; 58713760Sjairo.balart@metempsy.com icv_ctlr_el1.A3V = 1; 58813760Sjairo.balart@metempsy.com icv_ctlr_el1.SEIS = 0; 58913760Sjairo.balart@metempsy.com icv_ctlr_el1.IDbits = 1; 59013760Sjairo.balart@metempsy.com icv_ctlr_el1.PRIbits = 7; 59113760Sjairo.balart@metempsy.com value = icv_ctlr_el1; 59213531Sjairo.balart@metempsy.com break; 59313531Sjairo.balart@metempsy.com } 59413531Sjairo.balart@metempsy.com 59513760Sjairo.balart@metempsy.com // Control Register 59613531Sjairo.balart@metempsy.com case MISCREG_ICC_MCTLR: 59713531Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL3: { 59813760Sjairo.balart@metempsy.com // Enforce value for RO bits 59913760Sjairo.balart@metempsy.com // ExtRange [19], INTIDs in the range 1024..8191 not supported 60013760Sjairo.balart@metempsy.com // RSS [18], SGIs with affinity level 0 values of 0-255 are supported 60113760Sjairo.balart@metempsy.com // nDS [17], supports disabling of security 60213760Sjairo.balart@metempsy.com // A3V [15], supports non-zero values of the Aff3 field in SGI 60313760Sjairo.balart@metempsy.com // generation System registers 60413760Sjairo.balart@metempsy.com // SEIS [14], does not support generation of SEIs (deprecated) 60513531Sjairo.balart@metempsy.com // IDbits [13:11], 001 = 24 bits | 000 = 16 bits 60613531Sjairo.balart@metempsy.com // PRIbits [10:8], number of priority bits implemented, minus one 60713760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = value; 60813760Sjairo.balart@metempsy.com icc_ctlr_el3.ExtRange = 0; 60913760Sjairo.balart@metempsy.com icc_ctlr_el3.RSS = 1; 61013760Sjairo.balart@metempsy.com icc_ctlr_el3.nDS = 0; 61113760Sjairo.balart@metempsy.com icc_ctlr_el3.A3V = 1; 61213760Sjairo.balart@metempsy.com icc_ctlr_el3.SEIS = 0; 61313760Sjairo.balart@metempsy.com icc_ctlr_el3.IDbits = 0; 61413760Sjairo.balart@metempsy.com icc_ctlr_el3.PRIbits = PRIORITY_BITS - 1; 61513760Sjairo.balart@metempsy.com value = icc_ctlr_el3; 61613531Sjairo.balart@metempsy.com break; 61713531Sjairo.balart@metempsy.com } 61813531Sjairo.balart@metempsy.com 61913760Sjairo.balart@metempsy.com // Hyp Control Register 62013531Sjairo.balart@metempsy.com case MISCREG_ICH_HCR: 62113531Sjairo.balart@metempsy.com case MISCREG_ICH_HCR_EL2: 62213531Sjairo.balart@metempsy.com break; 62313531Sjairo.balart@metempsy.com 62413760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 0 Registers 62513531Sjairo.balart@metempsy.com case MISCREG_ICH_AP0R0: 62613531Sjairo.balart@metempsy.com case MISCREG_ICH_AP0R0_EL2: 62713531Sjairo.balart@metempsy.com break; 62813531Sjairo.balart@metempsy.com 62914236Sgiacomo.travaglini@arm.com // only implemented if supporting 6 or more bits of priority 63014236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R1: 63114236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R1_EL2: 63214236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 63314236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R2: 63414236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R2_EL2: 63514236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 63614236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R3: 63714236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R3_EL2: 63814236Sgiacomo.travaglini@arm.com // Unimplemented registers are RAZ/WI 63914236Sgiacomo.travaglini@arm.com return 0; 64014236Sgiacomo.travaglini@arm.com 64113760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 1 Registers 64213531Sjairo.balart@metempsy.com case MISCREG_ICH_AP1R0: 64313531Sjairo.balart@metempsy.com case MISCREG_ICH_AP1R0_EL2: 64413531Sjairo.balart@metempsy.com break; 64513531Sjairo.balart@metempsy.com 64614236Sgiacomo.travaglini@arm.com // only implemented if supporting 6 or more bits of priority 64714236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R1: 64814236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R1_EL2: 64914236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 65014236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R2: 65114236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R2_EL2: 65214236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 65314236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R3: 65414236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R3_EL2: 65514236Sgiacomo.travaglini@arm.com // Unimplemented registers are RAZ/WI 65614236Sgiacomo.travaglini@arm.com return 0; 65714236Sgiacomo.travaglini@arm.com 65813760Sjairo.balart@metempsy.com // Maintenance Interrupt State Register 65913531Sjairo.balart@metempsy.com case MISCREG_ICH_MISR: 66013760Sjairo.balart@metempsy.com case MISCREG_ICH_MISR_EL2: 66113760Sjairo.balart@metempsy.com value = maintenanceInterruptStatus(); 66213760Sjairo.balart@metempsy.com break; 66313760Sjairo.balart@metempsy.com 66413760Sjairo.balart@metempsy.com // VGIC Type Register 66513760Sjairo.balart@metempsy.com case MISCREG_ICH_VTR: 66613760Sjairo.balart@metempsy.com case MISCREG_ICH_VTR_EL2: { 66713760Sjairo.balart@metempsy.com ICH_VTR_EL2 ich_vtr_el2 = value; 66813760Sjairo.balart@metempsy.com 66913760Sjairo.balart@metempsy.com ich_vtr_el2.ListRegs = VIRTUAL_NUM_LIST_REGS - 1; 67013760Sjairo.balart@metempsy.com ich_vtr_el2.A3V = 1; 67113760Sjairo.balart@metempsy.com ich_vtr_el2.IDbits = 1; 67213760Sjairo.balart@metempsy.com ich_vtr_el2.PREbits = VIRTUAL_PREEMPTION_BITS - 1; 67313760Sjairo.balart@metempsy.com ich_vtr_el2.PRIbits = VIRTUAL_PRIORITY_BITS - 1; 67413760Sjairo.balart@metempsy.com 67513760Sjairo.balart@metempsy.com value = ich_vtr_el2; 67613760Sjairo.balart@metempsy.com break; 67713531Sjairo.balart@metempsy.com } 67813531Sjairo.balart@metempsy.com 67913760Sjairo.balart@metempsy.com // End of Interrupt Status Register 68013531Sjairo.balart@metempsy.com case MISCREG_ICH_EISR: 68113531Sjairo.balart@metempsy.com case MISCREG_ICH_EISR_EL2: 68213760Sjairo.balart@metempsy.com value = eoiMaintenanceInterruptStatus(); 68313531Sjairo.balart@metempsy.com break; 68413531Sjairo.balart@metempsy.com 68513760Sjairo.balart@metempsy.com // Empty List Register Status Register 68613531Sjairo.balart@metempsy.com case MISCREG_ICH_ELRSR: 68713531Sjairo.balart@metempsy.com case MISCREG_ICH_ELRSR_EL2: 68813531Sjairo.balart@metempsy.com value = 0; 68913531Sjairo.balart@metempsy.com 69013531Sjairo.balart@metempsy.com for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 69113760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 69213531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 69313531Sjairo.balart@metempsy.com 69413760Sjairo.balart@metempsy.com if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) && 69513760Sjairo.balart@metempsy.com (ich_lr_el2.HW || !ich_lr_el2.EOI)) { 69613531Sjairo.balart@metempsy.com value |= (1 << lr_idx); 69713531Sjairo.balart@metempsy.com } 69813531Sjairo.balart@metempsy.com } 69913531Sjairo.balart@metempsy.com 70013531Sjairo.balart@metempsy.com break; 70113531Sjairo.balart@metempsy.com 70213760Sjairo.balart@metempsy.com // List Registers 70313531Sjairo.balart@metempsy.com case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: 70413531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part) 70513531Sjairo.balart@metempsy.com value = value >> 32; 70613531Sjairo.balart@metempsy.com break; 70713531Sjairo.balart@metempsy.com 70813760Sjairo.balart@metempsy.com // List Registers 70913531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: 71013531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part) 71113531Sjairo.balart@metempsy.com value = value & 0xffffffff; 71213531Sjairo.balart@metempsy.com break; 71313531Sjairo.balart@metempsy.com 71413760Sjairo.balart@metempsy.com // List Registers 71513531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: 71613531Sjairo.balart@metempsy.com break; 71713531Sjairo.balart@metempsy.com 71813760Sjairo.balart@metempsy.com // Virtual Machine Control Register 71913531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR: 72013531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR_EL2: 72113531Sjairo.balart@metempsy.com break; 72213531Sjairo.balart@metempsy.com 72313531Sjairo.balart@metempsy.com default: 72413760Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::readMiscReg(): unknown register %d (%s)", 72513760Sjairo.balart@metempsy.com misc_reg, miscRegName[misc_reg]); 72613531Sjairo.balart@metempsy.com } 72713531Sjairo.balart@metempsy.com 72813760Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::readMiscReg(): register %s value %#x\n", 72913760Sjairo.balart@metempsy.com miscRegName[misc_reg], value); 73013531Sjairo.balart@metempsy.com return value; 73113531Sjairo.balart@metempsy.com} 73213531Sjairo.balart@metempsy.com 73313531Sjairo.balart@metempsy.comvoid 73413580Sgabeblack@google.comGicv3CPUInterface::setMiscReg(int misc_reg, RegVal val) 73513531Sjairo.balart@metempsy.com{ 73613531Sjairo.balart@metempsy.com bool do_virtual_update = false; 73713760Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): register %s value %#x\n", 73813760Sjairo.balart@metempsy.com miscRegName[misc_reg], val); 73913531Sjairo.balart@metempsy.com bool hcr_fmo = getHCREL2FMO(); 74013531Sjairo.balart@metempsy.com bool hcr_imo = getHCREL2IMO(); 74113531Sjairo.balart@metempsy.com 74213531Sjairo.balart@metempsy.com switch (misc_reg) { 74313760Sjairo.balart@metempsy.com // Active Priorities Group 1 Registers 74413531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0: 74513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R0_EL1: 74613531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 74713531Sjairo.balart@metempsy.com return isa->setMiscRegNoEffect(MISCREG_ICV_AP1R0_EL1, val); 74813531Sjairo.balart@metempsy.com } 74913531Sjairo.balart@metempsy.com 75014246Sgiacomo.travaglini@arm.com setBankedMiscReg(MISCREG_ICC_AP1R0_EL1, val); 75114246Sgiacomo.travaglini@arm.com return; 75213531Sjairo.balart@metempsy.com 75313531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1: 75413531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R1_EL1: 75513531Sjairo.balart@metempsy.com 75613531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 75713531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2: 75813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R2_EL1: 75913531Sjairo.balart@metempsy.com 76013531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 76113531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3: 76213531Sjairo.balart@metempsy.com case MISCREG_ICC_AP1R3_EL1: 76313531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 76413531Sjairo.balart@metempsy.com break; 76513531Sjairo.balart@metempsy.com 76613760Sjairo.balart@metempsy.com // Active Priorities Group 0 Registers 76713531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0: 76813531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R0_EL1: 76913531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 77013531Sjairo.balart@metempsy.com return isa->setMiscRegNoEffect(MISCREG_ICV_AP0R0_EL1, val); 77113531Sjairo.balart@metempsy.com } 77213531Sjairo.balart@metempsy.com 77313531Sjairo.balart@metempsy.com break; 77413531Sjairo.balart@metempsy.com 77513531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1: 77613531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R1_EL1: 77713531Sjairo.balart@metempsy.com 77813531Sjairo.balart@metempsy.com // only implemented if supporting 6 or more bits of priority 77913531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2: 78013531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R2_EL1: 78113531Sjairo.balart@metempsy.com 78213531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 78313531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3: 78413531Sjairo.balart@metempsy.com case MISCREG_ICC_AP0R3_EL1: 78513531Sjairo.balart@metempsy.com // only implemented if supporting 7 or more bits of priority 78613531Sjairo.balart@metempsy.com break; 78713531Sjairo.balart@metempsy.com 78813760Sjairo.balart@metempsy.com // End Of Interrupt Register 0 78913531Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR0: 79013531Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR0_EL1: { // End Of Interrupt Register 0 79113531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 79213531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_EOIR0_EL1, val); 79313531Sjairo.balart@metempsy.com } 79413531Sjairo.balart@metempsy.com 79513531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 79613531Sjairo.balart@metempsy.com 79713531Sjairo.balart@metempsy.com // avoid activation for special interrupts 79813923Sgiacomo.travaglini@arm.com if (int_id >= Gicv3::INTID_SECURE && 79913923Sgiacomo.travaglini@arm.com int_id <= Gicv3::INTID_SPURIOUS) { 80013531Sjairo.balart@metempsy.com return; 80113531Sjairo.balart@metempsy.com } 80213531Sjairo.balart@metempsy.com 80313531Sjairo.balart@metempsy.com Gicv3::GroupId group = Gicv3::G0S; 80413531Sjairo.balart@metempsy.com 80513531Sjairo.balart@metempsy.com if (highestActiveGroup() != group) { 80613531Sjairo.balart@metempsy.com return; 80713531Sjairo.balart@metempsy.com } 80813531Sjairo.balart@metempsy.com 80913531Sjairo.balart@metempsy.com dropPriority(group); 81013531Sjairo.balart@metempsy.com 81113531Sjairo.balart@metempsy.com if (!isEOISplitMode()) { 81213531Sjairo.balart@metempsy.com deactivateIRQ(int_id, group); 81313531Sjairo.balart@metempsy.com } 81413531Sjairo.balart@metempsy.com 81513531Sjairo.balart@metempsy.com break; 81613531Sjairo.balart@metempsy.com } 81713531Sjairo.balart@metempsy.com 81813760Sjairo.balart@metempsy.com // Virtual End Of Interrupt Register 0 81913531Sjairo.balart@metempsy.com case MISCREG_ICV_EOIR0_EL1: { 82013531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 82113531Sjairo.balart@metempsy.com 82213531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 82313531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE && 82413531Sjairo.balart@metempsy.com int_id <= Gicv3::INTID_SPURIOUS) { 82513531Sjairo.balart@metempsy.com return; 82613531Sjairo.balart@metempsy.com } 82713531Sjairo.balart@metempsy.com 82813531Sjairo.balart@metempsy.com uint8_t drop_prio = virtualDropPriority(); 82913531Sjairo.balart@metempsy.com 83013531Sjairo.balart@metempsy.com if (drop_prio == 0xff) { 83113531Sjairo.balart@metempsy.com return; 83213531Sjairo.balart@metempsy.com } 83313531Sjairo.balart@metempsy.com 83413531Sjairo.balart@metempsy.com int lr_idx = virtualFindActive(int_id); 83513531Sjairo.balart@metempsy.com 83613531Sjairo.balart@metempsy.com if (lr_idx < 0) { 83713531Sjairo.balart@metempsy.com // No LR found matching 83813531Sjairo.balart@metempsy.com virtualIncrementEOICount(); 83913531Sjairo.balart@metempsy.com } else { 84013760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 84113531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 84213531Sjairo.balart@metempsy.com Gicv3::GroupId lr_group = 84313760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 84413760Sjairo.balart@metempsy.com uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8; 84513531Sjairo.balart@metempsy.com 84613531Sjairo.balart@metempsy.com if (lr_group == Gicv3::G0S && lr_group_prio == drop_prio) { 84713760Sjairo.balart@metempsy.com //if (!virtualIsEOISplitMode()) 84813531Sjairo.balart@metempsy.com { 84913531Sjairo.balart@metempsy.com virtualDeactivateIRQ(lr_idx); 85013531Sjairo.balart@metempsy.com } 85113531Sjairo.balart@metempsy.com } 85213531Sjairo.balart@metempsy.com } 85313531Sjairo.balart@metempsy.com 85413531Sjairo.balart@metempsy.com virtualUpdate(); 85513531Sjairo.balart@metempsy.com break; 85613531Sjairo.balart@metempsy.com } 85713531Sjairo.balart@metempsy.com 85813760Sjairo.balart@metempsy.com // End Of Interrupt Register 1 85913531Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR1: 86013760Sjairo.balart@metempsy.com case MISCREG_ICC_EOIR1_EL1: { 86113531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 86213531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_EOIR1_EL1, val); 86313531Sjairo.balart@metempsy.com } 86413531Sjairo.balart@metempsy.com 86513531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 86613531Sjairo.balart@metempsy.com 86713531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 86813923Sgiacomo.travaglini@arm.com if (int_id >= Gicv3::INTID_SECURE && 86913923Sgiacomo.travaglini@arm.com int_id <= Gicv3::INTID_SPURIOUS) { 87013531Sjairo.balart@metempsy.com return; 87113531Sjairo.balart@metempsy.com } 87213531Sjairo.balart@metempsy.com 87313760Sjairo.balart@metempsy.com Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS; 87413531Sjairo.balart@metempsy.com 87513531Sjairo.balart@metempsy.com if (highestActiveGroup() == Gicv3::G0S) { 87613531Sjairo.balart@metempsy.com return; 87713531Sjairo.balart@metempsy.com } 87813531Sjairo.balart@metempsy.com 87913531Sjairo.balart@metempsy.com if (distributor->DS == 0) { 88013531Sjairo.balart@metempsy.com if (highestActiveGroup() == Gicv3::G1S && !inSecureState()) { 88113531Sjairo.balart@metempsy.com return; 88213531Sjairo.balart@metempsy.com } else if (highestActiveGroup() == Gicv3::G1NS && 88313760Sjairo.balart@metempsy.com !(!inSecureState() or (currEL() == EL3))) { 88413531Sjairo.balart@metempsy.com return; 88513531Sjairo.balart@metempsy.com } 88613531Sjairo.balart@metempsy.com } 88713531Sjairo.balart@metempsy.com 88813531Sjairo.balart@metempsy.com dropPriority(group); 88913531Sjairo.balart@metempsy.com 89013531Sjairo.balart@metempsy.com if (!isEOISplitMode()) { 89113531Sjairo.balart@metempsy.com deactivateIRQ(int_id, group); 89213531Sjairo.balart@metempsy.com } 89313531Sjairo.balart@metempsy.com 89413531Sjairo.balart@metempsy.com break; 89513531Sjairo.balart@metempsy.com } 89613531Sjairo.balart@metempsy.com 89713760Sjairo.balart@metempsy.com // Virtual End Of Interrupt Register 1 89813531Sjairo.balart@metempsy.com case MISCREG_ICV_EOIR1_EL1: { 89913531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 90013531Sjairo.balart@metempsy.com 90113531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 90213531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE && 90313760Sjairo.balart@metempsy.com int_id <= Gicv3::INTID_SPURIOUS) { 90413531Sjairo.balart@metempsy.com return; 90513531Sjairo.balart@metempsy.com } 90613531Sjairo.balart@metempsy.com 90713531Sjairo.balart@metempsy.com uint8_t drop_prio = virtualDropPriority(); 90813531Sjairo.balart@metempsy.com 90913531Sjairo.balart@metempsy.com if (drop_prio == 0xff) { 91013531Sjairo.balart@metempsy.com return; 91113531Sjairo.balart@metempsy.com } 91213531Sjairo.balart@metempsy.com 91313531Sjairo.balart@metempsy.com int lr_idx = virtualFindActive(int_id); 91413531Sjairo.balart@metempsy.com 91513531Sjairo.balart@metempsy.com if (lr_idx < 0) { 91613760Sjairo.balart@metempsy.com // No matching LR found 91713531Sjairo.balart@metempsy.com virtualIncrementEOICount(); 91813531Sjairo.balart@metempsy.com } else { 91913760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 92013531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 92113531Sjairo.balart@metempsy.com Gicv3::GroupId lr_group = 92213760Sjairo.balart@metempsy.com ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 92313760Sjairo.balart@metempsy.com uint8_t lr_group_prio = ich_lr_el2.Priority & 0xf8; 92413531Sjairo.balart@metempsy.com 92513531Sjairo.balart@metempsy.com if (lr_group == Gicv3::G1NS && lr_group_prio == drop_prio) { 92613531Sjairo.balart@metempsy.com if (!virtualIsEOISplitMode()) { 92713531Sjairo.balart@metempsy.com virtualDeactivateIRQ(lr_idx); 92813531Sjairo.balart@metempsy.com } 92913531Sjairo.balart@metempsy.com } 93013531Sjairo.balart@metempsy.com } 93113531Sjairo.balart@metempsy.com 93213531Sjairo.balart@metempsy.com virtualUpdate(); 93313531Sjairo.balart@metempsy.com break; 93413531Sjairo.balart@metempsy.com } 93513531Sjairo.balart@metempsy.com 93613760Sjairo.balart@metempsy.com // Deactivate Interrupt Register 93713531Sjairo.balart@metempsy.com case MISCREG_ICC_DIR: 93813760Sjairo.balart@metempsy.com case MISCREG_ICC_DIR_EL1: { 93913531Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && 94013760Sjairo.balart@metempsy.com (hcr_imo || hcr_fmo)) { 94113531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_DIR_EL1, val); 94213531Sjairo.balart@metempsy.com } 94313531Sjairo.balart@metempsy.com 94413531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 94513531Sjairo.balart@metempsy.com 94613760Sjairo.balart@metempsy.com // The following checks are as per spec pseudocode 94713760Sjairo.balart@metempsy.com // aarch64/support/ICC_DIR_EL1 94813760Sjairo.balart@metempsy.com 94913760Sjairo.balart@metempsy.com // Check for spurious ID 95013531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE) { 95113531Sjairo.balart@metempsy.com return; 95213531Sjairo.balart@metempsy.com } 95313531Sjairo.balart@metempsy.com 95413760Sjairo.balart@metempsy.com // EOI mode is not set, so don't deactivate 95513531Sjairo.balart@metempsy.com if (!isEOISplitMode()) { 95613531Sjairo.balart@metempsy.com return; 95713531Sjairo.balart@metempsy.com } 95813531Sjairo.balart@metempsy.com 95913531Sjairo.balart@metempsy.com Gicv3::GroupId group = 96013531Sjairo.balart@metempsy.com int_id >= 32 ? distributor->getIntGroup(int_id) : 96113531Sjairo.balart@metempsy.com redistributor->getIntGroup(int_id); 96213531Sjairo.balart@metempsy.com bool irq_is_grp0 = group == Gicv3::G0S; 96313531Sjairo.balart@metempsy.com bool single_sec_state = distributor->DS; 96413531Sjairo.balart@metempsy.com bool irq_is_secure = !single_sec_state && (group != Gicv3::G1NS); 96513531Sjairo.balart@metempsy.com SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 96613531Sjairo.balart@metempsy.com bool route_fiq_to_el3 = scr_el3.fiq; 96713531Sjairo.balart@metempsy.com bool route_irq_to_el3 = scr_el3.irq; 96813531Sjairo.balart@metempsy.com bool route_fiq_to_el2 = hcr_fmo; 96913531Sjairo.balart@metempsy.com bool route_irq_to_el2 = hcr_imo; 97013531Sjairo.balart@metempsy.com 97113531Sjairo.balart@metempsy.com switch (currEL()) { 97213531Sjairo.balart@metempsy.com case EL3: 97313531Sjairo.balart@metempsy.com break; 97413531Sjairo.balart@metempsy.com 97513531Sjairo.balart@metempsy.com case EL2: 97613531Sjairo.balart@metempsy.com if (single_sec_state && irq_is_grp0 && !route_fiq_to_el3) { 97713531Sjairo.balart@metempsy.com break; 97813531Sjairo.balart@metempsy.com } 97913531Sjairo.balart@metempsy.com 98013531Sjairo.balart@metempsy.com if (!irq_is_secure && !irq_is_grp0 && !route_irq_to_el3) { 98113531Sjairo.balart@metempsy.com break; 98213531Sjairo.balart@metempsy.com } 98313531Sjairo.balart@metempsy.com 98413531Sjairo.balart@metempsy.com return; 98513531Sjairo.balart@metempsy.com 98613531Sjairo.balart@metempsy.com case EL1: 98713531Sjairo.balart@metempsy.com if (!isSecureBelowEL3()) { 98813531Sjairo.balart@metempsy.com if (single_sec_state && irq_is_grp0 && 98913760Sjairo.balart@metempsy.com !route_fiq_to_el3 && !route_fiq_to_el2) { 99013531Sjairo.balart@metempsy.com break; 99113531Sjairo.balart@metempsy.com } 99213531Sjairo.balart@metempsy.com 99313531Sjairo.balart@metempsy.com if (!irq_is_secure && !irq_is_grp0 && 99413760Sjairo.balart@metempsy.com !route_irq_to_el3 && !route_irq_to_el2) { 99513531Sjairo.balart@metempsy.com break; 99613531Sjairo.balart@metempsy.com } 99713531Sjairo.balart@metempsy.com } else { 99813531Sjairo.balart@metempsy.com if (irq_is_grp0 && !route_fiq_to_el3) { 99913531Sjairo.balart@metempsy.com break; 100013531Sjairo.balart@metempsy.com } 100113531Sjairo.balart@metempsy.com 100213531Sjairo.balart@metempsy.com if (!irq_is_grp0 && 100313760Sjairo.balart@metempsy.com (!irq_is_secure || !single_sec_state) && 100413760Sjairo.balart@metempsy.com !route_irq_to_el3) { 100513531Sjairo.balart@metempsy.com break; 100613531Sjairo.balart@metempsy.com } 100713531Sjairo.balart@metempsy.com } 100813531Sjairo.balart@metempsy.com 100913531Sjairo.balart@metempsy.com return; 101013531Sjairo.balart@metempsy.com 101113531Sjairo.balart@metempsy.com default: 101213531Sjairo.balart@metempsy.com break; 101313531Sjairo.balart@metempsy.com } 101413531Sjairo.balart@metempsy.com 101513531Sjairo.balart@metempsy.com deactivateIRQ(int_id, group); 101613531Sjairo.balart@metempsy.com break; 101713531Sjairo.balart@metempsy.com } 101813531Sjairo.balart@metempsy.com 101913760Sjairo.balart@metempsy.com // Deactivate Virtual Interrupt Register 102013531Sjairo.balart@metempsy.com case MISCREG_ICV_DIR_EL1: { 102113531Sjairo.balart@metempsy.com int int_id = val & 0xffffff; 102213531Sjairo.balart@metempsy.com 102313531Sjairo.balart@metempsy.com // avoid deactivation for special interrupts 102413531Sjairo.balart@metempsy.com if (int_id >= Gicv3::INTID_SECURE && 102513760Sjairo.balart@metempsy.com int_id <= Gicv3::INTID_SPURIOUS) { 102613531Sjairo.balart@metempsy.com return; 102713531Sjairo.balart@metempsy.com } 102813531Sjairo.balart@metempsy.com 102913531Sjairo.balart@metempsy.com if (!virtualIsEOISplitMode()) { 103013531Sjairo.balart@metempsy.com return; 103113531Sjairo.balart@metempsy.com } 103213531Sjairo.balart@metempsy.com 103313531Sjairo.balart@metempsy.com int lr_idx = virtualFindActive(int_id); 103413531Sjairo.balart@metempsy.com 103513531Sjairo.balart@metempsy.com if (lr_idx < 0) { 103613760Sjairo.balart@metempsy.com // No matching LR found 103713531Sjairo.balart@metempsy.com virtualIncrementEOICount(); 103813531Sjairo.balart@metempsy.com } else { 103913531Sjairo.balart@metempsy.com virtualDeactivateIRQ(lr_idx); 104013531Sjairo.balart@metempsy.com } 104113531Sjairo.balart@metempsy.com 104213531Sjairo.balart@metempsy.com virtualUpdate(); 104313531Sjairo.balart@metempsy.com break; 104413531Sjairo.balart@metempsy.com } 104513531Sjairo.balart@metempsy.com 104613760Sjairo.balart@metempsy.com // Binary Point Register 0 104713531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR0: 104814237Sgiacomo.travaglini@arm.com case MISCREG_ICC_BPR0_EL1: { 104914237Sgiacomo.travaglini@arm.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 105014237Sgiacomo.travaglini@arm.com return setMiscReg(MISCREG_ICV_BPR0_EL1, val); 105114237Sgiacomo.travaglini@arm.com } 105214237Sgiacomo.travaglini@arm.com break; 105314237Sgiacomo.travaglini@arm.com } 105413760Sjairo.balart@metempsy.com // Binary Point Register 1 105513531Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1: 105613760Sjairo.balart@metempsy.com case MISCREG_ICC_BPR1_EL1: { 105714237Sgiacomo.travaglini@arm.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 105814237Sgiacomo.travaglini@arm.com return setMiscReg(MISCREG_ICV_BPR1_EL1, val); 105914237Sgiacomo.travaglini@arm.com } 106014237Sgiacomo.travaglini@arm.com 106114237Sgiacomo.travaglini@arm.com val &= 0x7; 106214237Sgiacomo.travaglini@arm.com 106314237Sgiacomo.travaglini@arm.com if (isSecureBelowEL3()) { 106414237Sgiacomo.travaglini@arm.com // group == Gicv3::G1S 106514237Sgiacomo.travaglini@arm.com ICC_CTLR_EL1 icc_ctlr_el1_s = 106614237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 106714237Sgiacomo.travaglini@arm.com 106814237Sgiacomo.travaglini@arm.com val = val > GIC_MIN_BPR ? val : GIC_MIN_BPR; 106914237Sgiacomo.travaglini@arm.com if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_s.CBPR) { 107014237Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICC_BPR0_EL1, val); 107114237Sgiacomo.travaglini@arm.com } else { 107214237Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_S, val); 107314237Sgiacomo.travaglini@arm.com } 107414237Sgiacomo.travaglini@arm.com return; 107514237Sgiacomo.travaglini@arm.com } else { 107614237Sgiacomo.travaglini@arm.com // group == Gicv3::G1NS 107714237Sgiacomo.travaglini@arm.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 107814237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 107914237Sgiacomo.travaglini@arm.com 108014237Sgiacomo.travaglini@arm.com val = val > GIC_MIN_BPR_NS ? val : GIC_MIN_BPR_NS; 108114237Sgiacomo.travaglini@arm.com if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_ns.CBPR) { 108214237Sgiacomo.travaglini@arm.com // Non secure writes from EL1 and EL2 are ignored 108314237Sgiacomo.travaglini@arm.com } else { 108414237Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_NS, val); 108514237Sgiacomo.travaglini@arm.com } 108614237Sgiacomo.travaglini@arm.com return; 108714237Sgiacomo.travaglini@arm.com } 108814237Sgiacomo.travaglini@arm.com 108914237Sgiacomo.travaglini@arm.com break; 109013531Sjairo.balart@metempsy.com } 109113531Sjairo.balart@metempsy.com 109213760Sjairo.balart@metempsy.com // Virtual Binary Point Register 0 109313531Sjairo.balart@metempsy.com case MISCREG_ICV_BPR0_EL1: 109413760Sjairo.balart@metempsy.com // Virtual Binary Point Register 1 109513531Sjairo.balart@metempsy.com case MISCREG_ICV_BPR1_EL1: { 109613531Sjairo.balart@metempsy.com Gicv3::GroupId group = 109713531Sjairo.balart@metempsy.com misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS; 109813760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 109913531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 110013531Sjairo.balart@metempsy.com 110113760Sjairo.balart@metempsy.com if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) { 110213760Sjairo.balart@metempsy.com // BPR0 + 1 saturated to 7, WI 110313531Sjairo.balart@metempsy.com return; 110413531Sjairo.balart@metempsy.com } 110513531Sjairo.balart@metempsy.com 110613531Sjairo.balart@metempsy.com uint8_t min_VPBR = 7 - VIRTUAL_PREEMPTION_BITS; 110713531Sjairo.balart@metempsy.com 110813531Sjairo.balart@metempsy.com if (group != Gicv3::G0S) { 110913531Sjairo.balart@metempsy.com min_VPBR++; 111013531Sjairo.balart@metempsy.com } 111113531Sjairo.balart@metempsy.com 111213531Sjairo.balart@metempsy.com if (val < min_VPBR) { 111313531Sjairo.balart@metempsy.com val = min_VPBR; 111413531Sjairo.balart@metempsy.com } 111513531Sjairo.balart@metempsy.com 111613531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 111713760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR0 = val; 111813531Sjairo.balart@metempsy.com } else { 111913760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR1 = val; 112013531Sjairo.balart@metempsy.com } 112113531Sjairo.balart@metempsy.com 112213531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 112313531Sjairo.balart@metempsy.com do_virtual_update = true; 112413531Sjairo.balart@metempsy.com break; 112513531Sjairo.balart@metempsy.com } 112613531Sjairo.balart@metempsy.com 112713760Sjairo.balart@metempsy.com // Control Register EL1 112813531Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR: 112913760Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL1: { 113013760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 113113531Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_CTLR_EL1, val); 113213531Sjairo.balart@metempsy.com } 113313531Sjairo.balart@metempsy.com 113413531Sjairo.balart@metempsy.com /* 113513760Sjairo.balart@metempsy.com * ExtRange is RO. 113613531Sjairo.balart@metempsy.com * RSS is RO. 113713531Sjairo.balart@metempsy.com * A3V is RO. 113813531Sjairo.balart@metempsy.com * SEIS is RO. 113913531Sjairo.balart@metempsy.com * IDbits is RO. 114013531Sjairo.balart@metempsy.com * PRIbits is RO. 114113531Sjairo.balart@metempsy.com */ 114213760Sjairo.balart@metempsy.com ICC_CTLR_EL1 requested_icc_ctlr_el1 = val; 114313760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1 = 114414245Sgiacomo.travaglini@arm.com readBankedMiscReg(MISCREG_ICC_CTLR_EL1); 114513760Sjairo.balart@metempsy.com 114613760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = 114713760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 114813760Sjairo.balart@metempsy.com 114913760Sjairo.balart@metempsy.com // The following could be refactored but it is following 115013760Sjairo.balart@metempsy.com // spec description section 9.2.6 point by point. 115113760Sjairo.balart@metempsy.com 115213760Sjairo.balart@metempsy.com // PMHE 115313760Sjairo.balart@metempsy.com if (haveEL(EL3)) { 115413760Sjairo.balart@metempsy.com // PMHE is alias of ICC_CTLR_EL3.PMHE 115513760Sjairo.balart@metempsy.com 115613760Sjairo.balart@metempsy.com if (distributor->DS == 0) { 115713760Sjairo.balart@metempsy.com // PMHE is RO 115813760Sjairo.balart@metempsy.com } else if (distributor->DS == 1) { 115913760Sjairo.balart@metempsy.com // PMHE is RW 116013760Sjairo.balart@metempsy.com icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE; 116113760Sjairo.balart@metempsy.com icc_ctlr_el3.PMHE = icc_ctlr_el1.PMHE; 116213760Sjairo.balart@metempsy.com } 116313531Sjairo.balart@metempsy.com } else { 116413760Sjairo.balart@metempsy.com // PMHE is RW (by implementation choice) 116513760Sjairo.balart@metempsy.com icc_ctlr_el1.PMHE = requested_icc_ctlr_el1.PMHE; 116613531Sjairo.balart@metempsy.com } 116713531Sjairo.balart@metempsy.com 116813760Sjairo.balart@metempsy.com // EOImode 116913760Sjairo.balart@metempsy.com icc_ctlr_el1.EOImode = requested_icc_ctlr_el1.EOImode; 117013760Sjairo.balart@metempsy.com 117113760Sjairo.balart@metempsy.com if (inSecureState()) { 117213760Sjairo.balart@metempsy.com // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1S 117313760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1S = icc_ctlr_el1.EOImode; 117413760Sjairo.balart@metempsy.com } else { 117513760Sjairo.balart@metempsy.com // EOIMode is alias of ICC_CTLR_EL3.EOImode_EL1NS 117613760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1NS = icc_ctlr_el1.EOImode; 117713760Sjairo.balart@metempsy.com } 117813760Sjairo.balart@metempsy.com 117913760Sjairo.balart@metempsy.com // CBPR 118013760Sjairo.balart@metempsy.com if (haveEL(EL3)) { 118113760Sjairo.balart@metempsy.com // CBPR is alias of ICC_CTLR_EL3.CBPR_EL1{S,NS} 118213760Sjairo.balart@metempsy.com 118313760Sjairo.balart@metempsy.com if (distributor->DS == 0) { 118413760Sjairo.balart@metempsy.com // CBPR is RO 118513760Sjairo.balart@metempsy.com } else { 118613760Sjairo.balart@metempsy.com // CBPR is RW 118713760Sjairo.balart@metempsy.com icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR; 118813760Sjairo.balart@metempsy.com 118913760Sjairo.balart@metempsy.com if (inSecureState()) { 119013760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1S = icc_ctlr_el1.CBPR; 119113760Sjairo.balart@metempsy.com } else { 119213760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1NS = icc_ctlr_el1.CBPR; 119313760Sjairo.balart@metempsy.com } 119413760Sjairo.balart@metempsy.com } 119513760Sjairo.balart@metempsy.com } else { 119613760Sjairo.balart@metempsy.com // CBPR is RW 119713760Sjairo.balart@metempsy.com icc_ctlr_el1.CBPR = requested_icc_ctlr_el1.CBPR; 119813760Sjairo.balart@metempsy.com } 119913760Sjairo.balart@metempsy.com 120013760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL3, icc_ctlr_el3); 120113760Sjairo.balart@metempsy.com 120214245Sgiacomo.travaglini@arm.com setBankedMiscReg(MISCREG_ICC_CTLR_EL1, icc_ctlr_el1); 120314245Sgiacomo.travaglini@arm.com return; 120413531Sjairo.balart@metempsy.com } 120513531Sjairo.balart@metempsy.com 120613760Sjairo.balart@metempsy.com // Virtual Control Register 120713531Sjairo.balart@metempsy.com case MISCREG_ICV_CTLR_EL1: { 120813760Sjairo.balart@metempsy.com ICV_CTLR_EL1 requested_icv_ctlr_el1 = val; 120913760Sjairo.balart@metempsy.com ICV_CTLR_EL1 icv_ctlr_el1 = 121013760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICV_CTLR_EL1); 121113760Sjairo.balart@metempsy.com icv_ctlr_el1.EOImode = requested_icv_ctlr_el1.EOImode; 121213760Sjairo.balart@metempsy.com icv_ctlr_el1.CBPR = requested_icv_ctlr_el1.CBPR; 121313760Sjairo.balart@metempsy.com val = icv_ctlr_el1; 121413760Sjairo.balart@metempsy.com 121513760Sjairo.balart@metempsy.com // Aliases 121613760Sjairo.balart@metempsy.com // ICV_CTLR_EL1.CBPR aliases ICH_VMCR_EL2.VCBPR. 121713760Sjairo.balart@metempsy.com // ICV_CTLR_EL1.EOImode aliases ICH_VMCR_EL2.VEOIM. 121813760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 121913760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 122013760Sjairo.balart@metempsy.com ich_vmcr_el2.VCBPR = icv_ctlr_el1.CBPR; 122113760Sjairo.balart@metempsy.com ich_vmcr_el2.VEOIM = icv_ctlr_el1.EOImode; 122213760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 122313760Sjairo.balart@metempsy.com break; 122413760Sjairo.balart@metempsy.com } 122513760Sjairo.balart@metempsy.com 122613760Sjairo.balart@metempsy.com // Control Register EL3 122713760Sjairo.balart@metempsy.com case MISCREG_ICC_MCTLR: 122813760Sjairo.balart@metempsy.com case MISCREG_ICC_CTLR_EL3: { 122913760Sjairo.balart@metempsy.com /* 123013760Sjairo.balart@metempsy.com * ExtRange is RO. 123113760Sjairo.balart@metempsy.com * RSS is RO. 123213760Sjairo.balart@metempsy.com * nDS is RO. 123313760Sjairo.balart@metempsy.com * A3V is RO. 123413760Sjairo.balart@metempsy.com * SEIS is RO. 123513760Sjairo.balart@metempsy.com * IDbits is RO. 123613760Sjairo.balart@metempsy.com * PRIbits is RO. 123713760Sjairo.balart@metempsy.com * PMHE is RAO/WI, priority-based routing is always used. 123813760Sjairo.balart@metempsy.com */ 123913760Sjairo.balart@metempsy.com ICC_CTLR_EL3 requested_icc_ctlr_el3 = val; 124013760Sjairo.balart@metempsy.com 124113760Sjairo.balart@metempsy.com // Aliases 124213760Sjairo.balart@metempsy.com if (haveEL(EL3)) 124313760Sjairo.balart@metempsy.com { 124413760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_s = 124513760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 124613760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 124713760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 124813760Sjairo.balart@metempsy.com 124913760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(NS).EOImode is an alias of 125013760Sjairo.balart@metempsy.com // ICC_CTLR_EL3.EOImode_EL1NS 125113760Sjairo.balart@metempsy.com icc_ctlr_el1_ns.EOImode = requested_icc_ctlr_el3.EOImode_EL1NS; 125213760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(S).EOImode is an alias of 125313760Sjairo.balart@metempsy.com // ICC_CTLR_EL3.EOImode_EL1S 125413760Sjairo.balart@metempsy.com icc_ctlr_el1_s.EOImode = requested_icc_ctlr_el3.EOImode_EL1S; 125513760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(NS).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1NS 125613760Sjairo.balart@metempsy.com icc_ctlr_el1_ns.CBPR = requested_icc_ctlr_el3.CBPR_EL1NS; 125713760Sjairo.balart@metempsy.com // ICC_CTLR_EL1(S).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1S 125813760Sjairo.balart@metempsy.com icc_ctlr_el1_s.CBPR = requested_icc_ctlr_el3.CBPR_EL1S; 125913760Sjairo.balart@metempsy.com 126013760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S, icc_ctlr_el1_s); 126113760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS, 126213760Sjairo.balart@metempsy.com icc_ctlr_el1_ns); 126313760Sjairo.balart@metempsy.com } 126413760Sjairo.balart@metempsy.com 126513760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = 126613760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 126713760Sjairo.balart@metempsy.com 126813760Sjairo.balart@metempsy.com icc_ctlr_el3.RM = requested_icc_ctlr_el3.RM; 126913760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1NS = requested_icc_ctlr_el3.EOImode_EL1NS; 127013760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL1S = requested_icc_ctlr_el3.EOImode_EL1S; 127113760Sjairo.balart@metempsy.com icc_ctlr_el3.EOImode_EL3 = requested_icc_ctlr_el3.EOImode_EL3; 127213760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1NS = requested_icc_ctlr_el3.CBPR_EL1NS; 127313760Sjairo.balart@metempsy.com icc_ctlr_el3.CBPR_EL1S = requested_icc_ctlr_el3.CBPR_EL1S; 127413760Sjairo.balart@metempsy.com 127513760Sjairo.balart@metempsy.com val = icc_ctlr_el3; 127613531Sjairo.balart@metempsy.com break; 127713531Sjairo.balart@metempsy.com } 127813531Sjairo.balart@metempsy.com 127913760Sjairo.balart@metempsy.com // Priority Mask Register 128013531Sjairo.balart@metempsy.com case MISCREG_ICC_PMR: 128113760Sjairo.balart@metempsy.com case MISCREG_ICC_PMR_EL1: { 128213760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) { 128314057Sgiacomo.travaglini@arm.com return setMiscReg(MISCREG_ICV_PMR_EL1, val); 128413531Sjairo.balart@metempsy.com } 128513531Sjairo.balart@metempsy.com 128613531Sjairo.balart@metempsy.com val &= 0xff; 128713531Sjairo.balart@metempsy.com SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 128813531Sjairo.balart@metempsy.com 128913531Sjairo.balart@metempsy.com if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) { 129013760Sjairo.balart@metempsy.com // Spec section 4.8.1 129113760Sjairo.balart@metempsy.com // For Non-secure access to ICC_PMR_EL1 SCR_EL3.FIQ == 1: 129213580Sgabeblack@google.com RegVal old_icc_pmr_el1 = 129313531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1); 129413531Sjairo.balart@metempsy.com 129513531Sjairo.balart@metempsy.com if (!(old_icc_pmr_el1 & 0x80)) { 129613760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 129713760Sjairo.balart@metempsy.com // 0x00-0x7F then WI 129813531Sjairo.balart@metempsy.com return; 129913531Sjairo.balart@metempsy.com } 130013531Sjairo.balart@metempsy.com 130113760Sjairo.balart@metempsy.com // If the current priority mask value is in the range of 130213760Sjairo.balart@metempsy.com // 0x80-0xFF then a write access to ICC_PMR_EL1 succeeds, 130313760Sjairo.balart@metempsy.com // based on the Non-secure read of the priority mask value 130413760Sjairo.balart@metempsy.com // written to the register. 130513760Sjairo.balart@metempsy.com 130613531Sjairo.balart@metempsy.com val = (val >> 1) | 0x80; 130713531Sjairo.balart@metempsy.com } 130813531Sjairo.balart@metempsy.com 130913531Sjairo.balart@metempsy.com val &= ~0U << (8 - PRIORITY_BITS); 131013531Sjairo.balart@metempsy.com break; 131113531Sjairo.balart@metempsy.com } 131213531Sjairo.balart@metempsy.com 131314057Sgiacomo.travaglini@arm.com case MISCREG_ICV_PMR_EL1: { // Priority Mask Register 131414057Sgiacomo.travaglini@arm.com ICH_VMCR_EL2 ich_vmcr_el2 = 131514057Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 131614057Sgiacomo.travaglini@arm.com ich_vmcr_el2.VPMR = val & 0xff; 131714057Sgiacomo.travaglini@arm.com 131814057Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 131914057Sgiacomo.travaglini@arm.com virtualUpdate(); 132014057Sgiacomo.travaglini@arm.com return; 132114057Sgiacomo.travaglini@arm.com } 132214057Sgiacomo.travaglini@arm.com 132313760Sjairo.balart@metempsy.com // Interrupt Group 0 Enable Register EL1 132413760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0: 132513760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN0_EL1: { 132613760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_fmo) { 132713760Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val); 132813760Sjairo.balart@metempsy.com } 132913760Sjairo.balart@metempsy.com 133014248Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1, val); 133114248Sgiacomo.travaglini@arm.com updateDistributor(); 133214248Sgiacomo.travaglini@arm.com return; 133313760Sjairo.balart@metempsy.com } 133413760Sjairo.balart@metempsy.com 133513760Sjairo.balart@metempsy.com // Virtual Interrupt Group 0 Enable register 133613760Sjairo.balart@metempsy.com case MISCREG_ICV_IGRPEN0_EL1: { 133713760Sjairo.balart@metempsy.com bool enable = val & 0x1; 133813760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 133913760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 134013760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG0 = enable; 134113740Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 134213740Sgiacomo.travaglini@arm.com virtualUpdate(); 134313740Sgiacomo.travaglini@arm.com return; 134413740Sgiacomo.travaglini@arm.com } 134513740Sgiacomo.travaglini@arm.com 134613760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register EL1 134713760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1: 134813760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1_EL1: { 134913760Sjairo.balart@metempsy.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 135013760Sjairo.balart@metempsy.com return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val); 135113760Sjairo.balart@metempsy.com } 135213760Sjairo.balart@metempsy.com 135314247Sgiacomo.travaglini@arm.com setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val); 135414248Sgiacomo.travaglini@arm.com updateDistributor(); 135514247Sgiacomo.travaglini@arm.com return; 135613531Sjairo.balart@metempsy.com } 135713531Sjairo.balart@metempsy.com 135813760Sjairo.balart@metempsy.com // Virtual Interrupt Group 1 Enable register 135913760Sjairo.balart@metempsy.com case MISCREG_ICV_IGRPEN1_EL1: { 136013531Sjairo.balart@metempsy.com bool enable = val & 0x1; 136113760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 136213531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 136313760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG1 = enable; 136413531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2); 136513531Sjairo.balart@metempsy.com virtualUpdate(); 136613531Sjairo.balart@metempsy.com return; 136713531Sjairo.balart@metempsy.com } 136813531Sjairo.balart@metempsy.com 136913760Sjairo.balart@metempsy.com // Interrupt Group 1 Enable register 137013760Sjairo.balart@metempsy.com case MISCREG_ICC_MGRPEN1: 137113760Sjairo.balart@metempsy.com case MISCREG_ICC_IGRPEN1_EL3: { 137213760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL3 icc_igrpen1_el3 = val; 137314254Sgiacomo.travaglini@arm.com 137414254Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect( 137514254Sgiacomo.travaglini@arm.com MISCREG_ICC_IGRPEN1_EL1_S, icc_igrpen1_el3.EnableGrp1S); 137614254Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect( 137714254Sgiacomo.travaglini@arm.com MISCREG_ICC_IGRPEN1_EL1_NS, icc_igrpen1_el3.EnableGrp1NS); 137814256Sgiacomo.travaglini@arm.com updateDistributor(); 137914254Sgiacomo.travaglini@arm.com return; 138013531Sjairo.balart@metempsy.com } 138113531Sjairo.balart@metempsy.com 138213760Sjairo.balart@metempsy.com // Software Generated Interrupt Group 0 Register 138313531Sjairo.balart@metempsy.com case MISCREG_ICC_SGI0R: 138413531Sjairo.balart@metempsy.com case MISCREG_ICC_SGI0R_EL1: 138514227Sgiacomo.travaglini@arm.com generateSGI(val, Gicv3::G0S); 138614227Sgiacomo.travaglini@arm.com break; 138713531Sjairo.balart@metempsy.com 138813760Sjairo.balart@metempsy.com // Software Generated Interrupt Group 1 Register 138913531Sjairo.balart@metempsy.com case MISCREG_ICC_SGI1R: 139014227Sgiacomo.travaglini@arm.com case MISCREG_ICC_SGI1R_EL1: { 139114227Sgiacomo.travaglini@arm.com Gicv3::GroupId group = inSecureState() ? Gicv3::G1S : Gicv3::G1NS; 139214227Sgiacomo.travaglini@arm.com 139314227Sgiacomo.travaglini@arm.com generateSGI(val, group); 139414227Sgiacomo.travaglini@arm.com break; 139514227Sgiacomo.travaglini@arm.com } 139613531Sjairo.balart@metempsy.com 139713760Sjairo.balart@metempsy.com // Alias Software Generated Interrupt Group 1 Register 139813531Sjairo.balart@metempsy.com case MISCREG_ICC_ASGI1R: 139913531Sjairo.balart@metempsy.com case MISCREG_ICC_ASGI1R_EL1: { 140014227Sgiacomo.travaglini@arm.com Gicv3::GroupId group = inSecureState() ? Gicv3::G1NS : Gicv3::G1S; 140114227Sgiacomo.travaglini@arm.com 140214227Sgiacomo.travaglini@arm.com generateSGI(val, group); 140314227Sgiacomo.travaglini@arm.com break; 140413531Sjairo.balart@metempsy.com } 140513531Sjairo.balart@metempsy.com 140613760Sjairo.balart@metempsy.com // System Register Enable Register EL1 140713531Sjairo.balart@metempsy.com case MISCREG_ICC_SRE: 140813760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL1: 140913760Sjairo.balart@metempsy.com // System Register Enable Register EL2 141013531Sjairo.balart@metempsy.com case MISCREG_ICC_HSRE: 141113760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL2: 141213760Sjairo.balart@metempsy.com // System Register Enable Register EL3 141313531Sjairo.balart@metempsy.com case MISCREG_ICC_MSRE: 141413760Sjairo.balart@metempsy.com case MISCREG_ICC_SRE_EL3: 141513760Sjairo.balart@metempsy.com // All bits are RAO/WI 141613760Sjairo.balart@metempsy.com return; 141713760Sjairo.balart@metempsy.com 141813760Sjairo.balart@metempsy.com // Hyp Control Register 141913760Sjairo.balart@metempsy.com case MISCREG_ICH_HCR: 142013760Sjairo.balart@metempsy.com case MISCREG_ICH_HCR_EL2: { 142113760Sjairo.balart@metempsy.com ICH_HCR_EL2 requested_ich_hcr_el2 = val; 142213760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = 142313760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 142413760Sjairo.balart@metempsy.com 142513760Sjairo.balart@metempsy.com if (requested_ich_hcr_el2.EOIcount >= ich_hcr_el2.EOIcount) 142613760Sjairo.balart@metempsy.com { 142713760Sjairo.balart@metempsy.com // EOIcount - Permitted behaviors are: 142813760Sjairo.balart@metempsy.com // - Increment EOIcount. 142913760Sjairo.balart@metempsy.com // - Leave EOIcount unchanged. 143013760Sjairo.balart@metempsy.com ich_hcr_el2.EOIcount = requested_ich_hcr_el2.EOIcount; 143113531Sjairo.balart@metempsy.com } 143213531Sjairo.balart@metempsy.com 143313760Sjairo.balart@metempsy.com ich_hcr_el2.TDIR = requested_ich_hcr_el2.TDIR; 143413760Sjairo.balart@metempsy.com ich_hcr_el2.TSEI = requested_ich_hcr_el2.TSEI; 143513760Sjairo.balart@metempsy.com ich_hcr_el2.TALL1 = requested_ich_hcr_el2.TALL1;; 143613760Sjairo.balart@metempsy.com ich_hcr_el2.TALL0 = requested_ich_hcr_el2.TALL0;; 143713760Sjairo.balart@metempsy.com ich_hcr_el2.TC = requested_ich_hcr_el2.TC; 143813760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp1DIE = requested_ich_hcr_el2.VGrp1DIE; 143913760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp1EIE = requested_ich_hcr_el2.VGrp1EIE; 144013760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp0DIE = requested_ich_hcr_el2.VGrp0DIE; 144113760Sjairo.balart@metempsy.com ich_hcr_el2.VGrp0EIE = requested_ich_hcr_el2.VGrp0EIE; 144213760Sjairo.balart@metempsy.com ich_hcr_el2.NPIE = requested_ich_hcr_el2.NPIE; 144313760Sjairo.balart@metempsy.com ich_hcr_el2.LRENPIE = requested_ich_hcr_el2.LRENPIE; 144413760Sjairo.balart@metempsy.com ich_hcr_el2.UIE = requested_ich_hcr_el2.UIE; 144513760Sjairo.balart@metempsy.com ich_hcr_el2.En = requested_ich_hcr_el2.En; 144613760Sjairo.balart@metempsy.com val = ich_hcr_el2; 144713531Sjairo.balart@metempsy.com do_virtual_update = true; 144813531Sjairo.balart@metempsy.com break; 144913760Sjairo.balart@metempsy.com } 145013760Sjairo.balart@metempsy.com 145113760Sjairo.balart@metempsy.com // List Registers 145213760Sjairo.balart@metempsy.com case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15: { 145313531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part) 145413760Sjairo.balart@metempsy.com ICH_LRC requested_ich_lrc = val; 145513760Sjairo.balart@metempsy.com ICH_LRC ich_lrc = isa->readMiscRegNoEffect(misc_reg); 145613760Sjairo.balart@metempsy.com 145713760Sjairo.balart@metempsy.com ich_lrc.State = requested_ich_lrc.State; 145813760Sjairo.balart@metempsy.com ich_lrc.HW = requested_ich_lrc.HW; 145913760Sjairo.balart@metempsy.com ich_lrc.Group = requested_ich_lrc.Group; 146013760Sjairo.balart@metempsy.com 146113760Sjairo.balart@metempsy.com // Priority, bits [23:16] 146213760Sjairo.balart@metempsy.com // At least five bits must be implemented. 146313760Sjairo.balart@metempsy.com // Unimplemented bits are RES0 and start from bit[16] up to bit[18]. 146413760Sjairo.balart@metempsy.com // We implement 5 bits. 146513760Sjairo.balart@metempsy.com ich_lrc.Priority = (requested_ich_lrc.Priority & 0xf8) | 146613760Sjairo.balart@metempsy.com (ich_lrc.Priority & 0x07); 146713760Sjairo.balart@metempsy.com 146813760Sjairo.balart@metempsy.com // pINTID, bits [12:0] 146913760Sjairo.balart@metempsy.com // When ICH_LR<n>.HW is 0 this field has the following meaning: 147013760Sjairo.balart@metempsy.com // - Bits[12:10] : RES0. 147113760Sjairo.balart@metempsy.com // - Bit[9] : EOI. 147213760Sjairo.balart@metempsy.com // - Bits[8:0] : RES0. 147313760Sjairo.balart@metempsy.com // When ICH_LR<n>.HW is 1: 147413760Sjairo.balart@metempsy.com // - This field is only required to implement enough bits to hold a 147513760Sjairo.balart@metempsy.com // valid value for the implemented INTID size. Any unused higher 147613760Sjairo.balart@metempsy.com // order bits are RES0. 147713760Sjairo.balart@metempsy.com if (requested_ich_lrc.HW == 0) { 147813760Sjairo.balart@metempsy.com ich_lrc.EOI = requested_ich_lrc.EOI; 147913760Sjairo.balart@metempsy.com } else { 148013760Sjairo.balart@metempsy.com ich_lrc.pINTID = requested_ich_lrc.pINTID; 148113531Sjairo.balart@metempsy.com } 148213531Sjairo.balart@metempsy.com 148313760Sjairo.balart@metempsy.com val = ich_lrc; 148413760Sjairo.balart@metempsy.com do_virtual_update = true; 148513760Sjairo.balart@metempsy.com break; 148613760Sjairo.balart@metempsy.com } 148713760Sjairo.balart@metempsy.com 148813760Sjairo.balart@metempsy.com // List Registers 148913531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: { 149013531Sjairo.balart@metempsy.com // AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part) 149113580Sgabeblack@google.com RegVal old_val = isa->readMiscRegNoEffect(misc_reg); 149213531Sjairo.balart@metempsy.com val = (old_val & 0xffffffff00000000) | (val & 0xffffffff); 149313531Sjairo.balart@metempsy.com do_virtual_update = true; 149413531Sjairo.balart@metempsy.com break; 149513531Sjairo.balart@metempsy.com } 149613531Sjairo.balart@metempsy.com 149713760Sjairo.balart@metempsy.com // List Registers 149813531Sjairo.balart@metempsy.com case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: { // AArch64 149913760Sjairo.balart@metempsy.com ICH_LR_EL2 requested_ich_lr_el2 = val; 150013760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(misc_reg); 150113760Sjairo.balart@metempsy.com 150213760Sjairo.balart@metempsy.com ich_lr_el2.State = requested_ich_lr_el2.State; 150313760Sjairo.balart@metempsy.com ich_lr_el2.HW = requested_ich_lr_el2.HW; 150413760Sjairo.balart@metempsy.com ich_lr_el2.Group = requested_ich_lr_el2.Group; 150513760Sjairo.balart@metempsy.com 150613760Sjairo.balart@metempsy.com // Priority, bits [55:48] 150713760Sjairo.balart@metempsy.com // At least five bits must be implemented. 150813760Sjairo.balart@metempsy.com // Unimplemented bits are RES0 and start from bit[48] up to bit[50]. 150913760Sjairo.balart@metempsy.com // We implement 5 bits. 151013760Sjairo.balart@metempsy.com ich_lr_el2.Priority = (requested_ich_lr_el2.Priority & 0xf8) | 151113760Sjairo.balart@metempsy.com (ich_lr_el2.Priority & 0x07); 151213760Sjairo.balart@metempsy.com 151313760Sjairo.balart@metempsy.com // pINTID, bits [44:32] 151413760Sjairo.balart@metempsy.com // When ICH_LR<n>_EL2.HW is 0 this field has the following meaning: 151513760Sjairo.balart@metempsy.com // - Bits[44:42] : RES0. 151613760Sjairo.balart@metempsy.com // - Bit[41] : EOI. 151713760Sjairo.balart@metempsy.com // - Bits[40:32] : RES0. 151813760Sjairo.balart@metempsy.com // When ICH_LR<n>_EL2.HW is 1: 151913760Sjairo.balart@metempsy.com // - This field is only required to implement enough bits to hold a 152013760Sjairo.balart@metempsy.com // valid value for the implemented INTID size. Any unused higher 152113760Sjairo.balart@metempsy.com // order bits are RES0. 152213760Sjairo.balart@metempsy.com if (requested_ich_lr_el2.HW == 0) { 152313760Sjairo.balart@metempsy.com ich_lr_el2.EOI = requested_ich_lr_el2.EOI; 152413760Sjairo.balart@metempsy.com } else { 152513760Sjairo.balart@metempsy.com ich_lr_el2.pINTID = requested_ich_lr_el2.pINTID; 152613760Sjairo.balart@metempsy.com } 152713760Sjairo.balart@metempsy.com 152813760Sjairo.balart@metempsy.com // vINTID, bits [31:0] 152913760Sjairo.balart@metempsy.com // It is IMPLEMENTATION DEFINED how many bits are implemented, 153013760Sjairo.balart@metempsy.com // though at least 16 bits must be implemented. 153113760Sjairo.balart@metempsy.com // Unimplemented bits are RES0. 153213760Sjairo.balart@metempsy.com ich_lr_el2.vINTID = requested_ich_lr_el2.vINTID; 153313760Sjairo.balart@metempsy.com 153413760Sjairo.balart@metempsy.com val = ich_lr_el2; 153513531Sjairo.balart@metempsy.com do_virtual_update = true; 153613531Sjairo.balart@metempsy.com break; 153713531Sjairo.balart@metempsy.com } 153813531Sjairo.balart@metempsy.com 153913760Sjairo.balart@metempsy.com // Virtual Machine Control Register 154013531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR: 154113531Sjairo.balart@metempsy.com case MISCREG_ICH_VMCR_EL2: { 154213760Sjairo.balart@metempsy.com ICH_VMCR_EL2 requested_ich_vmcr_el2 = val; 154313760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 154413760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 154513760Sjairo.balart@metempsy.com ich_vmcr_el2.VPMR = requested_ich_vmcr_el2.VPMR; 154613531Sjairo.balart@metempsy.com uint8_t min_vpr0 = 7 - VIRTUAL_PREEMPTION_BITS; 154713760Sjairo.balart@metempsy.com 154813760Sjairo.balart@metempsy.com if (requested_ich_vmcr_el2.VBPR0 < min_vpr0) { 154913760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR0 = min_vpr0; 155013760Sjairo.balart@metempsy.com } else { 155113760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR0 = requested_ich_vmcr_el2.VBPR0; 155213760Sjairo.balart@metempsy.com } 155313760Sjairo.balart@metempsy.com 155413531Sjairo.balart@metempsy.com uint8_t min_vpr1 = min_vpr0 + 1; 155513760Sjairo.balart@metempsy.com 155613760Sjairo.balart@metempsy.com if (requested_ich_vmcr_el2.VBPR1 < min_vpr1) { 155713760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR1 = min_vpr1; 155813760Sjairo.balart@metempsy.com } else { 155913760Sjairo.balart@metempsy.com ich_vmcr_el2.VBPR1 = requested_ich_vmcr_el2.VBPR1; 156013760Sjairo.balart@metempsy.com } 156113760Sjairo.balart@metempsy.com 156213760Sjairo.balart@metempsy.com ich_vmcr_el2.VEOIM = requested_ich_vmcr_el2.VEOIM; 156313760Sjairo.balart@metempsy.com ich_vmcr_el2.VCBPR = requested_ich_vmcr_el2.VCBPR; 156413760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG1 = requested_ich_vmcr_el2.VENG1; 156513760Sjairo.balart@metempsy.com ich_vmcr_el2.VENG0 = requested_ich_vmcr_el2.VENG0; 156613760Sjairo.balart@metempsy.com val = ich_vmcr_el2; 156713531Sjairo.balart@metempsy.com break; 156813531Sjairo.balart@metempsy.com } 156913531Sjairo.balart@metempsy.com 157013760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 0 Registers 157114236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R0: 157214236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R0_EL2: 157314236Sgiacomo.travaglini@arm.com break; 157414236Sgiacomo.travaglini@arm.com 157514236Sgiacomo.travaglini@arm.com // only implemented if supporting 6 or more bits of priority 157614236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R1: 157714236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R1_EL2: 157814236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 157914236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R2: 158014236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R2_EL2: 158114236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 158214236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R3: 158314236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP0R3_EL2: 158414236Sgiacomo.travaglini@arm.com // Unimplemented registers are RAZ/WI 158514236Sgiacomo.travaglini@arm.com return; 158614236Sgiacomo.travaglini@arm.com 158713760Sjairo.balart@metempsy.com // Hyp Active Priorities Group 1 Registers 158814236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R0: 158914236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R0_EL2: 159013531Sjairo.balart@metempsy.com break; 159113531Sjairo.balart@metempsy.com 159214236Sgiacomo.travaglini@arm.com // only implemented if supporting 6 or more bits of priority 159314236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R1: 159414236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R1_EL2: 159514236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 159614236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R2: 159714236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R2_EL2: 159814236Sgiacomo.travaglini@arm.com // only implemented if supporting 7 or more bits of priority 159914236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R3: 160014236Sgiacomo.travaglini@arm.com case MISCREG_ICH_AP1R3_EL2: 160114236Sgiacomo.travaglini@arm.com // Unimplemented registers are RAZ/WI 160214236Sgiacomo.travaglini@arm.com return; 160314236Sgiacomo.travaglini@arm.com 160413531Sjairo.balart@metempsy.com default: 160513760Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::setMiscReg(): unknown register %d (%s)", 160613760Sjairo.balart@metempsy.com misc_reg, miscRegName[misc_reg]); 160713531Sjairo.balart@metempsy.com } 160813531Sjairo.balart@metempsy.com 160913531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(misc_reg, val); 161013531Sjairo.balart@metempsy.com 161113531Sjairo.balart@metempsy.com if (do_virtual_update) { 161213531Sjairo.balart@metempsy.com virtualUpdate(); 161313531Sjairo.balart@metempsy.com } 161413531Sjairo.balart@metempsy.com} 161513531Sjairo.balart@metempsy.com 161614243Sgiacomo.travaglini@arm.comRegVal 161714243Sgiacomo.travaglini@arm.comGicv3CPUInterface::readBankedMiscReg(MiscRegIndex misc_reg) const 161814243Sgiacomo.travaglini@arm.com{ 161914243Sgiacomo.travaglini@arm.com return isa->readMiscRegNoEffect( 162014243Sgiacomo.travaglini@arm.com isa->snsBankedIndex64(misc_reg, !isSecureBelowEL3())); 162114243Sgiacomo.travaglini@arm.com} 162214243Sgiacomo.travaglini@arm.com 162314243Sgiacomo.travaglini@arm.comvoid 162414243Sgiacomo.travaglini@arm.comGicv3CPUInterface::setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const 162514243Sgiacomo.travaglini@arm.com{ 162614243Sgiacomo.travaglini@arm.com isa->setMiscRegNoEffect( 162714243Sgiacomo.travaglini@arm.com isa->snsBankedIndex64(misc_reg, !isSecureBelowEL3()), val); 162814243Sgiacomo.travaglini@arm.com} 162914243Sgiacomo.travaglini@arm.com 163013531Sjairo.balart@metempsy.comint 163113760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualFindActive(uint32_t int_id) const 163213531Sjairo.balart@metempsy.com{ 163313531Sjairo.balart@metempsy.com for (uint32_t lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 163413760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 163513531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 163613760Sjairo.balart@metempsy.com 163713760Sjairo.balart@metempsy.com if (((ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE) || 163813760Sjairo.balart@metempsy.com (ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE_PENDING)) && 163913760Sjairo.balart@metempsy.com (ich_lr_el2.vINTID == int_id)) { 164013531Sjairo.balart@metempsy.com return lr_idx; 164113531Sjairo.balart@metempsy.com } 164213531Sjairo.balart@metempsy.com } 164313531Sjairo.balart@metempsy.com 164413531Sjairo.balart@metempsy.com return -1; 164513531Sjairo.balart@metempsy.com} 164613531Sjairo.balart@metempsy.com 164713531Sjairo.balart@metempsy.comuint32_t 164813760Sjairo.balart@metempsy.comGicv3CPUInterface::getHPPIR0() const 164913531Sjairo.balart@metempsy.com{ 165014233Sgiacomo.travaglini@arm.com if (hppi.prio == 0xff || !groupEnabled(hppi.group)) { 165113531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 165213531Sjairo.balart@metempsy.com } 165313531Sjairo.balart@metempsy.com 165413531Sjairo.balart@metempsy.com bool irq_is_secure = !distributor->DS && hppi.group != Gicv3::G1NS; 165513531Sjairo.balart@metempsy.com 165613531Sjairo.balart@metempsy.com if ((hppi.group != Gicv3::G0S) && isEL3OrMon()) { 165713760Sjairo.balart@metempsy.com // interrupt for the other state pending 165813531Sjairo.balart@metempsy.com return irq_is_secure ? Gicv3::INTID_SECURE : Gicv3::INTID_NONSECURE; 165913531Sjairo.balart@metempsy.com } 166013531Sjairo.balart@metempsy.com 166113531Sjairo.balart@metempsy.com if ((hppi.group != Gicv3::G0S)) { // && !isEL3OrMon()) 166213531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 166313531Sjairo.balart@metempsy.com } 166413531Sjairo.balart@metempsy.com 166513531Sjairo.balart@metempsy.com if (irq_is_secure && !inSecureState()) { 166613531Sjairo.balart@metempsy.com // Secure interrupts not visible in Non-secure 166713531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 166813531Sjairo.balart@metempsy.com } 166913531Sjairo.balart@metempsy.com 167013531Sjairo.balart@metempsy.com return hppi.intid; 167113531Sjairo.balart@metempsy.com} 167213531Sjairo.balart@metempsy.com 167313531Sjairo.balart@metempsy.comuint32_t 167413760Sjairo.balart@metempsy.comGicv3CPUInterface::getHPPIR1() const 167513531Sjairo.balart@metempsy.com{ 167614233Sgiacomo.travaglini@arm.com if (hppi.prio == 0xff || !groupEnabled(hppi.group)) { 167713531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 167813531Sjairo.balart@metempsy.com } 167913531Sjairo.balart@metempsy.com 168013760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 168113760Sjairo.balart@metempsy.com if ((currEL() == EL3) && icc_ctlr_el3.RM) { 168213531Sjairo.balart@metempsy.com if (hppi.group == Gicv3::G0S) { 168313531Sjairo.balart@metempsy.com return Gicv3::INTID_SECURE; 168413531Sjairo.balart@metempsy.com } else if (hppi.group == Gicv3::G1NS) { 168513531Sjairo.balart@metempsy.com return Gicv3::INTID_NONSECURE; 168613531Sjairo.balart@metempsy.com } 168713531Sjairo.balart@metempsy.com } 168813531Sjairo.balart@metempsy.com 168913531Sjairo.balart@metempsy.com if (hppi.group == Gicv3::G0S) { 169013531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 169113531Sjairo.balart@metempsy.com } 169213531Sjairo.balart@metempsy.com 169313531Sjairo.balart@metempsy.com bool irq_is_secure = (distributor->DS == 0) && (hppi.group != Gicv3::G1NS); 169413531Sjairo.balart@metempsy.com 169513531Sjairo.balart@metempsy.com if (irq_is_secure) { 169613531Sjairo.balart@metempsy.com if (!inSecureState()) { 169713531Sjairo.balart@metempsy.com // Secure interrupts not visible in Non-secure 169813531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 169913531Sjairo.balart@metempsy.com } 170013531Sjairo.balart@metempsy.com } else if (!isEL3OrMon() && inSecureState()) { 170113531Sjairo.balart@metempsy.com // Group 1 non-secure interrupts not visible in Secure EL1 170213531Sjairo.balart@metempsy.com return Gicv3::INTID_SPURIOUS; 170313531Sjairo.balart@metempsy.com } 170413531Sjairo.balart@metempsy.com 170513531Sjairo.balart@metempsy.com return hppi.intid; 170613531Sjairo.balart@metempsy.com} 170713531Sjairo.balart@metempsy.com 170813531Sjairo.balart@metempsy.comvoid 170913531Sjairo.balart@metempsy.comGicv3CPUInterface::dropPriority(Gicv3::GroupId group) 171013531Sjairo.balart@metempsy.com{ 171114246Sgiacomo.travaglini@arm.com int apr_misc_reg = 0; 171214246Sgiacomo.travaglini@arm.com 171314246Sgiacomo.travaglini@arm.com switch (group) { 171414246Sgiacomo.travaglini@arm.com case Gicv3::G0S: 171514246Sgiacomo.travaglini@arm.com apr_misc_reg = MISCREG_ICC_AP0R0_EL1; 171614246Sgiacomo.travaglini@arm.com break; 171714246Sgiacomo.travaglini@arm.com case Gicv3::G1S: 171814246Sgiacomo.travaglini@arm.com apr_misc_reg = MISCREG_ICC_AP1R0_EL1_S; 171914246Sgiacomo.travaglini@arm.com break; 172014246Sgiacomo.travaglini@arm.com case Gicv3::G1NS: 172114246Sgiacomo.travaglini@arm.com apr_misc_reg = MISCREG_ICC_AP1R0_EL1_NS; 172214246Sgiacomo.travaglini@arm.com break; 172314246Sgiacomo.travaglini@arm.com default: 172414246Sgiacomo.travaglini@arm.com panic("Invalid Gicv3::GroupId"); 172514246Sgiacomo.travaglini@arm.com } 172614246Sgiacomo.travaglini@arm.com 172714246Sgiacomo.travaglini@arm.com RegVal apr = isa->readMiscRegNoEffect(apr_misc_reg); 172813531Sjairo.balart@metempsy.com 172913531Sjairo.balart@metempsy.com if (apr) { 173013531Sjairo.balart@metempsy.com apr &= apr - 1; 173113531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(apr_misc_reg, apr); 173213531Sjairo.balart@metempsy.com } 173313531Sjairo.balart@metempsy.com 173413531Sjairo.balart@metempsy.com update(); 173513531Sjairo.balart@metempsy.com} 173613531Sjairo.balart@metempsy.com 173713531Sjairo.balart@metempsy.comuint8_t 173813531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualDropPriority() 173913531Sjairo.balart@metempsy.com{ 174013531Sjairo.balart@metempsy.com int apr_max = 1 << (VIRTUAL_PREEMPTION_BITS - 5); 174113531Sjairo.balart@metempsy.com 174213531Sjairo.balart@metempsy.com for (int i = 0; i < apr_max; i++) { 174313580Sgabeblack@google.com RegVal vapr0 = isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i); 174413580Sgabeblack@google.com RegVal vapr1 = isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i); 174513531Sjairo.balart@metempsy.com 174613531Sjairo.balart@metempsy.com if (!vapr0 && !vapr1) { 174713531Sjairo.balart@metempsy.com continue; 174813531Sjairo.balart@metempsy.com } 174913531Sjairo.balart@metempsy.com 175013531Sjairo.balart@metempsy.com int vapr0_count = ctz32(vapr0); 175113531Sjairo.balart@metempsy.com int vapr1_count = ctz32(vapr1); 175213531Sjairo.balart@metempsy.com 175313531Sjairo.balart@metempsy.com if (vapr0_count <= vapr1_count) { 175413531Sjairo.balart@metempsy.com vapr0 &= vapr0 - 1; 175513531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i, vapr0); 175613531Sjairo.balart@metempsy.com return (vapr0_count + i * 32) << (GIC_MIN_VBPR + 1); 175713531Sjairo.balart@metempsy.com } else { 175813531Sjairo.balart@metempsy.com vapr1 &= vapr1 - 1; 175913531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i, vapr1); 176013531Sjairo.balart@metempsy.com return (vapr1_count + i * 32) << (GIC_MIN_VBPR + 1); 176113531Sjairo.balart@metempsy.com } 176213531Sjairo.balart@metempsy.com } 176313531Sjairo.balart@metempsy.com 176413531Sjairo.balart@metempsy.com return 0xff; 176513531Sjairo.balart@metempsy.com} 176613531Sjairo.balart@metempsy.com 176713531Sjairo.balart@metempsy.comvoid 176814227Sgiacomo.travaglini@arm.comGicv3CPUInterface::generateSGI(RegVal val, Gicv3::GroupId group) 176914227Sgiacomo.travaglini@arm.com{ 177014227Sgiacomo.travaglini@arm.com uint8_t aff3 = bits(val, 55, 48); 177114227Sgiacomo.travaglini@arm.com uint8_t aff2 = bits(val, 39, 32); 177214227Sgiacomo.travaglini@arm.com uint8_t aff1 = bits(val, 23, 16);; 177314227Sgiacomo.travaglini@arm.com uint16_t target_list = bits(val, 15, 0); 177414227Sgiacomo.travaglini@arm.com uint32_t int_id = bits(val, 27, 24); 177514227Sgiacomo.travaglini@arm.com bool irm = bits(val, 40, 40); 177614227Sgiacomo.travaglini@arm.com uint8_t rs = bits(val, 47, 44); 177714227Sgiacomo.travaglini@arm.com 177814227Sgiacomo.travaglini@arm.com bool ns = !inSecureState(); 177914227Sgiacomo.travaglini@arm.com 178014227Sgiacomo.travaglini@arm.com for (int i = 0; i < gic->getSystem()->numContexts(); i++) { 178114227Sgiacomo.travaglini@arm.com Gicv3Redistributor * redistributor_i = 178214227Sgiacomo.travaglini@arm.com gic->getRedistributor(i); 178314227Sgiacomo.travaglini@arm.com uint32_t affinity_i = redistributor_i->getAffinity(); 178414227Sgiacomo.travaglini@arm.com 178514227Sgiacomo.travaglini@arm.com if (irm) { 178614227Sgiacomo.travaglini@arm.com // Interrupts routed to all PEs in the system, 178714227Sgiacomo.travaglini@arm.com // excluding "self" 178814227Sgiacomo.travaglini@arm.com if (affinity_i == redistributor->getAffinity()) { 178914227Sgiacomo.travaglini@arm.com continue; 179014227Sgiacomo.travaglini@arm.com } 179114227Sgiacomo.travaglini@arm.com } else { 179214227Sgiacomo.travaglini@arm.com // Interrupts routed to the PEs specified by 179314227Sgiacomo.travaglini@arm.com // Aff3.Aff2.Aff1.<target list> 179414227Sgiacomo.travaglini@arm.com if ((affinity_i >> 8) != 179514227Sgiacomo.travaglini@arm.com ((aff3 << 16) | (aff2 << 8) | (aff1 << 0))) { 179614227Sgiacomo.travaglini@arm.com continue; 179714227Sgiacomo.travaglini@arm.com } 179814227Sgiacomo.travaglini@arm.com 179914227Sgiacomo.travaglini@arm.com uint8_t aff0_i = bits(affinity_i, 7, 0); 180014227Sgiacomo.travaglini@arm.com 180114227Sgiacomo.travaglini@arm.com if (!(aff0_i >= rs * 16 && aff0_i < (rs + 1) * 16 && 180214227Sgiacomo.travaglini@arm.com ((0x1 << (aff0_i - rs * 16)) & target_list))) { 180314227Sgiacomo.travaglini@arm.com continue; 180414227Sgiacomo.travaglini@arm.com } 180514227Sgiacomo.travaglini@arm.com } 180614227Sgiacomo.travaglini@arm.com 180714227Sgiacomo.travaglini@arm.com redistributor_i->sendSGI(int_id, group, ns); 180814227Sgiacomo.travaglini@arm.com } 180914227Sgiacomo.travaglini@arm.com} 181014227Sgiacomo.travaglini@arm.com 181114227Sgiacomo.travaglini@arm.comvoid 181213531Sjairo.balart@metempsy.comGicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group) 181313531Sjairo.balart@metempsy.com{ 181413531Sjairo.balart@metempsy.com // Update active priority registers. 181513531Sjairo.balart@metempsy.com uint32_t prio = hppi.prio & 0xf8; 181613531Sjairo.balart@metempsy.com int apr_bit = prio >> (8 - PRIORITY_BITS); 181713531Sjairo.balart@metempsy.com int reg_bit = apr_bit % 32; 181814246Sgiacomo.travaglini@arm.com 181914246Sgiacomo.travaglini@arm.com int apr_idx = 0; 182014246Sgiacomo.travaglini@arm.com switch (group) { 182114246Sgiacomo.travaglini@arm.com case Gicv3::G0S: 182214246Sgiacomo.travaglini@arm.com apr_idx = MISCREG_ICC_AP0R0_EL1; 182314246Sgiacomo.travaglini@arm.com break; 182414246Sgiacomo.travaglini@arm.com case Gicv3::G1S: 182514246Sgiacomo.travaglini@arm.com apr_idx = MISCREG_ICC_AP1R0_EL1_S; 182614246Sgiacomo.travaglini@arm.com break; 182714246Sgiacomo.travaglini@arm.com case Gicv3::G1NS: 182814246Sgiacomo.travaglini@arm.com apr_idx = MISCREG_ICC_AP1R0_EL1_NS; 182914246Sgiacomo.travaglini@arm.com break; 183014246Sgiacomo.travaglini@arm.com default: 183114246Sgiacomo.travaglini@arm.com panic("Invalid Gicv3::GroupId"); 183214246Sgiacomo.travaglini@arm.com } 183314246Sgiacomo.travaglini@arm.com 183413580Sgabeblack@google.com RegVal apr = isa->readMiscRegNoEffect(apr_idx); 183513531Sjairo.balart@metempsy.com apr |= (1 << reg_bit); 183613531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(apr_idx, apr); 183713531Sjairo.balart@metempsy.com 183813531Sjairo.balart@metempsy.com // Move interrupt state from pending to active. 183913531Sjairo.balart@metempsy.com if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) { 184013531Sjairo.balart@metempsy.com // SGI or PPI, redistributor 184113531Sjairo.balart@metempsy.com redistributor->activateIRQ(int_id); 184213531Sjairo.balart@metempsy.com } else if (int_id < Gicv3::INTID_SECURE) { 184313531Sjairo.balart@metempsy.com // SPI, distributor 184413531Sjairo.balart@metempsy.com distributor->activateIRQ(int_id); 184513923Sgiacomo.travaglini@arm.com } else if (int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) { 184613923Sgiacomo.travaglini@arm.com // LPI, Redistributor 184713923Sgiacomo.travaglini@arm.com redistributor->setClrLPI(int_id, false); 184813531Sjairo.balart@metempsy.com } 184914231Sgiacomo.travaglini@arm.com 185014231Sgiacomo.travaglini@arm.com // By setting the priority to 0xff we are effectively 185114231Sgiacomo.travaglini@arm.com // making the int_id not pending anymore at the cpu 185214231Sgiacomo.travaglini@arm.com // interface. 185314259Sgiacomo.travaglini@arm.com resetHppi(int_id); 185414231Sgiacomo.travaglini@arm.com updateDistributor(); 185513531Sjairo.balart@metempsy.com} 185613531Sjairo.balart@metempsy.com 185713531Sjairo.balart@metempsy.comvoid 185813531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx) 185913531Sjairo.balart@metempsy.com{ 186013531Sjairo.balart@metempsy.com // Update active priority registers. 186113760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + 186213531Sjairo.balart@metempsy.com lr_idx); 186313760Sjairo.balart@metempsy.com Gicv3::GroupId group = ich_lr_el.Group ? Gicv3::G1NS : Gicv3::G0S; 186413760Sjairo.balart@metempsy.com uint8_t prio = ich_lr_el.Priority & 0xf8; 186513531Sjairo.balart@metempsy.com int apr_bit = prio >> (8 - VIRTUAL_PREEMPTION_BITS); 186613531Sjairo.balart@metempsy.com int reg_no = apr_bit / 32; 186713531Sjairo.balart@metempsy.com int reg_bit = apr_bit % 32; 186813531Sjairo.balart@metempsy.com int apr_idx = group == Gicv3::G0S ? 186913531Sjairo.balart@metempsy.com MISCREG_ICH_AP0R0_EL2 + reg_no : MISCREG_ICH_AP1R0_EL2 + reg_no; 187013580Sgabeblack@google.com RegVal apr = isa->readMiscRegNoEffect(apr_idx); 187113531Sjairo.balart@metempsy.com apr |= (1 << reg_bit); 187213531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(apr_idx, apr); 187313531Sjairo.balart@metempsy.com // Move interrupt state from pending to active. 187413760Sjairo.balart@metempsy.com ich_lr_el.State = ICH_LR_EL2_STATE_ACTIVE; 187513760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el); 187613531Sjairo.balart@metempsy.com} 187713531Sjairo.balart@metempsy.com 187813531Sjairo.balart@metempsy.comvoid 187913531Sjairo.balart@metempsy.comGicv3CPUInterface::deactivateIRQ(uint32_t int_id, Gicv3::GroupId group) 188013531Sjairo.balart@metempsy.com{ 188113531Sjairo.balart@metempsy.com if (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX) { 188213531Sjairo.balart@metempsy.com // SGI or PPI, redistributor 188313531Sjairo.balart@metempsy.com redistributor->deactivateIRQ(int_id); 188413531Sjairo.balart@metempsy.com } else if (int_id < Gicv3::INTID_SECURE) { 188513531Sjairo.balart@metempsy.com // SPI, distributor 188613531Sjairo.balart@metempsy.com distributor->deactivateIRQ(int_id); 188713531Sjairo.balart@metempsy.com } 188814231Sgiacomo.travaglini@arm.com 188914231Sgiacomo.travaglini@arm.com updateDistributor(); 189013531Sjairo.balart@metempsy.com} 189113531Sjairo.balart@metempsy.com 189213531Sjairo.balart@metempsy.comvoid 189313531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualDeactivateIRQ(int lr_idx) 189413531Sjairo.balart@metempsy.com{ 189513760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + 189613531Sjairo.balart@metempsy.com lr_idx); 189713531Sjairo.balart@metempsy.com 189813760Sjairo.balart@metempsy.com if (ich_lr_el2.HW) { 189913531Sjairo.balart@metempsy.com // Deactivate the associated physical interrupt 190013760Sjairo.balart@metempsy.com if (ich_lr_el2.pINTID < Gicv3::INTID_SECURE) { 190113760Sjairo.balart@metempsy.com Gicv3::GroupId group = ich_lr_el2.pINTID >= 32 ? 190213760Sjairo.balart@metempsy.com distributor->getIntGroup(ich_lr_el2.pINTID) : 190313760Sjairo.balart@metempsy.com redistributor->getIntGroup(ich_lr_el2.pINTID); 190413760Sjairo.balart@metempsy.com deactivateIRQ(ich_lr_el2.pINTID, group); 190513531Sjairo.balart@metempsy.com } 190613531Sjairo.balart@metempsy.com } 190713531Sjairo.balart@metempsy.com 190813531Sjairo.balart@metempsy.com // Remove the active bit 190913760Sjairo.balart@metempsy.com ich_lr_el2.State = ich_lr_el2.State & ~ICH_LR_EL2_STATE_ACTIVE; 191013760Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx, ich_lr_el2); 191113531Sjairo.balart@metempsy.com} 191213531Sjairo.balart@metempsy.com 191313531Sjairo.balart@metempsy.com/* 191413760Sjairo.balart@metempsy.com * Returns the priority group field for the current BPR value for the group. 191513760Sjairo.balart@metempsy.com * GroupBits() Pseudocode from spec. 191613531Sjairo.balart@metempsy.com */ 191713531Sjairo.balart@metempsy.comuint32_t 191813926Sgiacomo.travaglini@arm.comGicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group) 191913531Sjairo.balart@metempsy.com{ 192013760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_s = 192113760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 192213760Sjairo.balart@metempsy.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 192313760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 192413760Sjairo.balart@metempsy.com 192513760Sjairo.balart@metempsy.com if ((group == Gicv3::G1S && icc_ctlr_el1_s.CBPR) || 192613760Sjairo.balart@metempsy.com (group == Gicv3::G1NS && icc_ctlr_el1_ns.CBPR)) { 192713531Sjairo.balart@metempsy.com group = Gicv3::G0S; 192813531Sjairo.balart@metempsy.com } 192913531Sjairo.balart@metempsy.com 193013531Sjairo.balart@metempsy.com int bpr; 193113531Sjairo.balart@metempsy.com 193213531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 193313926Sgiacomo.travaglini@arm.com bpr = readMiscReg(MISCREG_ICC_BPR0_EL1) & 0x7; 193414237Sgiacomo.travaglini@arm.com } else if (group == Gicv3::G1S) { 193514237Sgiacomo.travaglini@arm.com bpr = bpr1(Gicv3::G1S) & 0x7; 193613531Sjairo.balart@metempsy.com } else { 193714237Sgiacomo.travaglini@arm.com bpr = bpr1(Gicv3::G1NS) & 0x7; 193813531Sjairo.balart@metempsy.com } 193913531Sjairo.balart@metempsy.com 194013531Sjairo.balart@metempsy.com if (group == Gicv3::G1NS) { 194113531Sjairo.balart@metempsy.com assert(bpr > 0); 194213531Sjairo.balart@metempsy.com bpr--; 194313531Sjairo.balart@metempsy.com } 194413531Sjairo.balart@metempsy.com 194513531Sjairo.balart@metempsy.com return ~0U << (bpr + 1); 194613531Sjairo.balart@metempsy.com} 194713531Sjairo.balart@metempsy.com 194813531Sjairo.balart@metempsy.comuint32_t 194913760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualGroupPriorityMask(Gicv3::GroupId group) const 195013531Sjairo.balart@metempsy.com{ 195113760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 195213531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 195313531Sjairo.balart@metempsy.com 195413760Sjairo.balart@metempsy.com if ((group == Gicv3::G1NS) && ich_vmcr_el2.VCBPR) { 195513531Sjairo.balart@metempsy.com group = Gicv3::G0S; 195613531Sjairo.balart@metempsy.com } 195713531Sjairo.balart@metempsy.com 195813531Sjairo.balart@metempsy.com int bpr; 195913531Sjairo.balart@metempsy.com 196013531Sjairo.balart@metempsy.com if (group == Gicv3::G0S) { 196113760Sjairo.balart@metempsy.com bpr = ich_vmcr_el2.VBPR0; 196213531Sjairo.balart@metempsy.com } else { 196313760Sjairo.balart@metempsy.com bpr = ich_vmcr_el2.VBPR1; 196413531Sjairo.balart@metempsy.com } 196513531Sjairo.balart@metempsy.com 196613531Sjairo.balart@metempsy.com if (group == Gicv3::G1NS) { 196713531Sjairo.balart@metempsy.com assert(bpr > 0); 196813531Sjairo.balart@metempsy.com bpr--; 196913531Sjairo.balart@metempsy.com } 197013531Sjairo.balart@metempsy.com 197113531Sjairo.balart@metempsy.com return ~0U << (bpr + 1); 197213531Sjairo.balart@metempsy.com} 197313531Sjairo.balart@metempsy.com 197413531Sjairo.balart@metempsy.combool 197513760Sjairo.balart@metempsy.comGicv3CPUInterface::isEOISplitMode() const 197613531Sjairo.balart@metempsy.com{ 197713531Sjairo.balart@metempsy.com if (isEL3OrMon()) { 197813760Sjairo.balart@metempsy.com ICC_CTLR_EL3 icc_ctlr_el3 = 197913760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3); 198013760Sjairo.balart@metempsy.com return icc_ctlr_el3.EOImode_EL3; 198113531Sjairo.balart@metempsy.com } else { 198214245Sgiacomo.travaglini@arm.com ICC_CTLR_EL1 icc_ctlr_el1 = 0; 198314245Sgiacomo.travaglini@arm.com if (inSecureState()) 198414245Sgiacomo.travaglini@arm.com icc_ctlr_el1 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 198514245Sgiacomo.travaglini@arm.com else 198614245Sgiacomo.travaglini@arm.com icc_ctlr_el1 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 198713760Sjairo.balart@metempsy.com return icc_ctlr_el1.EOImode; 198813531Sjairo.balart@metempsy.com } 198913531Sjairo.balart@metempsy.com} 199013531Sjairo.balart@metempsy.com 199113531Sjairo.balart@metempsy.combool 199213760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualIsEOISplitMode() const 199313531Sjairo.balart@metempsy.com{ 199413760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 199513760Sjairo.balart@metempsy.com return ich_vmcr_el2.VEOIM; 199613531Sjairo.balart@metempsy.com} 199713531Sjairo.balart@metempsy.com 199813531Sjairo.balart@metempsy.comint 199913760Sjairo.balart@metempsy.comGicv3CPUInterface::highestActiveGroup() const 200013531Sjairo.balart@metempsy.com{ 200113531Sjairo.balart@metempsy.com int g0_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1)); 200213531Sjairo.balart@metempsy.com int gq_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S)); 200313531Sjairo.balart@metempsy.com int g1nz_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS)); 200413531Sjairo.balart@metempsy.com 200513531Sjairo.balart@metempsy.com if (g1nz_ctz < g0_ctz && g1nz_ctz < gq_ctz) { 200613531Sjairo.balart@metempsy.com return Gicv3::G1NS; 200713531Sjairo.balart@metempsy.com } 200813531Sjairo.balart@metempsy.com 200913531Sjairo.balart@metempsy.com if (gq_ctz < g0_ctz) { 201013531Sjairo.balart@metempsy.com return Gicv3::G1S; 201113531Sjairo.balart@metempsy.com } 201213531Sjairo.balart@metempsy.com 201313531Sjairo.balart@metempsy.com if (g0_ctz < 32) { 201413531Sjairo.balart@metempsy.com return Gicv3::G0S; 201513531Sjairo.balart@metempsy.com } 201613531Sjairo.balart@metempsy.com 201713531Sjairo.balart@metempsy.com return -1; 201813531Sjairo.balart@metempsy.com} 201913531Sjairo.balart@metempsy.com 202013531Sjairo.balart@metempsy.comvoid 202114231Sgiacomo.travaglini@arm.comGicv3CPUInterface::updateDistributor() 202214231Sgiacomo.travaglini@arm.com{ 202314231Sgiacomo.travaglini@arm.com distributor->update(); 202414231Sgiacomo.travaglini@arm.com} 202514231Sgiacomo.travaglini@arm.com 202614231Sgiacomo.travaglini@arm.comvoid 202713531Sjairo.balart@metempsy.comGicv3CPUInterface::update() 202813531Sjairo.balart@metempsy.com{ 202913531Sjairo.balart@metempsy.com bool signal_IRQ = false; 203013531Sjairo.balart@metempsy.com bool signal_FIQ = false; 203113531Sjairo.balart@metempsy.com 203213531Sjairo.balart@metempsy.com if (hppi.group == Gicv3::G1S && !haveEL(EL3)) { 203313531Sjairo.balart@metempsy.com /* 203413531Sjairo.balart@metempsy.com * Secure enabled GIC sending a G1S IRQ to a secure disabled 203513531Sjairo.balart@metempsy.com * CPU -> send G0 IRQ 203613531Sjairo.balart@metempsy.com */ 203713531Sjairo.balart@metempsy.com hppi.group = Gicv3::G0S; 203813531Sjairo.balart@metempsy.com } 203913531Sjairo.balart@metempsy.com 204013531Sjairo.balart@metempsy.com if (hppiCanPreempt()) { 204113531Sjairo.balart@metempsy.com ArmISA::InterruptTypes int_type = intSignalType(hppi.group); 204213531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::update(): " 204313531Sjairo.balart@metempsy.com "posting int as %d!\n", int_type); 204413531Sjairo.balart@metempsy.com int_type == ArmISA::INT_IRQ ? signal_IRQ = true : signal_FIQ = true; 204513531Sjairo.balart@metempsy.com } 204613531Sjairo.balart@metempsy.com 204713531Sjairo.balart@metempsy.com if (signal_IRQ) { 204813531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_IRQ); 204913531Sjairo.balart@metempsy.com } else { 205013531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_IRQ); 205113531Sjairo.balart@metempsy.com } 205213531Sjairo.balart@metempsy.com 205313531Sjairo.balart@metempsy.com if (signal_FIQ) { 205413531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_FIQ); 205513531Sjairo.balart@metempsy.com } else { 205613531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_FIQ); 205713531Sjairo.balart@metempsy.com } 205813531Sjairo.balart@metempsy.com} 205913531Sjairo.balart@metempsy.com 206013531Sjairo.balart@metempsy.comvoid 206113531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualUpdate() 206213531Sjairo.balart@metempsy.com{ 206313531Sjairo.balart@metempsy.com bool signal_IRQ = false; 206413531Sjairo.balart@metempsy.com bool signal_FIQ = false; 206513531Sjairo.balart@metempsy.com int lr_idx = getHPPVILR(); 206613531Sjairo.balart@metempsy.com 206713531Sjairo.balart@metempsy.com if (lr_idx >= 0) { 206813760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 206913531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 207013531Sjairo.balart@metempsy.com 207113531Sjairo.balart@metempsy.com if (hppviCanPreempt(lr_idx)) { 207213760Sjairo.balart@metempsy.com if (ich_lr_el2.Group) { 207313531Sjairo.balart@metempsy.com signal_IRQ = true; 207413531Sjairo.balart@metempsy.com } else { 207513531Sjairo.balart@metempsy.com signal_FIQ = true; 207613531Sjairo.balart@metempsy.com } 207713531Sjairo.balart@metempsy.com } 207813531Sjairo.balart@metempsy.com } 207913531Sjairo.balart@metempsy.com 208013760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 208113760Sjairo.balart@metempsy.com 208213760Sjairo.balart@metempsy.com if (ich_hcr_el2.En) { 208313531Sjairo.balart@metempsy.com if (maintenanceInterruptStatus()) { 208413826Sgiacomo.travaglini@arm.com maintenanceInterrupt->raise(); 208513531Sjairo.balart@metempsy.com } 208613531Sjairo.balart@metempsy.com } 208713531Sjairo.balart@metempsy.com 208813531Sjairo.balart@metempsy.com if (signal_IRQ) { 208913531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): " 209013531Sjairo.balart@metempsy.com "posting int as %d!\n", ArmISA::INT_VIRT_IRQ); 209113531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_VIRT_IRQ); 209213531Sjairo.balart@metempsy.com } else { 209313531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_VIRT_IRQ); 209413531Sjairo.balart@metempsy.com } 209513531Sjairo.balart@metempsy.com 209613531Sjairo.balart@metempsy.com if (signal_FIQ) { 209713531Sjairo.balart@metempsy.com DPRINTF(GIC, "Gicv3CPUInterface::virtualUpdate(): " 209813531Sjairo.balart@metempsy.com "posting int as %d!\n", ArmISA::INT_VIRT_FIQ); 209913531Sjairo.balart@metempsy.com gic->postInt(cpuId, ArmISA::INT_VIRT_FIQ); 210013531Sjairo.balart@metempsy.com } else { 210113531Sjairo.balart@metempsy.com gic->deassertInt(cpuId, ArmISA::INT_VIRT_FIQ); 210213531Sjairo.balart@metempsy.com } 210313531Sjairo.balart@metempsy.com} 210413531Sjairo.balart@metempsy.com 210513760Sjairo.balart@metempsy.com// Returns the index of the LR with the HPPI 210613531Sjairo.balart@metempsy.comint 210713760Sjairo.balart@metempsy.comGicv3CPUInterface::getHPPVILR() const 210813531Sjairo.balart@metempsy.com{ 210913531Sjairo.balart@metempsy.com int idx = -1; 211013760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 211113760Sjairo.balart@metempsy.com 211213760Sjairo.balart@metempsy.com if (!ich_vmcr_el2.VENG0 && !ich_vmcr_el2.VENG1) { 211313531Sjairo.balart@metempsy.com // VG0 and VG1 disabled... 211413531Sjairo.balart@metempsy.com return idx; 211513531Sjairo.balart@metempsy.com } 211613531Sjairo.balart@metempsy.com 211713531Sjairo.balart@metempsy.com uint8_t highest_prio = 0xff; 211813531Sjairo.balart@metempsy.com 211913531Sjairo.balart@metempsy.com for (int i = 0; i < 16; i++) { 212013760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 212113531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + i); 212213760Sjairo.balart@metempsy.com 212313760Sjairo.balart@metempsy.com if (ich_lr_el2.State != Gicv3::INT_PENDING) { 212413531Sjairo.balart@metempsy.com continue; 212513531Sjairo.balart@metempsy.com } 212613531Sjairo.balart@metempsy.com 212713760Sjairo.balart@metempsy.com if (ich_lr_el2.Group) { 212813531Sjairo.balart@metempsy.com // VG1 212913760Sjairo.balart@metempsy.com if (!ich_vmcr_el2.VENG1) { 213013531Sjairo.balart@metempsy.com continue; 213113531Sjairo.balart@metempsy.com } 213213531Sjairo.balart@metempsy.com } else { 213313531Sjairo.balart@metempsy.com // VG0 213413760Sjairo.balart@metempsy.com if (!ich_vmcr_el2.VENG0) { 213513531Sjairo.balart@metempsy.com continue; 213613531Sjairo.balart@metempsy.com } 213713531Sjairo.balart@metempsy.com } 213813531Sjairo.balart@metempsy.com 213913760Sjairo.balart@metempsy.com uint8_t prio = ich_lr_el2.Priority; 214013531Sjairo.balart@metempsy.com 214113531Sjairo.balart@metempsy.com if (prio < highest_prio) { 214213531Sjairo.balart@metempsy.com highest_prio = prio; 214313531Sjairo.balart@metempsy.com idx = i; 214413531Sjairo.balart@metempsy.com } 214513531Sjairo.balart@metempsy.com } 214613531Sjairo.balart@metempsy.com 214713531Sjairo.balart@metempsy.com return idx; 214813531Sjairo.balart@metempsy.com} 214913531Sjairo.balart@metempsy.com 215013531Sjairo.balart@metempsy.combool 215113760Sjairo.balart@metempsy.comGicv3CPUInterface::hppviCanPreempt(int lr_idx) const 215213531Sjairo.balart@metempsy.com{ 215313760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 215413760Sjairo.balart@metempsy.com if (!ich_hcr_el2.En) { 215513531Sjairo.balart@metempsy.com // virtual interface is disabled 215613531Sjairo.balart@metempsy.com return false; 215713531Sjairo.balart@metempsy.com } 215813531Sjairo.balart@metempsy.com 215913760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 216013760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 216113760Sjairo.balart@metempsy.com uint8_t prio = ich_lr_el2.Priority; 216213531Sjairo.balart@metempsy.com uint8_t vpmr = 216313531Sjairo.balart@metempsy.com bits(isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2), 31, 24); 216413531Sjairo.balart@metempsy.com 216513531Sjairo.balart@metempsy.com if (prio >= vpmr) { 216613531Sjairo.balart@metempsy.com // prioriry masked 216713531Sjairo.balart@metempsy.com return false; 216813531Sjairo.balart@metempsy.com } 216913531Sjairo.balart@metempsy.com 217013531Sjairo.balart@metempsy.com uint8_t rprio = virtualHighestActivePriority(); 217113531Sjairo.balart@metempsy.com 217213531Sjairo.balart@metempsy.com if (rprio == 0xff) { 217313531Sjairo.balart@metempsy.com return true; 217413531Sjairo.balart@metempsy.com } 217513531Sjairo.balart@metempsy.com 217613760Sjairo.balart@metempsy.com Gicv3::GroupId group = ich_lr_el2.Group ? Gicv3::G1NS : Gicv3::G0S; 217713531Sjairo.balart@metempsy.com uint32_t prio_mask = virtualGroupPriorityMask(group); 217813531Sjairo.balart@metempsy.com 217913531Sjairo.balart@metempsy.com if ((prio & prio_mask) < (rprio & prio_mask)) { 218013531Sjairo.balart@metempsy.com return true; 218113531Sjairo.balart@metempsy.com } 218213531Sjairo.balart@metempsy.com 218313531Sjairo.balart@metempsy.com return false; 218413531Sjairo.balart@metempsy.com} 218513531Sjairo.balart@metempsy.com 218613531Sjairo.balart@metempsy.comuint8_t 218713760Sjairo.balart@metempsy.comGicv3CPUInterface::virtualHighestActivePriority() const 218813531Sjairo.balart@metempsy.com{ 218913531Sjairo.balart@metempsy.com uint8_t num_aprs = 1 << (VIRTUAL_PRIORITY_BITS - 5); 219013531Sjairo.balart@metempsy.com 219113531Sjairo.balart@metempsy.com for (int i = 0; i < num_aprs; i++) { 219213580Sgabeblack@google.com RegVal vapr = 219313531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i) | 219413531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i); 219513531Sjairo.balart@metempsy.com 219613531Sjairo.balart@metempsy.com if (!vapr) { 219713531Sjairo.balart@metempsy.com continue; 219813531Sjairo.balart@metempsy.com } 219913531Sjairo.balart@metempsy.com 220013531Sjairo.balart@metempsy.com return (i * 32 + ctz32(vapr)) << (GIC_MIN_VBPR + 1); 220113531Sjairo.balart@metempsy.com } 220213531Sjairo.balart@metempsy.com 220313531Sjairo.balart@metempsy.com // no active interrups, return idle priority 220413531Sjairo.balart@metempsy.com return 0xff; 220513531Sjairo.balart@metempsy.com} 220613531Sjairo.balart@metempsy.com 220713531Sjairo.balart@metempsy.comvoid 220813531Sjairo.balart@metempsy.comGicv3CPUInterface::virtualIncrementEOICount() 220913531Sjairo.balart@metempsy.com{ 221013531Sjairo.balart@metempsy.com // Increment the EOICOUNT field in ICH_HCR_EL2 221113580Sgabeblack@google.com RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 221213531Sjairo.balart@metempsy.com uint32_t EOI_cout = bits(ich_hcr_el2, 31, 27); 221313531Sjairo.balart@metempsy.com EOI_cout++; 221413531Sjairo.balart@metempsy.com ich_hcr_el2 = insertBits(ich_hcr_el2, 31, 27, EOI_cout); 221513531Sjairo.balart@metempsy.com isa->setMiscRegNoEffect(MISCREG_ICH_HCR_EL2, ich_hcr_el2); 221613531Sjairo.balart@metempsy.com} 221713531Sjairo.balart@metempsy.com 221813760Sjairo.balart@metempsy.com// spec section 4.6.2 221913531Sjairo.balart@metempsy.comArmISA::InterruptTypes 222013760Sjairo.balart@metempsy.comGicv3CPUInterface::intSignalType(Gicv3::GroupId group) const 222113531Sjairo.balart@metempsy.com{ 222213531Sjairo.balart@metempsy.com bool is_fiq = false; 222313531Sjairo.balart@metempsy.com 222413531Sjairo.balart@metempsy.com switch (group) { 222513531Sjairo.balart@metempsy.com case Gicv3::G0S: 222613531Sjairo.balart@metempsy.com is_fiq = true; 222713531Sjairo.balart@metempsy.com break; 222813531Sjairo.balart@metempsy.com 222913531Sjairo.balart@metempsy.com case Gicv3::G1S: 223013531Sjairo.balart@metempsy.com is_fiq = (distributor->DS == 0) && 223113531Sjairo.balart@metempsy.com (!inSecureState() || ((currEL() == EL3) && isAA64())); 223213531Sjairo.balart@metempsy.com break; 223313531Sjairo.balart@metempsy.com 223413531Sjairo.balart@metempsy.com case Gicv3::G1NS: 223513531Sjairo.balart@metempsy.com is_fiq = (distributor->DS == 0) && inSecureState(); 223613531Sjairo.balart@metempsy.com break; 223713531Sjairo.balart@metempsy.com 223813531Sjairo.balart@metempsy.com default: 223913531Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::intSignalType(): invalid group!"); 224013531Sjairo.balart@metempsy.com } 224113531Sjairo.balart@metempsy.com 224213531Sjairo.balart@metempsy.com if (is_fiq) { 224313531Sjairo.balart@metempsy.com return ArmISA::INT_FIQ; 224413531Sjairo.balart@metempsy.com } else { 224513531Sjairo.balart@metempsy.com return ArmISA::INT_IRQ; 224613531Sjairo.balart@metempsy.com } 224713531Sjairo.balart@metempsy.com} 224813531Sjairo.balart@metempsy.com 224913531Sjairo.balart@metempsy.combool 225013926Sgiacomo.travaglini@arm.comGicv3CPUInterface::hppiCanPreempt() 225113531Sjairo.balart@metempsy.com{ 225213531Sjairo.balart@metempsy.com if (hppi.prio == 0xff) { 225313531Sjairo.balart@metempsy.com // there is no pending interrupt 225413531Sjairo.balart@metempsy.com return false; 225513531Sjairo.balart@metempsy.com } 225613531Sjairo.balart@metempsy.com 225713531Sjairo.balart@metempsy.com if (!groupEnabled(hppi.group)) { 225813531Sjairo.balart@metempsy.com // group disabled at CPU interface 225913531Sjairo.balart@metempsy.com return false; 226013531Sjairo.balart@metempsy.com } 226113531Sjairo.balart@metempsy.com 226213531Sjairo.balart@metempsy.com if (hppi.prio >= isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1)) { 226313531Sjairo.balart@metempsy.com // priority masked 226413531Sjairo.balart@metempsy.com return false; 226513531Sjairo.balart@metempsy.com } 226613531Sjairo.balart@metempsy.com 226713531Sjairo.balart@metempsy.com uint8_t rprio = highestActivePriority(); 226813531Sjairo.balart@metempsy.com 226913531Sjairo.balart@metempsy.com if (rprio == 0xff) { 227013531Sjairo.balart@metempsy.com return true; 227113531Sjairo.balart@metempsy.com } 227213531Sjairo.balart@metempsy.com 227313531Sjairo.balart@metempsy.com uint32_t prio_mask = groupPriorityMask(hppi.group); 227413531Sjairo.balart@metempsy.com 227513531Sjairo.balart@metempsy.com if ((hppi.prio & prio_mask) < (rprio & prio_mask)) { 227613531Sjairo.balart@metempsy.com return true; 227713531Sjairo.balart@metempsy.com } 227813531Sjairo.balart@metempsy.com 227913531Sjairo.balart@metempsy.com return false; 228013531Sjairo.balart@metempsy.com} 228113531Sjairo.balart@metempsy.com 228213531Sjairo.balart@metempsy.comuint8_t 228313760Sjairo.balart@metempsy.comGicv3CPUInterface::highestActivePriority() const 228413531Sjairo.balart@metempsy.com{ 228513531Sjairo.balart@metempsy.com uint32_t apr = isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1) | 228613531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS) | 228713531Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S); 228813531Sjairo.balart@metempsy.com 228913531Sjairo.balart@metempsy.com if (apr) { 229013531Sjairo.balart@metempsy.com return ctz32(apr) << (GIC_MIN_BPR + 1); 229113531Sjairo.balart@metempsy.com } 229213531Sjairo.balart@metempsy.com 229313531Sjairo.balart@metempsy.com // no active interrups, return idle priority 229413531Sjairo.balart@metempsy.com return 0xff; 229513531Sjairo.balart@metempsy.com} 229613531Sjairo.balart@metempsy.com 229713531Sjairo.balart@metempsy.combool 229813760Sjairo.balart@metempsy.comGicv3CPUInterface::groupEnabled(Gicv3::GroupId group) const 229913531Sjairo.balart@metempsy.com{ 230013531Sjairo.balart@metempsy.com switch (group) { 230113760Sjairo.balart@metempsy.com case Gicv3::G0S: { 230213760Sjairo.balart@metempsy.com ICC_IGRPEN0_EL1 icc_igrpen0_el1 = 230313760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1); 230414234Sgiacomo.travaglini@arm.com return icc_igrpen0_el1.Enable && distributor->EnableGrp0; 230513760Sjairo.balart@metempsy.com } 230613760Sjairo.balart@metempsy.com 230713760Sjairo.balart@metempsy.com case Gicv3::G1S: { 230813760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL1 icc_igrpen1_el1_s = 230913760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_S); 231014234Sgiacomo.travaglini@arm.com return icc_igrpen1_el1_s.Enable && distributor->EnableGrp1S; 231113760Sjairo.balart@metempsy.com } 231213760Sjairo.balart@metempsy.com 231313760Sjairo.balart@metempsy.com case Gicv3::G1NS: { 231413760Sjairo.balart@metempsy.com ICC_IGRPEN1_EL1 icc_igrpen1_el1_ns = 231513760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1_NS); 231614234Sgiacomo.travaglini@arm.com return icc_igrpen1_el1_ns.Enable && distributor->EnableGrp1NS; 231713760Sjairo.balart@metempsy.com } 231813531Sjairo.balart@metempsy.com 231913531Sjairo.balart@metempsy.com default: 232013531Sjairo.balart@metempsy.com panic("Gicv3CPUInterface::groupEnable(): invalid group!\n"); 232113531Sjairo.balart@metempsy.com } 232213531Sjairo.balart@metempsy.com} 232313531Sjairo.balart@metempsy.com 232413531Sjairo.balart@metempsy.combool 232513760Sjairo.balart@metempsy.comGicv3CPUInterface::inSecureState() const 232613531Sjairo.balart@metempsy.com{ 232713531Sjairo.balart@metempsy.com if (!gic->getSystem()->haveSecurity()) { 232813531Sjairo.balart@metempsy.com return false; 232913531Sjairo.balart@metempsy.com } 233013531Sjairo.balart@metempsy.com 233113531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 233213531Sjairo.balart@metempsy.com SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR); 233313531Sjairo.balart@metempsy.com return ArmISA::inSecureState(scr, cpsr); 233413531Sjairo.balart@metempsy.com} 233513531Sjairo.balart@metempsy.com 233613531Sjairo.balart@metempsy.comint 233713760Sjairo.balart@metempsy.comGicv3CPUInterface::currEL() const 233813531Sjairo.balart@metempsy.com{ 233913531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 234013531Sjairo.balart@metempsy.com bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 234113531Sjairo.balart@metempsy.com 234213531Sjairo.balart@metempsy.com if (is_64) { 234313531Sjairo.balart@metempsy.com return (ExceptionLevel)(uint8_t) cpsr.el; 234413531Sjairo.balart@metempsy.com } else { 234513531Sjairo.balart@metempsy.com switch (cpsr.mode) { 234613531Sjairo.balart@metempsy.com case MODE_USER: 234713531Sjairo.balart@metempsy.com return 0; 234813531Sjairo.balart@metempsy.com 234913531Sjairo.balart@metempsy.com case MODE_HYP: 235013531Sjairo.balart@metempsy.com return 2; 235113531Sjairo.balart@metempsy.com 235213531Sjairo.balart@metempsy.com case MODE_MON: 235313531Sjairo.balart@metempsy.com return 3; 235413531Sjairo.balart@metempsy.com 235513531Sjairo.balart@metempsy.com default: 235613531Sjairo.balart@metempsy.com return 1; 235713531Sjairo.balart@metempsy.com } 235813531Sjairo.balart@metempsy.com } 235913531Sjairo.balart@metempsy.com} 236013531Sjairo.balart@metempsy.com 236113531Sjairo.balart@metempsy.combool 236213760Sjairo.balart@metempsy.comGicv3CPUInterface::haveEL(ExceptionLevel el) const 236313531Sjairo.balart@metempsy.com{ 236413531Sjairo.balart@metempsy.com switch (el) { 236513531Sjairo.balart@metempsy.com case EL0: 236613531Sjairo.balart@metempsy.com case EL1: 236713531Sjairo.balart@metempsy.com return true; 236813531Sjairo.balart@metempsy.com 236913531Sjairo.balart@metempsy.com case EL2: 237013531Sjairo.balart@metempsy.com return gic->getSystem()->haveVirtualization(); 237113531Sjairo.balart@metempsy.com 237213531Sjairo.balart@metempsy.com case EL3: 237313531Sjairo.balart@metempsy.com return gic->getSystem()->haveSecurity(); 237413531Sjairo.balart@metempsy.com 237513531Sjairo.balart@metempsy.com default: 237613531Sjairo.balart@metempsy.com warn("Unimplemented Exception Level\n"); 237713531Sjairo.balart@metempsy.com return false; 237813531Sjairo.balart@metempsy.com } 237913531Sjairo.balart@metempsy.com} 238013531Sjairo.balart@metempsy.com 238113531Sjairo.balart@metempsy.combool 238213760Sjairo.balart@metempsy.comGicv3CPUInterface::isSecureBelowEL3() const 238313531Sjairo.balart@metempsy.com{ 238413531Sjairo.balart@metempsy.com SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); 238513531Sjairo.balart@metempsy.com return haveEL(EL3) && scr.ns == 0; 238613531Sjairo.balart@metempsy.com} 238713531Sjairo.balart@metempsy.com 238813531Sjairo.balart@metempsy.combool 238913760Sjairo.balart@metempsy.comGicv3CPUInterface::isAA64() const 239013531Sjairo.balart@metempsy.com{ 239113531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 239213531Sjairo.balart@metempsy.com return opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 239313531Sjairo.balart@metempsy.com} 239413531Sjairo.balart@metempsy.com 239513531Sjairo.balart@metempsy.combool 239613760Sjairo.balart@metempsy.comGicv3CPUInterface::isEL3OrMon() const 239713531Sjairo.balart@metempsy.com{ 239813531Sjairo.balart@metempsy.com if (haveEL(EL3)) { 239913531Sjairo.balart@metempsy.com CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR); 240013531Sjairo.balart@metempsy.com bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode); 240113531Sjairo.balart@metempsy.com 240213531Sjairo.balart@metempsy.com if (is_64 && (cpsr.el == EL3)) { 240313531Sjairo.balart@metempsy.com return true; 240413531Sjairo.balart@metempsy.com } else if (!is_64 && (cpsr.mode == MODE_MON)) { 240513531Sjairo.balart@metempsy.com return true; 240613531Sjairo.balart@metempsy.com } 240713531Sjairo.balart@metempsy.com } 240813531Sjairo.balart@metempsy.com 240913531Sjairo.balart@metempsy.com return false; 241013531Sjairo.balart@metempsy.com} 241113531Sjairo.balart@metempsy.com 241213760Sjairo.balart@metempsy.com// Computes ICH_EISR_EL2 241313760Sjairo.balart@metempsy.comuint64_t 241413760Sjairo.balart@metempsy.comGicv3CPUInterface::eoiMaintenanceInterruptStatus() const 241513531Sjairo.balart@metempsy.com{ 241613760Sjairo.balart@metempsy.com // ICH_EISR_EL2 241713760Sjairo.balart@metempsy.com // Bits [63:16] - RES0 241813760Sjairo.balart@metempsy.com // Status<n>, bit [n], for n = 0 to 15 241913760Sjairo.balart@metempsy.com // EOI maintenance interrupt status bit for List register <n>: 242013760Sjairo.balart@metempsy.com // 0 if List register <n>, ICH_LR<n>_EL2, does not have an EOI 242113760Sjairo.balart@metempsy.com // maintenance interrupt. 242213760Sjairo.balart@metempsy.com // 1 if List register <n>, ICH_LR<n>_EL2, has an EOI maintenance 242313760Sjairo.balart@metempsy.com // interrupt that has not been handled. 242413760Sjairo.balart@metempsy.com // 242513760Sjairo.balart@metempsy.com // For any ICH_LR<n>_EL2, the corresponding status bit is set to 1 if all 242613760Sjairo.balart@metempsy.com // of the following are true: 242713760Sjairo.balart@metempsy.com // - ICH_LR<n>_EL2.State is 0b00 (ICH_LR_EL2_STATE_INVALID). 242813760Sjairo.balart@metempsy.com // - ICH_LR<n>_EL2.HW is 0. 242913760Sjairo.balart@metempsy.com // - ICH_LR<n>_EL2.EOI (bit [41]) is 1. 243013760Sjairo.balart@metempsy.com 243113760Sjairo.balart@metempsy.com uint64_t value = 0; 243213531Sjairo.balart@metempsy.com 243313531Sjairo.balart@metempsy.com for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 243413760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 243513760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 243613760Sjairo.balart@metempsy.com 243713760Sjairo.balart@metempsy.com if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) && 243813760Sjairo.balart@metempsy.com !ich_lr_el2.HW && ich_lr_el2.EOI) { 243913531Sjairo.balart@metempsy.com value |= (1 << lr_idx); 244013531Sjairo.balart@metempsy.com } 244113760Sjairo.balart@metempsy.com } 244213760Sjairo.balart@metempsy.com 244313760Sjairo.balart@metempsy.com return value; 244413760Sjairo.balart@metempsy.com} 244513760Sjairo.balart@metempsy.com 244613760Sjairo.balart@metempsy.comGicv3CPUInterface::ICH_MISR_EL2 244713760Sjairo.balart@metempsy.comGicv3CPUInterface::maintenanceInterruptStatus() const 244813760Sjairo.balart@metempsy.com{ 244913760Sjairo.balart@metempsy.com // Comments are copied from SPEC section 9.4.7 (ID012119) 245013760Sjairo.balart@metempsy.com ICH_MISR_EL2 ich_misr_el2 = 0; 245113760Sjairo.balart@metempsy.com ICH_HCR_EL2 ich_hcr_el2 = 245213760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2); 245313760Sjairo.balart@metempsy.com ICH_VMCR_EL2 ich_vmcr_el2 = 245413760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2); 245513760Sjairo.balart@metempsy.com 245613760Sjairo.balart@metempsy.com // End Of Interrupt. [bit 0] 245713760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when at least one bit in 245813760Sjairo.balart@metempsy.com // ICH_EISR_EL2 is 1. 245913760Sjairo.balart@metempsy.com 246013760Sjairo.balart@metempsy.com if (eoiMaintenanceInterruptStatus()) { 246113760Sjairo.balart@metempsy.com ich_misr_el2.EOI = 1; 246213760Sjairo.balart@metempsy.com } 246313760Sjairo.balart@metempsy.com 246413760Sjairo.balart@metempsy.com // Underflow. [bit 1] 246513760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when ICH_HCR_EL2.UIE==1 and 246613760Sjairo.balart@metempsy.com // zero or one of the List register entries are marked as a valid 246713760Sjairo.balart@metempsy.com // interrupt, that is, if the corresponding ICH_LR<n>_EL2.State bits 246813760Sjairo.balart@metempsy.com // do not equal 0x0. 246913760Sjairo.balart@metempsy.com uint32_t num_valid_interrupts = 0; 247013760Sjairo.balart@metempsy.com uint32_t num_pending_interrupts = 0; 247113760Sjairo.balart@metempsy.com 247213760Sjairo.balart@metempsy.com for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) { 247313760Sjairo.balart@metempsy.com ICH_LR_EL2 ich_lr_el2 = 247413760Sjairo.balart@metempsy.com isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx); 247513760Sjairo.balart@metempsy.com 247613760Sjairo.balart@metempsy.com if (ich_lr_el2.State != ICH_LR_EL2_STATE_INVALID) { 247713760Sjairo.balart@metempsy.com num_valid_interrupts++; 247813531Sjairo.balart@metempsy.com } 247913531Sjairo.balart@metempsy.com 248013760Sjairo.balart@metempsy.com if (ich_lr_el2.State == ICH_LR_EL2_STATE_PENDING) { 248113760Sjairo.balart@metempsy.com num_pending_interrupts++; 248213531Sjairo.balart@metempsy.com } 248313531Sjairo.balart@metempsy.com } 248413531Sjairo.balart@metempsy.com 248513760Sjairo.balart@metempsy.com if (ich_hcr_el2.UIE && (num_valid_interrupts < 2)) { 248613760Sjairo.balart@metempsy.com ich_misr_el2.U = 1; 248713531Sjairo.balart@metempsy.com } 248813531Sjairo.balart@metempsy.com 248913760Sjairo.balart@metempsy.com // List Register Entry Not Present. [bit 2] 249013760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when ICH_HCR_EL2.LRENPIE==1 249113760Sjairo.balart@metempsy.com // and ICH_HCR_EL2.EOIcount is non-zero. 249213760Sjairo.balart@metempsy.com if (ich_hcr_el2.LRENPIE && ich_hcr_el2.EOIcount) { 249313760Sjairo.balart@metempsy.com ich_misr_el2.LRENP = 1; 249413531Sjairo.balart@metempsy.com } 249513531Sjairo.balart@metempsy.com 249613760Sjairo.balart@metempsy.com // No Pending. [bit 3] 249713760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when ICH_HCR_EL2.NPIE==1 and 249813760Sjairo.balart@metempsy.com // no List register is in pending state. 249913760Sjairo.balart@metempsy.com if (ich_hcr_el2.NPIE && (num_pending_interrupts == 0)) { 250013760Sjairo.balart@metempsy.com ich_misr_el2.NP = 1; 250113531Sjairo.balart@metempsy.com } 250213531Sjairo.balart@metempsy.com 250313760Sjairo.balart@metempsy.com // vPE Group 0 Enabled. [bit 4] 250413760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 250513760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp0EIE==1 and ICH_VMCR_EL2.VENG0==1. 250613760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp0EIE && ich_vmcr_el2.VENG0) { 250713760Sjairo.balart@metempsy.com ich_misr_el2.VGrp0E = 1; 250813531Sjairo.balart@metempsy.com } 250913531Sjairo.balart@metempsy.com 251013760Sjairo.balart@metempsy.com // vPE Group 0 Disabled. [bit 5] 251113760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 251213760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp0DIE==1 and ICH_VMCR_EL2.VENG0==0. 251313760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp0DIE && !ich_vmcr_el2.VENG0) { 251413760Sjairo.balart@metempsy.com ich_misr_el2.VGrp0D = 1; 251513531Sjairo.balart@metempsy.com } 251613531Sjairo.balart@metempsy.com 251713760Sjairo.balart@metempsy.com // vPE Group 1 Enabled. [bit 6] 251813760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 251913760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp1EIE==1 and ICH_VMCR_EL2.VENG1==is 1. 252013760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp1EIE && ich_vmcr_el2.VENG1) { 252113760Sjairo.balart@metempsy.com ich_misr_el2.VGrp1E = 1; 252213531Sjairo.balart@metempsy.com } 252313531Sjairo.balart@metempsy.com 252413760Sjairo.balart@metempsy.com // vPE Group 1 Disabled. [bit 7] 252513760Sjairo.balart@metempsy.com // This maintenance interrupt is asserted when 252613760Sjairo.balart@metempsy.com // ICH_HCR_EL2.VGrp1DIE==1 and ICH_VMCR_EL2.VENG1==is 0. 252713760Sjairo.balart@metempsy.com if (ich_hcr_el2.VGrp1DIE && !ich_vmcr_el2.VENG1) { 252813760Sjairo.balart@metempsy.com ich_misr_el2.VGrp1D = 1; 252913760Sjairo.balart@metempsy.com } 253013760Sjairo.balart@metempsy.com 253113760Sjairo.balart@metempsy.com return ich_misr_el2; 253213531Sjairo.balart@metempsy.com} 253313531Sjairo.balart@metempsy.com 253414237Sgiacomo.travaglini@arm.comRegVal 253514237Sgiacomo.travaglini@arm.comGicv3CPUInterface::bpr1(Gicv3::GroupId group) 253614237Sgiacomo.travaglini@arm.com{ 253714237Sgiacomo.travaglini@arm.com bool hcr_imo = getHCREL2IMO(); 253814237Sgiacomo.travaglini@arm.com if ((currEL() == EL1) && !inSecureState() && hcr_imo) { 253914237Sgiacomo.travaglini@arm.com return readMiscReg(MISCREG_ICV_BPR1_EL1); 254014237Sgiacomo.travaglini@arm.com } 254114237Sgiacomo.travaglini@arm.com 254214237Sgiacomo.travaglini@arm.com RegVal bpr = 0; 254314237Sgiacomo.travaglini@arm.com 254414237Sgiacomo.travaglini@arm.com if (group == Gicv3::G1S) { 254514237Sgiacomo.travaglini@arm.com ICC_CTLR_EL1 icc_ctlr_el1_s = 254614237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S); 254714237Sgiacomo.travaglini@arm.com 254814237Sgiacomo.travaglini@arm.com if (!isEL3OrMon() && icc_ctlr_el1_s.CBPR) { 254914237Sgiacomo.travaglini@arm.com bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1); 255014237Sgiacomo.travaglini@arm.com } else { 255114237Sgiacomo.travaglini@arm.com bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_S); 255214237Sgiacomo.travaglini@arm.com bpr = bpr > GIC_MIN_BPR ? bpr : GIC_MIN_BPR; 255314237Sgiacomo.travaglini@arm.com } 255414237Sgiacomo.travaglini@arm.com } else if (group == Gicv3::G1NS) { 255514237Sgiacomo.travaglini@arm.com ICC_CTLR_EL1 icc_ctlr_el1_ns = 255614237Sgiacomo.travaglini@arm.com isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS); 255714237Sgiacomo.travaglini@arm.com 255814237Sgiacomo.travaglini@arm.com // Check if EL3 is implemented and this is a non secure accesses at 255914237Sgiacomo.travaglini@arm.com // EL1 and EL2 256014237Sgiacomo.travaglini@arm.com if (haveEL(EL3) && !isEL3OrMon() && icc_ctlr_el1_ns.CBPR) { 256114237Sgiacomo.travaglini@arm.com // Reads return BPR0 + 1 saturated to 7, WI 256214237Sgiacomo.travaglini@arm.com bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1) + 1; 256314237Sgiacomo.travaglini@arm.com bpr = bpr < 7 ? bpr : 7; 256414237Sgiacomo.travaglini@arm.com } else { 256514237Sgiacomo.travaglini@arm.com bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1_NS); 256614237Sgiacomo.travaglini@arm.com bpr = bpr > GIC_MIN_BPR_NS ? bpr : GIC_MIN_BPR_NS; 256714237Sgiacomo.travaglini@arm.com } 256814237Sgiacomo.travaglini@arm.com } else { 256914237Sgiacomo.travaglini@arm.com panic("Should be used with G1S and G1NS only\n"); 257014237Sgiacomo.travaglini@arm.com } 257114237Sgiacomo.travaglini@arm.com 257214237Sgiacomo.travaglini@arm.com return bpr; 257314237Sgiacomo.travaglini@arm.com} 257414237Sgiacomo.travaglini@arm.com 257513531Sjairo.balart@metempsy.comvoid 257613531Sjairo.balart@metempsy.comGicv3CPUInterface::serialize(CheckpointOut & cp) const 257713531Sjairo.balart@metempsy.com{ 257813531Sjairo.balart@metempsy.com SERIALIZE_SCALAR(hppi.intid); 257913531Sjairo.balart@metempsy.com SERIALIZE_SCALAR(hppi.prio); 258013531Sjairo.balart@metempsy.com SERIALIZE_ENUM(hppi.group); 258113531Sjairo.balart@metempsy.com} 258213531Sjairo.balart@metempsy.com 258313531Sjairo.balart@metempsy.comvoid 258413531Sjairo.balart@metempsy.comGicv3CPUInterface::unserialize(CheckpointIn & cp) 258513531Sjairo.balart@metempsy.com{ 258613531Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(hppi.intid); 258713531Sjairo.balart@metempsy.com UNSERIALIZE_SCALAR(hppi.prio); 258813531Sjairo.balart@metempsy.com UNSERIALIZE_ENUM(hppi.group); 258913531Sjairo.balart@metempsy.com} 2590