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13611:c8b7847b4171 |
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19-Nov-2018 |
Gabe Black <gabeblack@google.com> |
arch: cpu: Rename *FloatRegBits* to *FloatReg*.
Now that there's no plain FloatReg, there's no reason to distinguish FloatRegBits with a special suffix since it's the only way to read or write FP registers.
Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded Reviewed-on: https://gem5-review.googlesource.com/c/14460 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
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13500:6e0a2a7c6d8c |
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19-Nov-2018 |
Gabe Black <gabeblack@google.com> |
arch, cpu: Remove float type accessors.
Use the binary accessors instead.
Change-Id: Iff1877e92c79df02b3d13635391a8c2f025776a2 Reviewed-on: https://gem5-review.googlesource.com/c/14457 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
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12642:d0ce95094a54 |
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14-Mar-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Add support for Tarmac trace generation
This patch introduces the TarmacTracer: an instruction tracer which allows to dump a gem5 execution trace in Tarmac format [1]. The new tracer is supporting either Tarmac and TarmacV8 format specifications. Not every traceable information has been implemented:
Implemented Trace Type: Instruction Trace Register Trace Processor Memory Access Trace
Unimplemented Trace Type: Program Flow Trace Event Trace Memory Bus Trace
[1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format
Change-Id: I8799d8e5852e868673f728971db3fe8c63961f5e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9382 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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