112642Sgiacomo.travaglini@arm.com/* 212642Sgiacomo.travaglini@arm.com * Copyright (c) 2017-2018 ARM Limited 312642Sgiacomo.travaglini@arm.com * All rights reserved 412642Sgiacomo.travaglini@arm.com * 512642Sgiacomo.travaglini@arm.com * The license below extends only to copyright in the software and shall 612642Sgiacomo.travaglini@arm.com * not be construed as granting a license to any other intellectual 712642Sgiacomo.travaglini@arm.com * property including but not limited to intellectual property relating 812642Sgiacomo.travaglini@arm.com * to a hardware implementation of the functionality of the software 912642Sgiacomo.travaglini@arm.com * licensed hereunder. You may use the software subject to the license 1012642Sgiacomo.travaglini@arm.com * terms below provided that you ensure that this notice is replicated 1112642Sgiacomo.travaglini@arm.com * unmodified and in its entirety in all distributions of the software, 1212642Sgiacomo.travaglini@arm.com * modified or unmodified, in source code or in binary form. 1312642Sgiacomo.travaglini@arm.com * 1412642Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 1512642Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 1612642Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 1712642Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 1812642Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 1912642Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 2012642Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 2112642Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 2212642Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 2312642Sgiacomo.travaglini@arm.com * this software without specific prior written permission. 2412642Sgiacomo.travaglini@arm.com * 2512642Sgiacomo.travaglini@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2612642Sgiacomo.travaglini@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2712642Sgiacomo.travaglini@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2812642Sgiacomo.travaglini@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2912642Sgiacomo.travaglini@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3012642Sgiacomo.travaglini@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3112642Sgiacomo.travaglini@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3212642Sgiacomo.travaglini@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3312642Sgiacomo.travaglini@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3412642Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3512642Sgiacomo.travaglini@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3612642Sgiacomo.travaglini@arm.com * 3712642Sgiacomo.travaglini@arm.com * Authors: Giacomo Travaglini 3812642Sgiacomo.travaglini@arm.com */ 3912642Sgiacomo.travaglini@arm.com 4012642Sgiacomo.travaglini@arm.com/** 4112642Sgiacomo.travaglini@arm.com * @file: The file contains the informations used to generate records 4212642Sgiacomo.travaglini@arm.com * for the pre-ARMv8 cores. 4312642Sgiacomo.travaglini@arm.com */ 4412642Sgiacomo.travaglini@arm.com 4512642Sgiacomo.travaglini@arm.com#ifndef __ARCH_ARM_TRACERS_TARMAC_RECORD_HH__ 4612642Sgiacomo.travaglini@arm.com#define __ARCH_ARM_TRACERS_TARMAC_RECORD_HH__ 4712642Sgiacomo.travaglini@arm.com 4812642Sgiacomo.travaglini@arm.com#include "arch/arm/tracers/tarmac_base.hh" 4912642Sgiacomo.travaglini@arm.com#include "base/printable.hh" 5012642Sgiacomo.travaglini@arm.com#include "config/the_isa.hh" 5112642Sgiacomo.travaglini@arm.com#include "cpu/reg_class.hh" 5212642Sgiacomo.travaglini@arm.com#include "cpu/static_inst.hh" 5312642Sgiacomo.travaglini@arm.com 5412642Sgiacomo.travaglini@arm.comnamespace Trace { 5512642Sgiacomo.travaglini@arm.com 5612642Sgiacomo.travaglini@arm.comclass TarmacContext; 5712642Sgiacomo.travaglini@arm.com 5812642Sgiacomo.travaglini@arm.comclass TarmacTracer; 5912642Sgiacomo.travaglini@arm.com 6012642Sgiacomo.travaglini@arm.com/** 6112642Sgiacomo.travaglini@arm.com * Returns the string representation of the instruction set being 6212642Sgiacomo.travaglini@arm.com * currently run according to the Tarmac format. 6312642Sgiacomo.travaglini@arm.com * 6412642Sgiacomo.travaglini@arm.com * @param isetstate: enum variable (ISetState) specifying an ARM 6512642Sgiacomo.travaglini@arm.com * instruction set. 6612642Sgiacomo.travaglini@arm.com * @return instruction set in string format. 6712642Sgiacomo.travaglini@arm.com */ 6812642Sgiacomo.travaglini@arm.comstd::string 6912642Sgiacomo.travaglini@arm.comiSetStateToStr(TarmacBaseRecord::ISetState isetstate); 7012642Sgiacomo.travaglini@arm.com 7112642Sgiacomo.travaglini@arm.com/** 7212642Sgiacomo.travaglini@arm.com * Returns the string representation of the ARM Operating Mode 7312642Sgiacomo.travaglini@arm.com * (CPSR.M[3:0] field) according to the Tarmac format. 7412642Sgiacomo.travaglini@arm.com * 7512642Sgiacomo.travaglini@arm.com * @param opMode: ARM operating mode. 7612642Sgiacomo.travaglini@arm.com * @return operating mode in string format. 7712642Sgiacomo.travaglini@arm.com */ 7812642Sgiacomo.travaglini@arm.comstd::string 7912642Sgiacomo.travaglini@arm.comopModeToStr(ArmISA::OperatingMode opMode); 8012642Sgiacomo.travaglini@arm.com 8112642Sgiacomo.travaglini@arm.com/** 8212642Sgiacomo.travaglini@arm.com * TarmacTracer Record: 8312642Sgiacomo.travaglini@arm.com * Record generated by the TarmacTracer for every executed instruction. 8412642Sgiacomo.travaglini@arm.com * The record is composed by a set of entries, matching the tracing 8512642Sgiacomo.travaglini@arm.com * capabilities provided by the Tarmac specifications: 8612642Sgiacomo.travaglini@arm.com * 8712642Sgiacomo.travaglini@arm.com * - Instruction Entry 8812642Sgiacomo.travaglini@arm.com * - Register Entry 8912642Sgiacomo.travaglini@arm.com * - Memory Entry 9012642Sgiacomo.travaglini@arm.com */ 9112642Sgiacomo.travaglini@arm.comclass TarmacTracerRecord : public TarmacBaseRecord 9212642Sgiacomo.travaglini@arm.com{ 9312642Sgiacomo.travaglini@arm.com public: 9412642Sgiacomo.travaglini@arm.com /** Instruction Entry */ 9512642Sgiacomo.travaglini@arm.com struct TraceInstEntry: public InstEntry, Printable 9612642Sgiacomo.travaglini@arm.com { 9712642Sgiacomo.travaglini@arm.com TraceInstEntry(const TarmacContext& tarmCtx, bool predicate); 9812642Sgiacomo.travaglini@arm.com 9912642Sgiacomo.travaglini@arm.com virtual void print(std::ostream& outs, 10012642Sgiacomo.travaglini@arm.com int verbosity = 0, 10112642Sgiacomo.travaglini@arm.com const std::string &prefix = "") const override; 10212642Sgiacomo.travaglini@arm.com 10312642Sgiacomo.travaglini@arm.com protected: 10412642Sgiacomo.travaglini@arm.com /** Number of instructions being traced */ 10512642Sgiacomo.travaglini@arm.com static uint64_t instCount; 10612642Sgiacomo.travaglini@arm.com 10712642Sgiacomo.travaglini@arm.com /** True if instruction is executed in secure mode */ 10812642Sgiacomo.travaglini@arm.com bool secureMode; 10912642Sgiacomo.travaglini@arm.com /** 11012642Sgiacomo.travaglini@arm.com * Instruction size: 11112642Sgiacomo.travaglini@arm.com * 16 for 16-bit Thumb Instruction 11212642Sgiacomo.travaglini@arm.com * 32 otherwise (ARM and BigThumb) 11312642Sgiacomo.travaglini@arm.com */ 11412642Sgiacomo.travaglini@arm.com uint8_t instSize; 11512642Sgiacomo.travaglini@arm.com }; 11612642Sgiacomo.travaglini@arm.com 11712642Sgiacomo.travaglini@arm.com /** Register Entry */ 11812642Sgiacomo.travaglini@arm.com struct TraceRegEntry: public RegEntry, Printable 11912642Sgiacomo.travaglini@arm.com { 12012642Sgiacomo.travaglini@arm.com public: 12112642Sgiacomo.travaglini@arm.com TraceRegEntry(const TarmacContext& tarmCtx, const RegId& reg); 12212642Sgiacomo.travaglini@arm.com 12312642Sgiacomo.travaglini@arm.com /** 12412642Sgiacomo.travaglini@arm.com * This updates the register entry using the update table. It is 12512642Sgiacomo.travaglini@arm.com * a required step after the register entry generation. 12612642Sgiacomo.travaglini@arm.com * If unupdated, the entry will be marked as invalid. 12712642Sgiacomo.travaglini@arm.com * The entry update cannot be done automatically at TraceRegEntry 12812642Sgiacomo.travaglini@arm.com * construction: the entries are extended by consequent Tarmac 12912642Sgiacomo.travaglini@arm.com * Tracer versions (like V8), and virtual functions should 13012642Sgiacomo.travaglini@arm.com * be avoided during construction. 13112642Sgiacomo.travaglini@arm.com */ 13212642Sgiacomo.travaglini@arm.com void update(const TarmacContext& tarmCtx); 13312642Sgiacomo.travaglini@arm.com 13412642Sgiacomo.travaglini@arm.com virtual void print(std::ostream& outs, 13512642Sgiacomo.travaglini@arm.com int verbosity = 0, 13612642Sgiacomo.travaglini@arm.com const std::string &prefix = "") const override; 13712642Sgiacomo.travaglini@arm.com 13812642Sgiacomo.travaglini@arm.com protected: 13912642Sgiacomo.travaglini@arm.com /** Register update functions. */ 14012642Sgiacomo.travaglini@arm.com virtual void 14112642Sgiacomo.travaglini@arm.com updateMisc(const TarmacContext& tarmCtx, RegIndex regRelIdx); 14212642Sgiacomo.travaglini@arm.com 14312642Sgiacomo.travaglini@arm.com virtual void 14412642Sgiacomo.travaglini@arm.com updateCC(const TarmacContext& tarmCtx, RegIndex regRelIdx); 14512642Sgiacomo.travaglini@arm.com 14612642Sgiacomo.travaglini@arm.com virtual void 14712642Sgiacomo.travaglini@arm.com updateFloat(const TarmacContext& tarmCtx, RegIndex regRelIdx); 14812642Sgiacomo.travaglini@arm.com 14912642Sgiacomo.travaglini@arm.com virtual void 15012642Sgiacomo.travaglini@arm.com updateInt(const TarmacContext& tarmCtx, RegIndex regRelIdx); 15112642Sgiacomo.travaglini@arm.com 15212642Sgiacomo.travaglini@arm.com public: 15312642Sgiacomo.travaglini@arm.com /** True if register entry is valid */ 15412642Sgiacomo.travaglini@arm.com bool regValid; 15512642Sgiacomo.travaglini@arm.com /** Register class */ 15612642Sgiacomo.travaglini@arm.com RegClass regClass; 15712642Sgiacomo.travaglini@arm.com /** Register arch number */ 15812642Sgiacomo.travaglini@arm.com RegIndex regRel; 15912642Sgiacomo.travaglini@arm.com /** Register name to be printed */ 16012642Sgiacomo.travaglini@arm.com std::string regName; 16112642Sgiacomo.travaglini@arm.com }; 16212642Sgiacomo.travaglini@arm.com 16312642Sgiacomo.travaglini@arm.com /** Memory Entry */ 16412642Sgiacomo.travaglini@arm.com struct TraceMemEntry: public MemEntry, Printable 16512642Sgiacomo.travaglini@arm.com { 16612642Sgiacomo.travaglini@arm.com public: 16712642Sgiacomo.travaglini@arm.com TraceMemEntry(const TarmacContext& tarmCtx, 16812642Sgiacomo.travaglini@arm.com uint8_t _size, Addr _addr, uint64_t _data); 16912642Sgiacomo.travaglini@arm.com 17012642Sgiacomo.travaglini@arm.com virtual void print(std::ostream& outs, 17112642Sgiacomo.travaglini@arm.com int verbosity = 0, 17212642Sgiacomo.travaglini@arm.com const std::string &prefix = "") const override; 17312642Sgiacomo.travaglini@arm.com 17412642Sgiacomo.travaglini@arm.com protected: 17512642Sgiacomo.travaglini@arm.com /** True if memory access is a load */ 17612642Sgiacomo.travaglini@arm.com bool loadAccess; 17712642Sgiacomo.travaglini@arm.com }; 17812642Sgiacomo.travaglini@arm.com 17912642Sgiacomo.travaglini@arm.com public: 18012642Sgiacomo.travaglini@arm.com TarmacTracerRecord(Tick _when, ThreadContext *_thread, 18113915Sgabeblack@google.com const StaticInstPtr _staticInst, ArmISA::PCState _pc, 18212642Sgiacomo.travaglini@arm.com TarmacTracer& _tracer, 18312642Sgiacomo.travaglini@arm.com const StaticInstPtr _macroStaticInst = NULL); 18412642Sgiacomo.travaglini@arm.com 18512642Sgiacomo.travaglini@arm.com virtual void dump() override; 18612642Sgiacomo.travaglini@arm.com 18712642Sgiacomo.travaglini@arm.com using InstPtr = std::unique_ptr<TraceInstEntry>; 18812642Sgiacomo.travaglini@arm.com using MemPtr = std::unique_ptr<TraceMemEntry>; 18912642Sgiacomo.travaglini@arm.com using RegPtr = std::unique_ptr<TraceRegEntry>; 19012642Sgiacomo.travaglini@arm.com 19112642Sgiacomo.travaglini@arm.com protected: 19212642Sgiacomo.travaglini@arm.com /** Generates an Entry for the executed instruction. */ 19312642Sgiacomo.travaglini@arm.com virtual void addInstEntry(std::vector<InstPtr>& queue, 19412642Sgiacomo.travaglini@arm.com const TarmacContext& ptr); 19512642Sgiacomo.travaglini@arm.com 19612642Sgiacomo.travaglini@arm.com /** Generates an Entry for every triggered memory access */ 19712642Sgiacomo.travaglini@arm.com virtual void addMemEntry(std::vector<MemPtr>& queue, 19812642Sgiacomo.travaglini@arm.com const TarmacContext& ptr); 19912642Sgiacomo.travaglini@arm.com 20012642Sgiacomo.travaglini@arm.com /** Generate an Entry for every register being written. */ 20112642Sgiacomo.travaglini@arm.com virtual void addRegEntry(std::vector<RegPtr>& queue, 20212642Sgiacomo.travaglini@arm.com const TarmacContext& ptr); 20312642Sgiacomo.travaglini@arm.com 20412642Sgiacomo.travaglini@arm.com protected: 20512642Sgiacomo.travaglini@arm.com /** Generate and update a register entry. */ 20612642Sgiacomo.travaglini@arm.com template<typename RegEntry> 20712642Sgiacomo.travaglini@arm.com RegEntry 20812642Sgiacomo.travaglini@arm.com genRegister(const TarmacContext& tarmCtx, const RegId& reg) 20912642Sgiacomo.travaglini@arm.com { 21012642Sgiacomo.travaglini@arm.com RegEntry single_reg(tarmCtx, reg); 21112642Sgiacomo.travaglini@arm.com single_reg.update(tarmCtx); 21212642Sgiacomo.travaglini@arm.com 21312642Sgiacomo.travaglini@arm.com return single_reg; 21412642Sgiacomo.travaglini@arm.com } 21512642Sgiacomo.travaglini@arm.com 21612642Sgiacomo.travaglini@arm.com template<typename RegEntry> 21712642Sgiacomo.travaglini@arm.com void 21812642Sgiacomo.travaglini@arm.com mergeCCEntry(std::vector<RegPtr>& queue, const TarmacContext& tarmCtx) 21912642Sgiacomo.travaglini@arm.com { 22012642Sgiacomo.travaglini@arm.com // Find all CC Entries and move them at the end of the queue 22112642Sgiacomo.travaglini@arm.com auto it = std::remove_if( 22212642Sgiacomo.travaglini@arm.com queue.begin(), queue.end(), 22312642Sgiacomo.travaglini@arm.com [] (RegPtr& reg) ->bool { return (reg->regClass == CCRegClass); } 22412642Sgiacomo.travaglini@arm.com ); 22512642Sgiacomo.travaglini@arm.com 22612642Sgiacomo.travaglini@arm.com if (it != queue.end()) { 22712642Sgiacomo.travaglini@arm.com // Remove all CC Entries. 22812642Sgiacomo.travaglini@arm.com queue.erase(it, queue.end()); 22912642Sgiacomo.travaglini@arm.com 23012642Sgiacomo.travaglini@arm.com auto is_cpsr = [] (RegPtr& reg) ->bool 23112642Sgiacomo.travaglini@arm.com { 23212642Sgiacomo.travaglini@arm.com return (reg->regClass == MiscRegClass) && 23312642Sgiacomo.travaglini@arm.com (reg->regRel == ArmISA::MISCREG_CPSR); 23412642Sgiacomo.travaglini@arm.com }; 23512642Sgiacomo.travaglini@arm.com 23612642Sgiacomo.travaglini@arm.com // Looking for the presence of a CPSR register entry. 23712642Sgiacomo.travaglini@arm.com auto cpsr_it = std::find_if( 23812642Sgiacomo.travaglini@arm.com queue.begin(), queue.end(), is_cpsr 23912642Sgiacomo.travaglini@arm.com ); 24012642Sgiacomo.travaglini@arm.com 24112642Sgiacomo.travaglini@arm.com // If CPSR entry not present, generate one 24212642Sgiacomo.travaglini@arm.com if (cpsr_it == queue.end()) { 24312642Sgiacomo.travaglini@arm.com RegId reg(MiscRegClass, ArmISA::MISCREG_CPSR); 24412642Sgiacomo.travaglini@arm.com queue.push_back( 24512642Sgiacomo.travaglini@arm.com m5::make_unique<RegEntry>( 24612642Sgiacomo.travaglini@arm.com genRegister<RegEntry>(tarmCtx, reg)) 24712642Sgiacomo.travaglini@arm.com ); 24812642Sgiacomo.travaglini@arm.com } 24912642Sgiacomo.travaglini@arm.com } 25012642Sgiacomo.travaglini@arm.com } 25112642Sgiacomo.travaglini@arm.com 25212642Sgiacomo.travaglini@arm.com /** Flush queues to the trace output */ 25312642Sgiacomo.travaglini@arm.com template<typename Queue> 25412642Sgiacomo.travaglini@arm.com void flushQueues(Queue& queue); 25512642Sgiacomo.travaglini@arm.com template<typename Queue, typename... Args> 25612642Sgiacomo.travaglini@arm.com void flushQueues(Queue& queue, Args & ... args); 25712642Sgiacomo.travaglini@arm.com 25812642Sgiacomo.travaglini@arm.com protected: 25912642Sgiacomo.travaglini@arm.com /** Reference to tracer */ 26012642Sgiacomo.travaglini@arm.com TarmacTracer& tracer; 26112642Sgiacomo.travaglini@arm.com}; 26212642Sgiacomo.travaglini@arm.com 26312642Sgiacomo.travaglini@arm.com} // namespace Trace 26412642Sgiacomo.travaglini@arm.com 26512642Sgiacomo.travaglini@arm.com#endif // __ARCH_ARM_TRACERS_TARMAC_RECORD_HH__ 266